1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2dfab439fSBenoit Cousson /* 3dfab439fSBenoit Cousson * OMAP54xx CM2 instance offset macros 4dfab439fSBenoit Cousson * 5*83bf6db0SAlexander A. Klimov * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 6dfab439fSBenoit Cousson * 7dfab439fSBenoit Cousson * Paul Walmsley (paul@pwsan.com) 8dfab439fSBenoit Cousson * Rajendra Nayak (rnayak@ti.com) 9dfab439fSBenoit Cousson * Benoit Cousson (b-cousson@ti.com) 10dfab439fSBenoit Cousson * 11dfab439fSBenoit Cousson * This file is automatically generated from the OMAP hardware databases. 12dfab439fSBenoit Cousson * We respectfully ask that any modifications to this file be coordinated 13dfab439fSBenoit Cousson * with the public linux-omap@vger.kernel.org mailing list and the 14dfab439fSBenoit Cousson * authors above to ensure that the autogeneration scripts are kept 15dfab439fSBenoit Cousson * up-to-date with the file contents. 16dfab439fSBenoit Cousson */ 17dfab439fSBenoit Cousson 18dfab439fSBenoit Cousson #ifndef __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 19dfab439fSBenoit Cousson #define __ARCH_ARM_MACH_OMAP2_CM2_54XX_H 20dfab439fSBenoit Cousson 21dfab439fSBenoit Cousson /* CM2 base address */ 22dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_BASE 0x4a008000 23dfab439fSBenoit Cousson 24dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_REGADDR(inst, reg) \ 25dfab439fSBenoit Cousson OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg)) 26dfab439fSBenoit Cousson 27dfab439fSBenoit Cousson /* CM_CORE instances */ 28dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_OCP_SOCKET_INST 0x0000 29dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CKGEN_INST 0x0100 30dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_COREAON_INST 0x0600 31dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_INST 0x0700 32dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_IVA_INST 0x1200 33dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CAM_INST 0x1300 34dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_DSS_INST 0x1400 35dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_GPU_INST 0x1500 36dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 37dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 38dfab439fSBenoit Cousson 39dfab439fSBenoit Cousson /* CM_CORE clockdomain register offsets (from instance start) */ 40dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 41dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 42dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_L3MAIN2_CDOFFS 0x0100 43dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_IPU_CDOFFS 0x0200 44dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 45dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 46dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_C2C_CDOFFS 0x0500 47dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 48dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 49dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_MIPIEXT_CDOFFS 0x0800 50dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_L4PER_CDOFFS 0x0900 51dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CORE_L4SEC_CDOFFS 0x0a80 52dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 53dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 54dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 55dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 56dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 57dfab439fSBenoit Cousson #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 58dfab439fSBenoit Cousson 59dfab439fSBenoit Cousson #endif 60