1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 24f92bab4SRajendra Nayak /* 34f92bab4SRajendra Nayak * DRA7xx Clock Management register bits 44f92bab4SRajendra Nayak * 5*83bf6db0SAlexander A. Klimov * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com 64f92bab4SRajendra Nayak * 74f92bab4SRajendra Nayak * Generated by code originally written by: 84f92bab4SRajendra Nayak * Paul Walmsley (paul@pwsan.com) 94f92bab4SRajendra Nayak * Rajendra Nayak (rnayak@ti.com) 104f92bab4SRajendra Nayak * Benoit Cousson (b-cousson@ti.com) 114f92bab4SRajendra Nayak * 124f92bab4SRajendra Nayak * This file is automatically generated from the OMAP hardware databases. 134f92bab4SRajendra Nayak * We respectfully ask that any modifications to this file be coordinated 144f92bab4SRajendra Nayak * with the public linux-omap@vger.kernel.org mailing list and the 154f92bab4SRajendra Nayak * authors above to ensure that the autogeneration scripts are kept 164f92bab4SRajendra Nayak * up-to-date with the file contents. 174f92bab4SRajendra Nayak */ 184f92bab4SRajendra Nayak 194f92bab4SRajendra Nayak #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H 204f92bab4SRajendra Nayak #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H 214f92bab4SRajendra Nayak 224f92bab4SRajendra Nayak #define DRA7XX_ATL_STATDEP_SHIFT 30 234f92bab4SRajendra Nayak #define DRA7XX_CAM_STATDEP_SHIFT 9 244f92bab4SRajendra Nayak #define DRA7XX_DSP1_STATDEP_SHIFT 1 254f92bab4SRajendra Nayak #define DRA7XX_DSP2_STATDEP_SHIFT 18 264f92bab4SRajendra Nayak #define DRA7XX_DSS_STATDEP_SHIFT 8 274f92bab4SRajendra Nayak #define DRA7XX_EMIF_STATDEP_SHIFT 4 284f92bab4SRajendra Nayak #define DRA7XX_EVE1_STATDEP_SHIFT 19 294f92bab4SRajendra Nayak #define DRA7XX_EVE2_STATDEP_SHIFT 20 304f92bab4SRajendra Nayak #define DRA7XX_EVE3_STATDEP_SHIFT 21 314f92bab4SRajendra Nayak #define DRA7XX_EVE4_STATDEP_SHIFT 22 324f92bab4SRajendra Nayak #define DRA7XX_GMAC_STATDEP_SHIFT 25 334f92bab4SRajendra Nayak #define DRA7XX_GPU_STATDEP_SHIFT 10 344f92bab4SRajendra Nayak #define DRA7XX_IPU1_STATDEP_SHIFT 23 354f92bab4SRajendra Nayak #define DRA7XX_IPU2_STATDEP_SHIFT 0 364f92bab4SRajendra Nayak #define DRA7XX_IPU_STATDEP_SHIFT 24 374f92bab4SRajendra Nayak #define DRA7XX_IVA_STATDEP_SHIFT 2 384f92bab4SRajendra Nayak #define DRA7XX_L3INIT_STATDEP_SHIFT 7 394f92bab4SRajendra Nayak #define DRA7XX_L3MAIN1_STATDEP_SHIFT 5 404f92bab4SRajendra Nayak #define DRA7XX_L4CFG_STATDEP_SHIFT 12 414f92bab4SRajendra Nayak #define DRA7XX_L4PER2_STATDEP_SHIFT 26 424f92bab4SRajendra Nayak #define DRA7XX_L4PER3_STATDEP_SHIFT 27 434f92bab4SRajendra Nayak #define DRA7XX_L4PER_STATDEP_SHIFT 13 444f92bab4SRajendra Nayak #define DRA7XX_L4SEC_STATDEP_SHIFT 14 454f92bab4SRajendra Nayak #define DRA7XX_PCIE_STATDEP_SHIFT 29 464f92bab4SRajendra Nayak #define DRA7XX_VPE_STATDEP_SHIFT 28 474f92bab4SRajendra Nayak #define DRA7XX_WKUPAON_STATDEP_SHIFT 15 484f92bab4SRajendra Nayak #endif 49