xref: /openbmc/linux/arch/arm/mach-omap2/clock.c (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2543d9378SPaul Walmsley /*
3543d9378SPaul Walmsley  *  linux/arch/arm/mach-omap2/clock.c
4543d9378SPaul Walmsley  *
5a16e9703STony Lindgren  *  Copyright (C) 2005-2008 Texas Instruments, Inc.
68c34974aSPaul Walmsley  *  Copyright (C) 2004-2010 Nokia Corporation
7a16e9703STony Lindgren  *
8a16e9703STony Lindgren  *  Contacts:
9543d9378SPaul Walmsley  *  Richard Woodruff <r-woodruff2@ti.com>
10543d9378SPaul Walmsley  *  Paul Walmsley
11543d9378SPaul Walmsley  */
12543d9378SPaul Walmsley #undef DEBUG
13543d9378SPaul Walmsley 
14543d9378SPaul Walmsley #include <linux/kernel.h>
151fe9be82SPaul Walmsley #include <linux/export.h>
16543d9378SPaul Walmsley #include <linux/list.h>
17543d9378SPaul Walmsley #include <linux/errno.h>
184d30e82cSPaul Walmsley #include <linux/err.h>
194d30e82cSPaul Walmsley #include <linux/delay.h>
20f5b00f6fSStephen Boyd #include <linux/clk.h>
2132cc0021SMike Turquette #include <linux/clk-provider.h>
22fced80c7SRussell King #include <linux/io.h>
23fbd3bdb2SRussell King #include <linux/bitops.h>
249f029b15STero Kristo #include <linux/of_address.h>
255e7c58dcSJean Pihet #include <asm/cpu.h>
26dbc04161STony Lindgren 
27dbc04161STony Lindgren #include <trace/events/power.h>
28dbc04161STony Lindgren 
29dbc04161STony Lindgren #include "soc.h"
30dbc04161STony Lindgren #include "clockdomain.h"
31543d9378SPaul Walmsley #include "clock.h"
32c4ceedcbSPaul Walmsley #include "cm.h"
33ff4ae5d9SPaul Walmsley #include "cm2xxx.h"
34ff4ae5d9SPaul Walmsley #include "cm3xxx.h"
35543d9378SPaul Walmsley #include "cm-regbits-24xx.h"
36543d9378SPaul Walmsley #include "cm-regbits-34xx.h"
37c4ceedcbSPaul Walmsley #include "common.h"
38c4ceedcbSPaul Walmsley 
3999541195SAfzal Mohammed /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
40543d9378SPaul Walmsley #define OMAP3430_DPLL_FINT_BAND1_MIN	750000
41a24886e2STero Kristo #define OMAP3430_DPLL_FINT_BAND1_MAX	2100000
42a24886e2STero Kristo #define OMAP3430_DPLL_FINT_BAND2_MIN	7500000
43a24886e2STero Kristo #define OMAP3430_DPLL_FINT_BAND2_MAX	21000000
44a24886e2STero Kristo 
45a24886e2STero Kristo /*
46a24886e2STero Kristo  * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
47a24886e2STero Kristo  * From device data manual section 4.3 "DPLL and DLL Specifications".
48a24886e2STero Kristo  */
49a24886e2STero Kristo #define OMAP3PLUS_DPLL_FINT_MIN		32000
50a24886e2STero Kristo #define OMAP3PLUS_DPLL_FINT_MAX		52000000
51a24886e2STero Kristo 
52a24886e2STero Kristo struct ti_clk_ll_ops omap_clk_ll_ops = {
53a24886e2STero Kristo 	.clkdm_clk_enable = clkdm_clk_enable,
546c0afb50STero Kristo 	.clkdm_clk_disable = clkdm_clk_disable,
559a356d62STero Kristo 	.clkdm_lookup = clkdm_lookup,
569a356d62STero Kristo 	.cm_wait_module_ready = omap_cm_wait_module_ready,
57b6f27b2dSTero Kristo 	.cm_split_idlest_reg = cm_split_idlest_reg,
58192383d8STero Kristo };
59192383d8STero Kristo 
609f029b15STero Kristo /**
619f029b15STero Kristo  * omap2_clk_setup_ll_ops - setup clock driver low-level ops
629f029b15STero Kristo  *
63e9e63088STero Kristo  * Sets up clock driver low-level platform ops. These are needed
64e9e63088STero Kristo  * for register accesses and various other misc platform operations.
65e9e63088STero Kristo  * Returns 0 on success, -EBUSY if low level ops have been registered
66e9e63088STero Kristo  * already.
67e9e63088STero Kristo  */
omap2_clk_setup_ll_ops(void)68e9e63088STero Kristo int __init omap2_clk_setup_ll_ops(void)
69e9e63088STero Kristo {
70e9e63088STero Kristo 	return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
71e9e63088STero Kristo }
72e9e63088STero Kristo 
73e9e63088STero Kristo /*
74e9e63088STero Kristo  * OMAP2+ specific clock functions
7532cc0021SMike Turquette  */
7630962d9dSPaul Walmsley 
7730962d9dSPaul Walmsley /**
78543d9378SPaul Walmsley  * ti_clk_init_features - init clock features struct for the SoC
798111e010STero Kristo  *
808111e010STero Kristo  * Initializes the clock features struct based on the SoC type.
818111e010STero Kristo  */
ti_clk_init_features(void)828111e010STero Kristo void __init ti_clk_init_features(void)
838111e010STero Kristo {
848111e010STero Kristo 	struct ti_clk_features features = { 0 };
858111e010STero Kristo 	/* Fint setup for DPLLs */
86f3b19aa5STero Kristo 	if (cpu_is_omap3430()) {
87a24886e2STero Kristo 		features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
88a24886e2STero Kristo 		features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
89f3b19aa5STero Kristo 		features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
90f3b19aa5STero Kristo 		features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
91f3b19aa5STero Kristo 	} else {
92f3b19aa5STero Kristo 		features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
93a24886e2STero Kristo 		features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
94f3b19aa5STero Kristo 	}
95f3b19aa5STero Kristo 
96a24886e2STero Kristo 	/* Bypass value setup for DPLLs */
97512d91cbSTero Kristo 	if (cpu_is_omap24xx()) {
98512d91cbSTero Kristo 		features.dpll_bypass_vals |=
99512d91cbSTero Kristo 			(1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
100f3b19aa5STero Kristo 			(1 << OMAP2XXX_EN_DPLL_FRBYPASS);
101512d91cbSTero Kristo 	} else if (cpu_is_omap34xx()) {
102512d91cbSTero Kristo 		features.dpll_bypass_vals |=
103512d91cbSTero Kristo 			(1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
104f3b19aa5STero Kristo 			(1 << OMAP3XXX_EN_DPLL_FRBYPASS);
105512d91cbSTero Kristo 	} else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
106512d91cbSTero Kristo 		   soc_is_omap54xx() || soc_is_dra7xx()) {
107512d91cbSTero Kristo 		features.dpll_bypass_vals |=
108512d91cbSTero Kristo 			(1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
109f3b19aa5STero Kristo 			(1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
110512d91cbSTero Kristo 			(1 << OMAP4XXX_EN_DPLL_MNBYPASS);
111512d91cbSTero Kristo 	}
112512d91cbSTero Kristo 
113512d91cbSTero Kristo 	/* Jitter correction only available on OMAP343X */
1142337c5b5STero Kristo 	if (cpu_is_omap343x())
1152337c5b5STero Kristo 		features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
1162337c5b5STero Kristo 
117f3b19aa5STero Kristo 	if (omap_type() == OMAP2_DEVICE_TYPE_GP)
118066edb2dSTero Kristo 		features.flags |= TI_CLK_DEVICE_TYPE_GP;
119869decd1STero Kristo 
120869decd1STero Kristo 	/* Idlest value for interface clocks.
121869decd1STero Kristo 	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
122066edb2dSTero Kristo 	 * 34xx reverses this, just to keep us on our toes
123066edb2dSTero Kristo 	 * AM35xx uses both, depending on the module.
124066edb2dSTero Kristo 	 */
125066edb2dSTero Kristo 	if (cpu_is_omap24xx())
126066edb2dSTero Kristo 		features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
127066edb2dSTero Kristo 	else if (cpu_is_omap34xx())
128f3b19aa5STero Kristo 		features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
129066edb2dSTero Kristo 
130f3b19aa5STero Kristo 	/* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
131f0d2f68aSTero Kristo 	if (omap_rev() == OMAP3430_REV_ES1_0)
132f0d2f68aSTero Kristo 		features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
133f0d2f68aSTero Kristo 
134f3b19aa5STero Kristo 	/* Errata I810 for omap5 / dra7 */
135f3b19aa5STero Kristo 	if (soc_is_omap54xx() || soc_is_dra7xx())
13607ff73a9STero Kristo 		features.flags |= TI_CLK_ERRATA_I810;
13707ff73a9STero Kristo 
13807ff73a9STero Kristo 	ti_clk_setup_features(&features);
13907ff73a9STero Kristo }
140f3b19aa5STero Kristo