1 /* 2 * linux/arch/arm/mach-omap1/time.c 3 * 4 * OMAP Timers 5 * 6 * Copyright (C) 2004 Nokia Corporation 7 * Partial timer rewrite and additional dynamic tick timer support by 8 * Tony Lindgen <tony@atomide.com> and 9 * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 10 * 11 * MPU timer code based on the older MPU timer code for OMAP 12 * Copyright (C) 2000 RidgeRun, Inc. 13 * Author: Greg Lonnon <glonnon@ridgerun.com> 14 * 15 * This program is free software; you can redistribute it and/or modify it 16 * under the terms of the GNU General Public License as published by the 17 * Free Software Foundation; either version 2 of the License, or (at your 18 * option) any later version. 19 * 20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 * You should have received a copy of the GNU General Public License along 32 * with this program; if not, write to the Free Software Foundation, Inc., 33 * 675 Mass Ave, Cambridge, MA 02139, USA. 34 */ 35 36 #include <linux/config.h> 37 #include <linux/kernel.h> 38 #include <linux/init.h> 39 #include <linux/delay.h> 40 #include <linux/interrupt.h> 41 #include <linux/sched.h> 42 #include <linux/spinlock.h> 43 44 #include <asm/system.h> 45 #include <asm/hardware.h> 46 #include <asm/io.h> 47 #include <asm/leds.h> 48 #include <asm/irq.h> 49 #include <asm/mach/irq.h> 50 #include <asm/mach/time.h> 51 52 struct sys_timer omap_timer; 53 54 #ifdef CONFIG_OMAP_MPU_TIMER 55 56 /* 57 * --------------------------------------------------------------------------- 58 * MPU timer 59 * --------------------------------------------------------------------------- 60 */ 61 #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE 62 #define OMAP_MPU_TIMER_OFFSET 0x100 63 64 /* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c, 65 * converted to use kHz by Kevin Hilman */ 66 /* convert from cycles(64bits) => nanoseconds (64bits) 67 * basic equation: 68 * ns = cycles / (freq / ns_per_sec) 69 * ns = cycles * (ns_per_sec / freq) 70 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 71 * ns = cycles * (10^6 / cpu_khz) 72 * 73 * Then we use scaling math (suggested by george at mvista.com) to get: 74 * ns = cycles * (10^6 * SC / cpu_khz / SC 75 * ns = cycles * cyc2ns_scale / SC 76 * 77 * And since SC is a constant power of two, we can convert the div 78 * into a shift. 79 * -johnstul at us.ibm.com "math is hard, lets go shopping!" 80 */ 81 static unsigned long cyc2ns_scale; 82 #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */ 83 84 static inline void set_cyc2ns_scale(unsigned long cpu_khz) 85 { 86 cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz; 87 } 88 89 static inline unsigned long long cycles_2_ns(unsigned long long cyc) 90 { 91 return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR; 92 } 93 94 /* 95 * MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs 96 * will break. On P2, the timer count rate is 6.5 MHz after programming PTV 97 * with 0. This divides the 13MHz input by 2, and is undocumented. 98 */ 99 #ifdef CONFIG_MACH_OMAP_PERSEUS2 100 /* REVISIT: This ifdef construct should be replaced by a query to clock 101 * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz. 102 */ 103 #define MPU_TICKS_PER_SEC (13000000 / 2) 104 #else 105 #define MPU_TICKS_PER_SEC (12000000 / 2) 106 #endif 107 108 #define MPU_TIMER_TICK_PERIOD ((MPU_TICKS_PER_SEC / HZ) - 1) 109 110 typedef struct { 111 u32 cntl; /* CNTL_TIMER, R/W */ 112 u32 load_tim; /* LOAD_TIM, W */ 113 u32 read_tim; /* READ_TIM, R */ 114 } omap_mpu_timer_regs_t; 115 116 #define omap_mpu_timer_base(n) \ 117 ((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \ 118 (n)*OMAP_MPU_TIMER_OFFSET)) 119 120 static inline unsigned long omap_mpu_timer_read(int nr) 121 { 122 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 123 return timer->read_tim; 124 } 125 126 static inline void omap_mpu_timer_start(int nr, unsigned long load_val) 127 { 128 volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr); 129 130 timer->cntl = MPU_TIMER_CLOCK_ENABLE; 131 udelay(1); 132 timer->load_tim = load_val; 133 udelay(1); 134 timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST); 135 } 136 137 unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks) 138 { 139 unsigned long long nsec; 140 141 nsec = cycles_2_ns((unsigned long long)nr_ticks); 142 return (unsigned long)nsec / 1000; 143 } 144 145 /* 146 * Last processed system timer interrupt 147 */ 148 static unsigned long omap_mpu_timer_last = 0; 149 150 /* 151 * Returns elapsed usecs since last system timer interrupt 152 */ 153 static unsigned long omap_mpu_timer_gettimeoffset(void) 154 { 155 unsigned long now = 0 - omap_mpu_timer_read(0); 156 unsigned long elapsed = now - omap_mpu_timer_last; 157 158 return omap_mpu_timer_ticks_to_usecs(elapsed); 159 } 160 161 /* 162 * Elapsed time between interrupts is calculated using timer0. 163 * Latency during the interrupt is calculated using timer1. 164 * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz). 165 */ 166 static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id, 167 struct pt_regs *regs) 168 { 169 unsigned long now, latency; 170 171 write_seqlock(&xtime_lock); 172 now = 0 - omap_mpu_timer_read(0); 173 latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1); 174 omap_mpu_timer_last = now - latency; 175 timer_tick(regs); 176 write_sequnlock(&xtime_lock); 177 178 return IRQ_HANDLED; 179 } 180 181 static struct irqaction omap_mpu_timer_irq = { 182 .name = "mpu timer", 183 .flags = SA_INTERRUPT | SA_TIMER, 184 .handler = omap_mpu_timer_interrupt, 185 }; 186 187 static unsigned long omap_mpu_timer1_overflows; 188 static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id, 189 struct pt_regs *regs) 190 { 191 omap_mpu_timer1_overflows++; 192 return IRQ_HANDLED; 193 } 194 195 static struct irqaction omap_mpu_timer1_irq = { 196 .name = "mpu timer1 overflow", 197 .flags = SA_INTERRUPT, 198 .handler = omap_mpu_timer1_interrupt, 199 }; 200 201 static __init void omap_init_mpu_timer(void) 202 { 203 set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000); 204 omap_timer.offset = omap_mpu_timer_gettimeoffset; 205 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); 206 setup_irq(INT_TIMER2, &omap_mpu_timer_irq); 207 omap_mpu_timer_start(0, 0xffffffff); 208 omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD); 209 } 210 211 /* 212 * Scheduler clock - returns current time in nanosec units. 213 */ 214 unsigned long long sched_clock(void) 215 { 216 unsigned long ticks = 0 - omap_mpu_timer_read(0); 217 unsigned long long ticks64; 218 219 ticks64 = omap_mpu_timer1_overflows; 220 ticks64 <<= 32; 221 ticks64 |= ticks; 222 223 return cycles_2_ns(ticks64); 224 } 225 #endif /* CONFIG_OMAP_MPU_TIMER */ 226 227 #ifdef CONFIG_OMAP_32K_TIMER 228 229 #ifdef CONFIG_ARCH_OMAP1510 230 #error OMAP 32KHz timer does not currently work on 1510! 231 #endif 232 233 /* 234 * --------------------------------------------------------------------------- 235 * 32KHz OS timer 236 * 237 * This currently works only on 16xx, as 1510 does not have the continuous 238 * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track 239 * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer 240 * on 1510 would be possible, but the timer would not be as accurate as 241 * with the 32KHz synchronized timer. 242 * --------------------------------------------------------------------------- 243 */ 244 #define OMAP_32K_TIMER_BASE 0xfffb9000 245 #define OMAP_32K_TIMER_CR 0x08 246 #define OMAP_32K_TIMER_TVR 0x00 247 #define OMAP_32K_TIMER_TCR 0x04 248 249 #define OMAP_32K_TICKS_PER_HZ (32768 / HZ) 250 #if (32768 % HZ) != 0 251 /* We cannot ignore modulo. 252 * Potential error can be as high as several percent. 253 */ 254 #define OMAP_32K_TICK_MODULO (32768 % HZ) 255 static unsigned modulo_count = 0; /* Counts 1/HZ units */ 256 #endif 257 258 /* 259 * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1 260 * so with HZ = 100, TVR = 327.68. 261 */ 262 #define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1) 263 #define TIMER_32K_SYNCHRONIZED 0xfffbc410 264 265 #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \ 266 (((nr_jiffies) * (clock_rate)) / HZ) 267 268 static inline void omap_32k_timer_write(int val, int reg) 269 { 270 omap_writew(val, reg + OMAP_32K_TIMER_BASE); 271 } 272 273 static inline unsigned long omap_32k_timer_read(int reg) 274 { 275 return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff; 276 } 277 278 /* 279 * The 32KHz synchronized timer is an additional timer on 16xx. 280 * It is always running. 281 */ 282 static inline unsigned long omap_32k_sync_timer_read(void) 283 { 284 return omap_readl(TIMER_32K_SYNCHRONIZED); 285 } 286 287 static inline void omap_32k_timer_start(unsigned long load_val) 288 { 289 omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR); 290 omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR); 291 } 292 293 static inline void omap_32k_timer_stop(void) 294 { 295 omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR); 296 } 297 298 /* 299 * Rounds down to nearest usec 300 */ 301 static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k) 302 { 303 return (ticks_32k * 5*5*5*5*5*5) >> 9; 304 } 305 306 static unsigned long omap_32k_last_tick = 0; 307 308 /* 309 * Returns elapsed usecs since last 32k timer interrupt 310 */ 311 static unsigned long omap_32k_timer_gettimeoffset(void) 312 { 313 unsigned long now = omap_32k_sync_timer_read(); 314 return omap_32k_ticks_to_usecs(now - omap_32k_last_tick); 315 } 316 317 /* 318 * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this 319 * function is also called from other interrupts to remove latency 320 * issues with dynamic tick. In the dynamic tick case, we need to lock 321 * with irqsave. 322 */ 323 static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id, 324 struct pt_regs *regs) 325 { 326 unsigned long flags; 327 unsigned long now; 328 329 write_seqlock_irqsave(&xtime_lock, flags); 330 now = omap_32k_sync_timer_read(); 331 332 while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) { 333 #ifdef OMAP_32K_TICK_MODULO 334 /* Modulo addition may put omap_32k_last_tick ahead of now 335 * and cause unwanted repetition of the while loop. 336 */ 337 if (unlikely(now - omap_32k_last_tick == ~0)) 338 break; 339 340 modulo_count += OMAP_32K_TICK_MODULO; 341 if (modulo_count > HZ) { 342 ++omap_32k_last_tick; 343 modulo_count -= HZ; 344 } 345 #endif 346 omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ; 347 timer_tick(regs); 348 } 349 350 /* Restart timer so we don't drift off due to modulo or dynamic tick. 351 * By default we program the next timer to be continuous to avoid 352 * latencies during high system load. During dynamic tick operation the 353 * continuous timer can be overridden from pm_idle to be longer. 354 */ 355 omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now); 356 write_sequnlock_irqrestore(&xtime_lock, flags); 357 358 return IRQ_HANDLED; 359 } 360 361 #ifdef CONFIG_NO_IDLE_HZ 362 /* 363 * Programs the next timer interrupt needed. Called when dynamic tick is 364 * enabled, and to reprogram the ticks to skip from pm_idle. Note that 365 * we can keep the timer continuous, and don't need to set it to run in 366 * one-shot mode. This is because the timer will get reprogrammed again 367 * after next interrupt. 368 */ 369 void omap_32k_timer_reprogram(unsigned long next_tick) 370 { 371 omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1); 372 } 373 374 static struct irqaction omap_32k_timer_irq; 375 extern struct timer_update_handler timer_update; 376 377 static int omap_32k_timer_enable_dyn_tick(void) 378 { 379 /* No need to reprogram timer, just use the next interrupt */ 380 return 0; 381 } 382 383 static int omap_32k_timer_disable_dyn_tick(void) 384 { 385 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); 386 return 0; 387 } 388 389 static struct dyn_tick_timer omap_dyn_tick_timer = { 390 .enable = omap_32k_timer_enable_dyn_tick, 391 .disable = omap_32k_timer_disable_dyn_tick, 392 .reprogram = omap_32k_timer_reprogram, 393 .handler = omap_32k_timer_interrupt, 394 }; 395 #endif /* CONFIG_NO_IDLE_HZ */ 396 397 static struct irqaction omap_32k_timer_irq = { 398 .name = "32KHz timer", 399 .flags = SA_INTERRUPT | SA_TIMER, 400 .handler = omap_32k_timer_interrupt, 401 }; 402 403 static __init void omap_init_32k_timer(void) 404 { 405 406 #ifdef CONFIG_NO_IDLE_HZ 407 omap_timer.dyn_tick = &omap_dyn_tick_timer; 408 #endif 409 410 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); 411 omap_timer.offset = omap_32k_timer_gettimeoffset; 412 omap_32k_last_tick = omap_32k_sync_timer_read(); 413 omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD); 414 } 415 #endif /* CONFIG_OMAP_32K_TIMER */ 416 417 /* 418 * --------------------------------------------------------------------------- 419 * Timer initialization 420 * --------------------------------------------------------------------------- 421 */ 422 static void __init omap_timer_init(void) 423 { 424 #if defined(CONFIG_OMAP_MPU_TIMER) 425 omap_init_mpu_timer(); 426 #elif defined(CONFIG_OMAP_32K_TIMER) 427 omap_init_32k_timer(); 428 #else 429 #error No system timer selected in Kconfig! 430 #endif 431 } 432 433 struct sys_timer omap_timer = { 434 .init = omap_timer_init, 435 .offset = NULL, /* Initialized later */ 436 }; 437