1*7e0a9e62SArnd Bergmann /* SPDX-License-Identifier: GPL-2.0-or-later */
2*7e0a9e62SArnd Bergmann /*
3*7e0a9e62SArnd Bergmann * Table of the Omap register configurations for the FUNC_MUX and
4*7e0a9e62SArnd Bergmann * PULL_DWN combinations.
5*7e0a9e62SArnd Bergmann *
6*7e0a9e62SArnd Bergmann * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7*7e0a9e62SArnd Bergmann * Copyright (C) 2003 - 2008 Nokia Corporation
8*7e0a9e62SArnd Bergmann *
9*7e0a9e62SArnd Bergmann * Written by Tony Lindgren
10*7e0a9e62SArnd Bergmann *
11*7e0a9e62SArnd Bergmann * NOTE: Please use the following naming style for new pin entries.
12*7e0a9e62SArnd Bergmann * For example, W8_1610_MMC2_DAT0, where:
13*7e0a9e62SArnd Bergmann * - W8 = ball
14*7e0a9e62SArnd Bergmann * - 1610 = 1510 or 1610, none if common for both 1510 and 1610
15*7e0a9e62SArnd Bergmann * - MMC2_DAT0 = function
16*7e0a9e62SArnd Bergmann */
17*7e0a9e62SArnd Bergmann
18*7e0a9e62SArnd Bergmann #ifndef __ASM_ARCH_MUX_H
19*7e0a9e62SArnd Bergmann #define __ASM_ARCH_MUX_H
20*7e0a9e62SArnd Bergmann
21*7e0a9e62SArnd Bergmann #include <linux/soc/ti/omap1-mux.h>
22*7e0a9e62SArnd Bergmann
23*7e0a9e62SArnd Bergmann #define PU_PD_SEL_NA 0 /* No pu_pd reg available */
24*7e0a9e62SArnd Bergmann #define PULL_DWN_CTRL_NA 0 /* No pull-down control needed */
25*7e0a9e62SArnd Bergmann
26*7e0a9e62SArnd Bergmann #ifdef CONFIG_OMAP_MUX_DEBUG
27*7e0a9e62SArnd Bergmann #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
28*7e0a9e62SArnd Bergmann .mux_reg = FUNC_MUX_CTRL_##reg, \
29*7e0a9e62SArnd Bergmann .mask_offset = mode_offset, \
30*7e0a9e62SArnd Bergmann .mask = mode,
31*7e0a9e62SArnd Bergmann
32*7e0a9e62SArnd Bergmann #define PULL_REG(reg, bit, status) .pull_name = "PULL_DWN_CTRL_"#reg, \
33*7e0a9e62SArnd Bergmann .pull_reg = PULL_DWN_CTRL_##reg, \
34*7e0a9e62SArnd Bergmann .pull_bit = bit, \
35*7e0a9e62SArnd Bergmann .pull_val = status,
36*7e0a9e62SArnd Bergmann
37*7e0a9e62SArnd Bergmann #define PU_PD_REG(reg, status) .pu_pd_name = "PU_PD_SEL_"#reg, \
38*7e0a9e62SArnd Bergmann .pu_pd_reg = PU_PD_SEL_##reg, \
39*7e0a9e62SArnd Bergmann .pu_pd_val = status,
40*7e0a9e62SArnd Bergmann
41*7e0a9e62SArnd Bergmann #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
42*7e0a9e62SArnd Bergmann .mux_reg = OMAP7XX_IO_CONF_##reg, \
43*7e0a9e62SArnd Bergmann .mask_offset = mode_offset, \
44*7e0a9e62SArnd Bergmann .mask = mode,
45*7e0a9e62SArnd Bergmann
46*7e0a9e62SArnd Bergmann #define PULL_REG_7XX(reg, bit, status) .pull_name = "OMAP7XX_IO_CONF_"#reg, \
47*7e0a9e62SArnd Bergmann .pull_reg = OMAP7XX_IO_CONF_##reg, \
48*7e0a9e62SArnd Bergmann .pull_bit = bit, \
49*7e0a9e62SArnd Bergmann .pull_val = status,
50*7e0a9e62SArnd Bergmann
51*7e0a9e62SArnd Bergmann #else
52*7e0a9e62SArnd Bergmann
53*7e0a9e62SArnd Bergmann #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
54*7e0a9e62SArnd Bergmann .mask_offset = mode_offset, \
55*7e0a9e62SArnd Bergmann .mask = mode,
56*7e0a9e62SArnd Bergmann
57*7e0a9e62SArnd Bergmann #define PULL_REG(reg, bit, status) .pull_reg = PULL_DWN_CTRL_##reg, \
58*7e0a9e62SArnd Bergmann .pull_bit = bit, \
59*7e0a9e62SArnd Bergmann .pull_val = status,
60*7e0a9e62SArnd Bergmann
61*7e0a9e62SArnd Bergmann #define PU_PD_REG(reg, status) .pu_pd_reg = PU_PD_SEL_##reg, \
62*7e0a9e62SArnd Bergmann .pu_pd_val = status,
63*7e0a9e62SArnd Bergmann
64*7e0a9e62SArnd Bergmann #define MUX_REG_7XX(reg, mode_offset, mode) \
65*7e0a9e62SArnd Bergmann .mux_reg = OMAP7XX_IO_CONF_##reg, \
66*7e0a9e62SArnd Bergmann .mask_offset = mode_offset, \
67*7e0a9e62SArnd Bergmann .mask = mode,
68*7e0a9e62SArnd Bergmann
69*7e0a9e62SArnd Bergmann #define PULL_REG_7XX(reg, bit, status) .pull_reg = OMAP7XX_IO_CONF_##reg, \
70*7e0a9e62SArnd Bergmann .pull_bit = bit, \
71*7e0a9e62SArnd Bergmann .pull_val = status,
72*7e0a9e62SArnd Bergmann
73*7e0a9e62SArnd Bergmann #endif /* CONFIG_OMAP_MUX_DEBUG */
74*7e0a9e62SArnd Bergmann
75*7e0a9e62SArnd Bergmann #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
76*7e0a9e62SArnd Bergmann pull_reg, pull_bit, pull_status, \
77*7e0a9e62SArnd Bergmann pu_pd_reg, pu_pd_status, debug_status) \
78*7e0a9e62SArnd Bergmann { \
79*7e0a9e62SArnd Bergmann .name = desc, \
80*7e0a9e62SArnd Bergmann .debug = debug_status, \
81*7e0a9e62SArnd Bergmann MUX_REG(mux_reg, mode_offset, mode) \
82*7e0a9e62SArnd Bergmann PULL_REG(pull_reg, pull_bit, pull_status) \
83*7e0a9e62SArnd Bergmann PU_PD_REG(pu_pd_reg, pu_pd_status) \
84*7e0a9e62SArnd Bergmann },
85*7e0a9e62SArnd Bergmann
86*7e0a9e62SArnd Bergmann
87*7e0a9e62SArnd Bergmann /*
88*7e0a9e62SArnd Bergmann * OMAP730/850 has a slightly different config for the pin mux.
89*7e0a9e62SArnd Bergmann * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
90*7e0a9e62SArnd Bergmann * not the FUNC_MUX_CTRL_x regs from hardware.h
91*7e0a9e62SArnd Bergmann * - for pull-up/down, only has one enable bit which is in the same register
92*7e0a9e62SArnd Bergmann * as mux config
93*7e0a9e62SArnd Bergmann */
94*7e0a9e62SArnd Bergmann #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \
95*7e0a9e62SArnd Bergmann pull_bit, pull_status, debug_status)\
96*7e0a9e62SArnd Bergmann { \
97*7e0a9e62SArnd Bergmann .name = desc, \
98*7e0a9e62SArnd Bergmann .debug = debug_status, \
99*7e0a9e62SArnd Bergmann MUX_REG_7XX(mux_reg, mode_offset, mode) \
100*7e0a9e62SArnd Bergmann PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
101*7e0a9e62SArnd Bergmann PU_PD_REG(NA, 0) \
102*7e0a9e62SArnd Bergmann },
103*7e0a9e62SArnd Bergmann
104*7e0a9e62SArnd Bergmann struct pin_config {
105*7e0a9e62SArnd Bergmann char *name;
106*7e0a9e62SArnd Bergmann const unsigned int mux_reg;
107*7e0a9e62SArnd Bergmann unsigned char debug;
108*7e0a9e62SArnd Bergmann
109*7e0a9e62SArnd Bergmann const unsigned char mask_offset;
110*7e0a9e62SArnd Bergmann const unsigned char mask;
111*7e0a9e62SArnd Bergmann
112*7e0a9e62SArnd Bergmann const char *pull_name;
113*7e0a9e62SArnd Bergmann const unsigned int pull_reg;
114*7e0a9e62SArnd Bergmann const unsigned char pull_val;
115*7e0a9e62SArnd Bergmann const unsigned char pull_bit;
116*7e0a9e62SArnd Bergmann
117*7e0a9e62SArnd Bergmann const char *pu_pd_name;
118*7e0a9e62SArnd Bergmann const unsigned int pu_pd_reg;
119*7e0a9e62SArnd Bergmann const unsigned char pu_pd_val;
120*7e0a9e62SArnd Bergmann
121*7e0a9e62SArnd Bergmann #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
122*7e0a9e62SArnd Bergmann const char *mux_reg_name;
123*7e0a9e62SArnd Bergmann #endif
124*7e0a9e62SArnd Bergmann
125*7e0a9e62SArnd Bergmann };
126*7e0a9e62SArnd Bergmann
127*7e0a9e62SArnd Bergmann struct omap_mux_cfg {
128*7e0a9e62SArnd Bergmann struct pin_config *pins;
129*7e0a9e62SArnd Bergmann unsigned long size;
130*7e0a9e62SArnd Bergmann int (*cfg_reg)(const struct pin_config *cfg);
131*7e0a9e62SArnd Bergmann };
132*7e0a9e62SArnd Bergmann
133*7e0a9e62SArnd Bergmann #ifdef CONFIG_OMAP_MUX
134*7e0a9e62SArnd Bergmann /* setup pin muxing in Linux */
135*7e0a9e62SArnd Bergmann extern int omap1_mux_init(void);
136*7e0a9e62SArnd Bergmann extern int omap_mux_register(struct omap_mux_cfg *);
137*7e0a9e62SArnd Bergmann #else
138*7e0a9e62SArnd Bergmann /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
omap1_mux_init(void)139*7e0a9e62SArnd Bergmann static inline int omap1_mux_init(void) { return 0; }
140*7e0a9e62SArnd Bergmann #endif
141*7e0a9e62SArnd Bergmann
142*7e0a9e62SArnd Bergmann extern int omap2_mux_init(void);
143*7e0a9e62SArnd Bergmann
144*7e0a9e62SArnd Bergmann #endif
145