145051539SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2f81ef4a9SWill Deacon /* 3f81ef4a9SWill Deacon * 4f81ef4a9SWill Deacon * Copyright (C) 2009, 2010 ARM Limited 5f81ef4a9SWill Deacon * 6f81ef4a9SWill Deacon * Author: Will Deacon <will.deacon@arm.com> 7f81ef4a9SWill Deacon */ 8f81ef4a9SWill Deacon 9f81ef4a9SWill Deacon /* 10f81ef4a9SWill Deacon * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, 11f81ef4a9SWill Deacon * using the CPU's debug registers. 12f81ef4a9SWill Deacon */ 13f81ef4a9SWill Deacon #define pr_fmt(fmt) "hw-breakpoint: " fmt 14f81ef4a9SWill Deacon 15f81ef4a9SWill Deacon #include <linux/errno.h> 167e202696SWill Deacon #include <linux/hardirq.h> 17f81ef4a9SWill Deacon #include <linux/perf_event.h> 18f81ef4a9SWill Deacon #include <linux/hw_breakpoint.h> 19f81ef4a9SWill Deacon #include <linux/smp.h> 209a6eb310SDietmar Eggemann #include <linux/cpu_pm.h> 21184901a0SMathieu Poirier #include <linux/coresight.h> 22f81ef4a9SWill Deacon 23f81ef4a9SWill Deacon #include <asm/cacheflush.h> 24f81ef4a9SWill Deacon #include <asm/cputype.h> 25f81ef4a9SWill Deacon #include <asm/current.h> 26f81ef4a9SWill Deacon #include <asm/hw_breakpoint.h> 27f81ef4a9SWill Deacon #include <asm/traps.h> 28f81ef4a9SWill Deacon 29f81ef4a9SWill Deacon /* Breakpoint currently in use for each BRP. */ 30f81ef4a9SWill Deacon static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); 31f81ef4a9SWill Deacon 32f81ef4a9SWill Deacon /* Watchpoint currently in use for each WRP. */ 33f81ef4a9SWill Deacon static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); 34f81ef4a9SWill Deacon 35f81ef4a9SWill Deacon /* Number of BRP/WRP registers on this CPU. */ 36670431eaSJinbum Park static int core_num_brps __ro_after_init; 37670431eaSJinbum Park static int core_num_wrps __ro_after_init; 38f81ef4a9SWill Deacon 39f81ef4a9SWill Deacon /* Debug architecture version. */ 40670431eaSJinbum Park static u8 debug_arch __ro_after_init; 41f81ef4a9SWill Deacon 4257ba8997SDietmar Eggemann /* Does debug architecture support OS Save and Restore? */ 43670431eaSJinbum Park static bool has_ossr __ro_after_init; 4457ba8997SDietmar Eggemann 45f81ef4a9SWill Deacon /* Maximum supported watchpoint length. */ 46670431eaSJinbum Park static u8 max_watchpoint_len __ro_after_init; 47f81ef4a9SWill Deacon 48f81ef4a9SWill Deacon #define READ_WB_REG_CASE(OP2, M, VAL) \ 49f81ef4a9SWill Deacon case ((OP2 << 4) + M): \ 509e962f76SDietmar Eggemann ARM_DBG_READ(c0, c ## M, OP2, VAL); \ 51f81ef4a9SWill Deacon break 52f81ef4a9SWill Deacon 53f81ef4a9SWill Deacon #define WRITE_WB_REG_CASE(OP2, M, VAL) \ 54f81ef4a9SWill Deacon case ((OP2 << 4) + M): \ 559e962f76SDietmar Eggemann ARM_DBG_WRITE(c0, c ## M, OP2, VAL); \ 56f81ef4a9SWill Deacon break 57f81ef4a9SWill Deacon 58f81ef4a9SWill Deacon #define GEN_READ_WB_REG_CASES(OP2, VAL) \ 59f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 0, VAL); \ 60f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 1, VAL); \ 61f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 2, VAL); \ 62f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 3, VAL); \ 63f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 4, VAL); \ 64f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 5, VAL); \ 65f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 6, VAL); \ 66f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 7, VAL); \ 67f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 8, VAL); \ 68f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 9, VAL); \ 69f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 10, VAL); \ 70f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 11, VAL); \ 71f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 12, VAL); \ 72f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 13, VAL); \ 73f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 14, VAL); \ 74f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 15, VAL) 75f81ef4a9SWill Deacon 76f81ef4a9SWill Deacon #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ 77f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 0, VAL); \ 78f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 1, VAL); \ 79f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 2, VAL); \ 80f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 3, VAL); \ 81f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 4, VAL); \ 82f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 5, VAL); \ 83f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 6, VAL); \ 84f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 7, VAL); \ 85f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 8, VAL); \ 86f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 9, VAL); \ 87f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 10, VAL); \ 88f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 11, VAL); \ 89f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 12, VAL); \ 90f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 13, VAL); \ 91f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 14, VAL); \ 92f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 15, VAL) 93f81ef4a9SWill Deacon 94f81ef4a9SWill Deacon static u32 read_wb_reg(int n) 95f81ef4a9SWill Deacon { 96f81ef4a9SWill Deacon u32 val = 0; 97f81ef4a9SWill Deacon 98f81ef4a9SWill Deacon switch (n) { 99f81ef4a9SWill Deacon GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); 100f81ef4a9SWill Deacon GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); 101f81ef4a9SWill Deacon GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); 102f81ef4a9SWill Deacon GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); 103f81ef4a9SWill Deacon default: 1048b521cb2SJoe Perches pr_warn("attempt to read from unknown breakpoint register %d\n", 1058b521cb2SJoe Perches n); 106f81ef4a9SWill Deacon } 107f81ef4a9SWill Deacon 108f81ef4a9SWill Deacon return val; 109f81ef4a9SWill Deacon } 110f81ef4a9SWill Deacon 111f81ef4a9SWill Deacon static void write_wb_reg(int n, u32 val) 112f81ef4a9SWill Deacon { 113f81ef4a9SWill Deacon switch (n) { 114f81ef4a9SWill Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); 115f81ef4a9SWill Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); 116f81ef4a9SWill Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); 117f81ef4a9SWill Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); 118f81ef4a9SWill Deacon default: 1198b521cb2SJoe Perches pr_warn("attempt to write to unknown breakpoint register %d\n", 1208b521cb2SJoe Perches n); 121f81ef4a9SWill Deacon } 122f81ef4a9SWill Deacon isb(); 123f81ef4a9SWill Deacon } 124f81ef4a9SWill Deacon 1250017ff42SWill Deacon /* Determine debug architecture. */ 1260017ff42SWill Deacon static u8 get_debug_arch(void) 1270017ff42SWill Deacon { 1280017ff42SWill Deacon u32 didr; 1290017ff42SWill Deacon 1300017ff42SWill Deacon /* Do we implement the extended CPUID interface? */ 131d1244336SWill Deacon if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { 1325ad29ea2SWill Deacon pr_warn_once("CPUID feature registers not supported. " 133d1244336SWill Deacon "Assuming v6 debug is present.\n"); 1340017ff42SWill Deacon return ARM_DEBUG_ARCH_V6; 135d1244336SWill Deacon } 1360017ff42SWill Deacon 1379e962f76SDietmar Eggemann ARM_DBG_READ(c0, c0, 0, didr); 1380017ff42SWill Deacon return (didr >> 16) & 0xf; 1390017ff42SWill Deacon } 1400017ff42SWill Deacon 1410017ff42SWill Deacon u8 arch_get_debug_arch(void) 1420017ff42SWill Deacon { 1430017ff42SWill Deacon return debug_arch; 1440017ff42SWill Deacon } 1450017ff42SWill Deacon 14666e1cfe6SWill Deacon static int debug_arch_supported(void) 14766e1cfe6SWill Deacon { 14866e1cfe6SWill Deacon u8 arch = get_debug_arch(); 149b5d5b8f9SWill Deacon 150b5d5b8f9SWill Deacon /* We don't support the memory-mapped interface. */ 151b5d5b8f9SWill Deacon return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) || 152b5d5b8f9SWill Deacon arch >= ARM_DEBUG_ARCH_V7_1; 15366e1cfe6SWill Deacon } 15466e1cfe6SWill Deacon 155bf880114SWill Deacon /* Can we determine the watchpoint access type from the fsr? */ 156bf880114SWill Deacon static int debug_exception_updates_fsr(void) 157bf880114SWill Deacon { 1585b61d4a5SChristopher Covington return get_debug_arch() >= ARM_DEBUG_ARCH_V8; 159bf880114SWill Deacon } 160bf880114SWill Deacon 161c512de95SWill Deacon /* Determine number of WRP registers available. */ 162c512de95SWill Deacon static int get_num_wrp_resources(void) 163c512de95SWill Deacon { 164c512de95SWill Deacon u32 didr; 1659e962f76SDietmar Eggemann ARM_DBG_READ(c0, c0, 0, didr); 166c512de95SWill Deacon return ((didr >> 28) & 0xf) + 1; 167c512de95SWill Deacon } 168c512de95SWill Deacon 169c512de95SWill Deacon /* Determine number of BRP registers available. */ 1700017ff42SWill Deacon static int get_num_brp_resources(void) 1710017ff42SWill Deacon { 1720017ff42SWill Deacon u32 didr; 1739e962f76SDietmar Eggemann ARM_DBG_READ(c0, c0, 0, didr); 1740017ff42SWill Deacon return ((didr >> 24) & 0xf) + 1; 1750017ff42SWill Deacon } 1760017ff42SWill Deacon 1770017ff42SWill Deacon /* Does this core support mismatch breakpoints? */ 1780017ff42SWill Deacon static int core_has_mismatch_brps(void) 1790017ff42SWill Deacon { 1800017ff42SWill Deacon return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 && 1810017ff42SWill Deacon get_num_brp_resources() > 1); 1820017ff42SWill Deacon } 1830017ff42SWill Deacon 1840017ff42SWill Deacon /* Determine number of usable WRPs available. */ 1850017ff42SWill Deacon static int get_num_wrps(void) 1860017ff42SWill Deacon { 1870017ff42SWill Deacon /* 188c512de95SWill Deacon * On debug architectures prior to 7.1, when a watchpoint fires, the 189c512de95SWill Deacon * only way to work out which watchpoint it was is by disassembling 190c512de95SWill Deacon * the faulting instruction and working out the address of the memory 191c512de95SWill Deacon * access. 1920017ff42SWill Deacon * 1930017ff42SWill Deacon * Furthermore, we can only do this if the watchpoint was precise 1940017ff42SWill Deacon * since imprecise watchpoints prevent us from calculating register 1950017ff42SWill Deacon * based addresses. 1960017ff42SWill Deacon * 1970017ff42SWill Deacon * Providing we have more than 1 breakpoint register, we only report 1980017ff42SWill Deacon * a single watchpoint register for the time being. This way, we always 1990017ff42SWill Deacon * know which watchpoint fired. In the future we can either add a 2000017ff42SWill Deacon * disassembler and address generation emulator, or we can insert a 2010017ff42SWill Deacon * check to see if the DFAR is set on watchpoint exception entry 2020017ff42SWill Deacon * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows 2030017ff42SWill Deacon * that it is set on some implementations]. 2040017ff42SWill Deacon */ 205c512de95SWill Deacon if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1) 206c512de95SWill Deacon return 1; 2070017ff42SWill Deacon 208c512de95SWill Deacon return get_num_wrp_resources(); 2090017ff42SWill Deacon } 2100017ff42SWill Deacon 2110017ff42SWill Deacon /* Determine number of usable BRPs available. */ 2120017ff42SWill Deacon static int get_num_brps(void) 2130017ff42SWill Deacon { 2140017ff42SWill Deacon int brps = get_num_brp_resources(); 215c512de95SWill Deacon return core_has_mismatch_brps() ? brps - 1 : brps; 2160017ff42SWill Deacon } 2170017ff42SWill Deacon 218f81ef4a9SWill Deacon /* 219f81ef4a9SWill Deacon * In order to access the breakpoint/watchpoint control registers, 220f81ef4a9SWill Deacon * we must be running in debug monitor mode. Unfortunately, we can 221f81ef4a9SWill Deacon * be put into halting debug mode at any time by an external debugger 222f81ef4a9SWill Deacon * but there is nothing we can do to prevent that. 223f81ef4a9SWill Deacon */ 2240daa034eSWill Deacon static int monitor_mode_enabled(void) 2250daa034eSWill Deacon { 2260daa034eSWill Deacon u32 dscr; 2279e962f76SDietmar Eggemann ARM_DBG_READ(c0, c1, 0, dscr); 2280daa034eSWill Deacon return !!(dscr & ARM_DSCR_MDBGEN); 2290daa034eSWill Deacon } 2300daa034eSWill Deacon 231f81ef4a9SWill Deacon static int enable_monitor_mode(void) 232f81ef4a9SWill Deacon { 233f81ef4a9SWill Deacon u32 dscr; 2349e962f76SDietmar Eggemann ARM_DBG_READ(c0, c1, 0, dscr); 235f81ef4a9SWill Deacon 2368fbf397cSWill Deacon /* If monitor mode is already enabled, just return. */ 2378fbf397cSWill Deacon if (dscr & ARM_DSCR_MDBGEN) 2388fbf397cSWill Deacon goto out; 2398fbf397cSWill Deacon 240f81ef4a9SWill Deacon /* Write to the corresponding DSCR. */ 2418fbf397cSWill Deacon switch (get_debug_arch()) { 242f81ef4a9SWill Deacon case ARM_DEBUG_ARCH_V6: 243f81ef4a9SWill Deacon case ARM_DEBUG_ARCH_V6_1: 2449e962f76SDietmar Eggemann ARM_DBG_WRITE(c0, c1, 0, (dscr | ARM_DSCR_MDBGEN)); 245f81ef4a9SWill Deacon break; 246f81ef4a9SWill Deacon case ARM_DEBUG_ARCH_V7_ECP14: 247b5d5b8f9SWill Deacon case ARM_DEBUG_ARCH_V7_1: 2485b61d4a5SChristopher Covington case ARM_DEBUG_ARCH_V8: 249bebe668eSCandle Sun case ARM_DEBUG_ARCH_V8_1: 250bebe668eSCandle Sun case ARM_DEBUG_ARCH_V8_2: 251bebe668eSCandle Sun case ARM_DEBUG_ARCH_V8_4: 2529e962f76SDietmar Eggemann ARM_DBG_WRITE(c0, c2, 2, (dscr | ARM_DSCR_MDBGEN)); 253b59a540cSWill Deacon isb(); 254f81ef4a9SWill Deacon break; 255f81ef4a9SWill Deacon default: 256614bea50SWill Deacon return -ENODEV; 257f81ef4a9SWill Deacon } 258f81ef4a9SWill Deacon 259f81ef4a9SWill Deacon /* Check that the write made it through. */ 2609e962f76SDietmar Eggemann ARM_DBG_READ(c0, c1, 0, dscr); 261f435ab79SWill Deacon if (!(dscr & ARM_DSCR_MDBGEN)) { 262f435ab79SWill Deacon pr_warn_once("Failed to enable monitor mode on CPU %d.\n", 263f435ab79SWill Deacon smp_processor_id()); 264614bea50SWill Deacon return -EPERM; 265f435ab79SWill Deacon } 266f81ef4a9SWill Deacon 267f81ef4a9SWill Deacon out: 268614bea50SWill Deacon return 0; 269f81ef4a9SWill Deacon } 270f81ef4a9SWill Deacon 2718fbf397cSWill Deacon int hw_breakpoint_slots(int type) 2728fbf397cSWill Deacon { 27366e1cfe6SWill Deacon if (!debug_arch_supported()) 27466e1cfe6SWill Deacon return 0; 27566e1cfe6SWill Deacon 2768fbf397cSWill Deacon /* 2778fbf397cSWill Deacon * We can be called early, so don't rely on 2788fbf397cSWill Deacon * our static variables being initialised. 2798fbf397cSWill Deacon */ 2808fbf397cSWill Deacon switch (type) { 2818fbf397cSWill Deacon case TYPE_INST: 2828fbf397cSWill Deacon return get_num_brps(); 2838fbf397cSWill Deacon case TYPE_DATA: 2848fbf397cSWill Deacon return get_num_wrps(); 2858fbf397cSWill Deacon default: 2868b521cb2SJoe Perches pr_warn("unknown slot type: %d\n", type); 2878fbf397cSWill Deacon return 0; 2888fbf397cSWill Deacon } 2898fbf397cSWill Deacon } 2908fbf397cSWill Deacon 291f81ef4a9SWill Deacon /* 292f81ef4a9SWill Deacon * Check if 8-bit byte-address select is available. 293f81ef4a9SWill Deacon * This clobbers WRP 0. 294f81ef4a9SWill Deacon */ 295f81ef4a9SWill Deacon static u8 get_max_wp_len(void) 296f81ef4a9SWill Deacon { 297f81ef4a9SWill Deacon u32 ctrl_reg; 298f81ef4a9SWill Deacon struct arch_hw_breakpoint_ctrl ctrl; 299f81ef4a9SWill Deacon u8 size = 4; 300f81ef4a9SWill Deacon 301f81ef4a9SWill Deacon if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) 302f81ef4a9SWill Deacon goto out; 303f81ef4a9SWill Deacon 304f81ef4a9SWill Deacon memset(&ctrl, 0, sizeof(ctrl)); 305f81ef4a9SWill Deacon ctrl.len = ARM_BREAKPOINT_LEN_8; 306f81ef4a9SWill Deacon ctrl_reg = encode_ctrl_reg(ctrl); 307f81ef4a9SWill Deacon 308f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_WVR, 0); 309f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_WCR, ctrl_reg); 310f81ef4a9SWill Deacon if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) 311f81ef4a9SWill Deacon size = 8; 312f81ef4a9SWill Deacon 313f81ef4a9SWill Deacon out: 314f81ef4a9SWill Deacon return size; 315f81ef4a9SWill Deacon } 316f81ef4a9SWill Deacon 317f81ef4a9SWill Deacon u8 arch_get_max_wp_len(void) 318f81ef4a9SWill Deacon { 319f81ef4a9SWill Deacon return max_watchpoint_len; 320f81ef4a9SWill Deacon } 321f81ef4a9SWill Deacon 322f81ef4a9SWill Deacon /* 323f81ef4a9SWill Deacon * Install a perf counter breakpoint. 324f81ef4a9SWill Deacon */ 325f81ef4a9SWill Deacon int arch_install_hw_breakpoint(struct perf_event *bp) 326f81ef4a9SWill Deacon { 327f81ef4a9SWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 328f81ef4a9SWill Deacon struct perf_event **slot, **slots; 3290daa034eSWill Deacon int i, max_slots, ctrl_base, val_base; 33093a04a34SWill Deacon u32 addr, ctrl; 331f81ef4a9SWill Deacon 33293a04a34SWill Deacon addr = info->address; 33393a04a34SWill Deacon ctrl = encode_ctrl_reg(info->ctrl) | 0x1; 33493a04a34SWill Deacon 335f81ef4a9SWill Deacon if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 336f81ef4a9SWill Deacon /* Breakpoint */ 337f81ef4a9SWill Deacon ctrl_base = ARM_BASE_BCR; 338f81ef4a9SWill Deacon val_base = ARM_BASE_BVR; 3391436c1aaSChristoph Lameter slots = this_cpu_ptr(bp_on_reg); 3400017ff42SWill Deacon max_slots = core_num_brps; 341f81ef4a9SWill Deacon } else { 342f81ef4a9SWill Deacon /* Watchpoint */ 343f81ef4a9SWill Deacon ctrl_base = ARM_BASE_WCR; 344f81ef4a9SWill Deacon val_base = ARM_BASE_WVR; 3451436c1aaSChristoph Lameter slots = this_cpu_ptr(wp_on_reg); 346f81ef4a9SWill Deacon max_slots = core_num_wrps; 347f81ef4a9SWill Deacon } 348f81ef4a9SWill Deacon 349f81ef4a9SWill Deacon for (i = 0; i < max_slots; ++i) { 350f81ef4a9SWill Deacon slot = &slots[i]; 351f81ef4a9SWill Deacon 352f81ef4a9SWill Deacon if (!*slot) { 353f81ef4a9SWill Deacon *slot = bp; 354f81ef4a9SWill Deacon break; 355f81ef4a9SWill Deacon } 356f81ef4a9SWill Deacon } 357f81ef4a9SWill Deacon 358f435ab79SWill Deacon if (i == max_slots) { 3598b521cb2SJoe Perches pr_warn("Can't find any breakpoint slot\n"); 3600daa034eSWill Deacon return -EBUSY; 361f435ab79SWill Deacon } 362f81ef4a9SWill Deacon 3636f26aa05SWill Deacon /* Override the breakpoint data with the step data. */ 3646f26aa05SWill Deacon if (info->step_ctrl.enabled) { 3656f26aa05SWill Deacon addr = info->trigger & ~0x3; 3666f26aa05SWill Deacon ctrl = encode_ctrl_reg(info->step_ctrl); 3676f26aa05SWill Deacon if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) { 3686f26aa05SWill Deacon i = 0; 3696f26aa05SWill Deacon ctrl_base = ARM_BASE_BCR + core_num_brps; 3706f26aa05SWill Deacon val_base = ARM_BASE_BVR + core_num_brps; 3716f26aa05SWill Deacon } 3726f26aa05SWill Deacon } 3736f26aa05SWill Deacon 374f81ef4a9SWill Deacon /* Setup the address register. */ 37593a04a34SWill Deacon write_wb_reg(val_base + i, addr); 376f81ef4a9SWill Deacon 377f81ef4a9SWill Deacon /* Setup the control register. */ 37893a04a34SWill Deacon write_wb_reg(ctrl_base + i, ctrl); 3790daa034eSWill Deacon return 0; 380f81ef4a9SWill Deacon } 381f81ef4a9SWill Deacon 382f81ef4a9SWill Deacon void arch_uninstall_hw_breakpoint(struct perf_event *bp) 383f81ef4a9SWill Deacon { 384f81ef4a9SWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 385f81ef4a9SWill Deacon struct perf_event **slot, **slots; 386f81ef4a9SWill Deacon int i, max_slots, base; 387f81ef4a9SWill Deacon 388f81ef4a9SWill Deacon if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 389f81ef4a9SWill Deacon /* Breakpoint */ 390f81ef4a9SWill Deacon base = ARM_BASE_BCR; 3911436c1aaSChristoph Lameter slots = this_cpu_ptr(bp_on_reg); 3920017ff42SWill Deacon max_slots = core_num_brps; 393f81ef4a9SWill Deacon } else { 394f81ef4a9SWill Deacon /* Watchpoint */ 395f81ef4a9SWill Deacon base = ARM_BASE_WCR; 3961436c1aaSChristoph Lameter slots = this_cpu_ptr(wp_on_reg); 397f81ef4a9SWill Deacon max_slots = core_num_wrps; 398f81ef4a9SWill Deacon } 399f81ef4a9SWill Deacon 400f81ef4a9SWill Deacon /* Remove the breakpoint. */ 401f81ef4a9SWill Deacon for (i = 0; i < max_slots; ++i) { 402f81ef4a9SWill Deacon slot = &slots[i]; 403f81ef4a9SWill Deacon 404f81ef4a9SWill Deacon if (*slot == bp) { 405f81ef4a9SWill Deacon *slot = NULL; 406f81ef4a9SWill Deacon break; 407f81ef4a9SWill Deacon } 408f81ef4a9SWill Deacon } 409f81ef4a9SWill Deacon 410f435ab79SWill Deacon if (i == max_slots) { 4118b521cb2SJoe Perches pr_warn("Can't find any breakpoint slot\n"); 412f81ef4a9SWill Deacon return; 413f435ab79SWill Deacon } 414f81ef4a9SWill Deacon 4156f26aa05SWill Deacon /* Ensure that we disable the mismatch breakpoint. */ 4166f26aa05SWill Deacon if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE && 4176f26aa05SWill Deacon info->step_ctrl.enabled) { 4186f26aa05SWill Deacon i = 0; 4196f26aa05SWill Deacon base = ARM_BASE_BCR + core_num_brps; 4206f26aa05SWill Deacon } 4216f26aa05SWill Deacon 422f81ef4a9SWill Deacon /* Reset the control register. */ 423f81ef4a9SWill Deacon write_wb_reg(base + i, 0); 424f81ef4a9SWill Deacon } 425f81ef4a9SWill Deacon 426f81ef4a9SWill Deacon static int get_hbp_len(u8 hbp_len) 427f81ef4a9SWill Deacon { 428f81ef4a9SWill Deacon unsigned int len_in_bytes = 0; 429f81ef4a9SWill Deacon 430f81ef4a9SWill Deacon switch (hbp_len) { 431f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_1: 432f81ef4a9SWill Deacon len_in_bytes = 1; 433f81ef4a9SWill Deacon break; 434f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_2: 435f81ef4a9SWill Deacon len_in_bytes = 2; 436f81ef4a9SWill Deacon break; 437f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_4: 438f81ef4a9SWill Deacon len_in_bytes = 4; 439f81ef4a9SWill Deacon break; 440f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_8: 441f81ef4a9SWill Deacon len_in_bytes = 8; 442f81ef4a9SWill Deacon break; 443f81ef4a9SWill Deacon } 444f81ef4a9SWill Deacon 445f81ef4a9SWill Deacon return len_in_bytes; 446f81ef4a9SWill Deacon } 447f81ef4a9SWill Deacon 448f81ef4a9SWill Deacon /* 449f81ef4a9SWill Deacon * Check whether bp virtual address is in kernel space. 450f81ef4a9SWill Deacon */ 4518e983ff9SFrederic Weisbecker int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) 452f81ef4a9SWill Deacon { 453f81ef4a9SWill Deacon unsigned int len; 454f81ef4a9SWill Deacon unsigned long va; 455f81ef4a9SWill Deacon 4568e983ff9SFrederic Weisbecker va = hw->address; 4578e983ff9SFrederic Weisbecker len = get_hbp_len(hw->ctrl.len); 458f81ef4a9SWill Deacon 459f81ef4a9SWill Deacon return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); 460f81ef4a9SWill Deacon } 461f81ef4a9SWill Deacon 462f81ef4a9SWill Deacon /* 463f81ef4a9SWill Deacon * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. 464f81ef4a9SWill Deacon * Hopefully this will disappear when ptrace can bypass the conversion 465f81ef4a9SWill Deacon * to generic breakpoint descriptions. 466f81ef4a9SWill Deacon */ 467f81ef4a9SWill Deacon int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, 468f81ef4a9SWill Deacon int *gen_len, int *gen_type) 469f81ef4a9SWill Deacon { 470f81ef4a9SWill Deacon /* Type */ 471f81ef4a9SWill Deacon switch (ctrl.type) { 472f81ef4a9SWill Deacon case ARM_BREAKPOINT_EXECUTE: 473f81ef4a9SWill Deacon *gen_type = HW_BREAKPOINT_X; 474f81ef4a9SWill Deacon break; 475f81ef4a9SWill Deacon case ARM_BREAKPOINT_LOAD: 476f81ef4a9SWill Deacon *gen_type = HW_BREAKPOINT_R; 477f81ef4a9SWill Deacon break; 478f81ef4a9SWill Deacon case ARM_BREAKPOINT_STORE: 479f81ef4a9SWill Deacon *gen_type = HW_BREAKPOINT_W; 480f81ef4a9SWill Deacon break; 481f81ef4a9SWill Deacon case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: 482f81ef4a9SWill Deacon *gen_type = HW_BREAKPOINT_RW; 483f81ef4a9SWill Deacon break; 484f81ef4a9SWill Deacon default: 485f81ef4a9SWill Deacon return -EINVAL; 486f81ef4a9SWill Deacon } 487f81ef4a9SWill Deacon 488f81ef4a9SWill Deacon /* Len */ 489f81ef4a9SWill Deacon switch (ctrl.len) { 490f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_1: 491f81ef4a9SWill Deacon *gen_len = HW_BREAKPOINT_LEN_1; 492f81ef4a9SWill Deacon break; 493f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_2: 494f81ef4a9SWill Deacon *gen_len = HW_BREAKPOINT_LEN_2; 495f81ef4a9SWill Deacon break; 496f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_4: 497f81ef4a9SWill Deacon *gen_len = HW_BREAKPOINT_LEN_4; 498f81ef4a9SWill Deacon break; 499f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_8: 500f81ef4a9SWill Deacon *gen_len = HW_BREAKPOINT_LEN_8; 501f81ef4a9SWill Deacon break; 502f81ef4a9SWill Deacon default: 503f81ef4a9SWill Deacon return -EINVAL; 504f81ef4a9SWill Deacon } 505f81ef4a9SWill Deacon 506f81ef4a9SWill Deacon return 0; 507f81ef4a9SWill Deacon } 508f81ef4a9SWill Deacon 509f81ef4a9SWill Deacon /* 510f81ef4a9SWill Deacon * Construct an arch_hw_breakpoint from a perf_event. 511f81ef4a9SWill Deacon */ 5129d52718cSFrederic Weisbecker static int arch_build_bp_info(struct perf_event *bp, 5139d52718cSFrederic Weisbecker const struct perf_event_attr *attr, 5149d52718cSFrederic Weisbecker struct arch_hw_breakpoint *hw) 515f81ef4a9SWill Deacon { 516f81ef4a9SWill Deacon /* Type */ 5179d52718cSFrederic Weisbecker switch (attr->bp_type) { 518f81ef4a9SWill Deacon case HW_BREAKPOINT_X: 5199d52718cSFrederic Weisbecker hw->ctrl.type = ARM_BREAKPOINT_EXECUTE; 520f81ef4a9SWill Deacon break; 521f81ef4a9SWill Deacon case HW_BREAKPOINT_R: 5229d52718cSFrederic Weisbecker hw->ctrl.type = ARM_BREAKPOINT_LOAD; 523f81ef4a9SWill Deacon break; 524f81ef4a9SWill Deacon case HW_BREAKPOINT_W: 5259d52718cSFrederic Weisbecker hw->ctrl.type = ARM_BREAKPOINT_STORE; 526f81ef4a9SWill Deacon break; 527f81ef4a9SWill Deacon case HW_BREAKPOINT_RW: 5289d52718cSFrederic Weisbecker hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; 529f81ef4a9SWill Deacon break; 530f81ef4a9SWill Deacon default: 531f81ef4a9SWill Deacon return -EINVAL; 532f81ef4a9SWill Deacon } 533f81ef4a9SWill Deacon 534f81ef4a9SWill Deacon /* Len */ 5359d52718cSFrederic Weisbecker switch (attr->bp_len) { 536f81ef4a9SWill Deacon case HW_BREAKPOINT_LEN_1: 5379d52718cSFrederic Weisbecker hw->ctrl.len = ARM_BREAKPOINT_LEN_1; 538f81ef4a9SWill Deacon break; 539f81ef4a9SWill Deacon case HW_BREAKPOINT_LEN_2: 5409d52718cSFrederic Weisbecker hw->ctrl.len = ARM_BREAKPOINT_LEN_2; 541f81ef4a9SWill Deacon break; 542f81ef4a9SWill Deacon case HW_BREAKPOINT_LEN_4: 5439d52718cSFrederic Weisbecker hw->ctrl.len = ARM_BREAKPOINT_LEN_4; 544f81ef4a9SWill Deacon break; 545f81ef4a9SWill Deacon case HW_BREAKPOINT_LEN_8: 5469d52718cSFrederic Weisbecker hw->ctrl.len = ARM_BREAKPOINT_LEN_8; 5479d52718cSFrederic Weisbecker if ((hw->ctrl.type != ARM_BREAKPOINT_EXECUTE) 548f81ef4a9SWill Deacon && max_watchpoint_len >= 8) 549f81ef4a9SWill Deacon break; 5502d0e988dSGustavo A. R. Silva /* Else, fall through */ 551f81ef4a9SWill Deacon default: 552f81ef4a9SWill Deacon return -EINVAL; 553f81ef4a9SWill Deacon } 554f81ef4a9SWill Deacon 5556ee33c27SWill Deacon /* 5566ee33c27SWill Deacon * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. 5576ee33c27SWill Deacon * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported 5586ee33c27SWill Deacon * by the hardware and must be aligned to the appropriate number of 5596ee33c27SWill Deacon * bytes. 5606ee33c27SWill Deacon */ 5619d52718cSFrederic Weisbecker if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE && 5629d52718cSFrederic Weisbecker hw->ctrl.len != ARM_BREAKPOINT_LEN_2 && 5639d52718cSFrederic Weisbecker hw->ctrl.len != ARM_BREAKPOINT_LEN_4) 5646ee33c27SWill Deacon return -EINVAL; 5656ee33c27SWill Deacon 566f81ef4a9SWill Deacon /* Address */ 5679d52718cSFrederic Weisbecker hw->address = attr->bp_addr; 568f81ef4a9SWill Deacon 569f81ef4a9SWill Deacon /* Privilege */ 5709d52718cSFrederic Weisbecker hw->ctrl.privilege = ARM_BREAKPOINT_USER; 5719d52718cSFrederic Weisbecker if (arch_check_bp_in_kernelspace(hw)) 5729d52718cSFrederic Weisbecker hw->ctrl.privilege |= ARM_BREAKPOINT_PRIV; 573f81ef4a9SWill Deacon 574f81ef4a9SWill Deacon /* Enabled? */ 5759d52718cSFrederic Weisbecker hw->ctrl.enabled = !attr->disabled; 576f81ef4a9SWill Deacon 577f81ef4a9SWill Deacon /* Mismatch */ 5789d52718cSFrederic Weisbecker hw->ctrl.mismatch = 0; 579f81ef4a9SWill Deacon 580f81ef4a9SWill Deacon return 0; 581f81ef4a9SWill Deacon } 582f81ef4a9SWill Deacon 583f81ef4a9SWill Deacon /* 584f81ef4a9SWill Deacon * Validate the arch-specific HW Breakpoint register settings. 585f81ef4a9SWill Deacon */ 5869d52718cSFrederic Weisbecker int hw_breakpoint_arch_parse(struct perf_event *bp, 5879d52718cSFrederic Weisbecker const struct perf_event_attr *attr, 5889d52718cSFrederic Weisbecker struct arch_hw_breakpoint *hw) 589f81ef4a9SWill Deacon { 590f81ef4a9SWill Deacon int ret = 0; 5916ee33c27SWill Deacon u32 offset, alignment_mask = 0x3; 592f81ef4a9SWill Deacon 5930daa034eSWill Deacon /* Ensure that we are in monitor debug mode. */ 5940daa034eSWill Deacon if (!monitor_mode_enabled()) 5950daa034eSWill Deacon return -ENODEV; 5960daa034eSWill Deacon 597f81ef4a9SWill Deacon /* Build the arch_hw_breakpoint. */ 5989d52718cSFrederic Weisbecker ret = arch_build_bp_info(bp, attr, hw); 599f81ef4a9SWill Deacon if (ret) 600f81ef4a9SWill Deacon goto out; 601f81ef4a9SWill Deacon 602f81ef4a9SWill Deacon /* Check address alignment. */ 6039d52718cSFrederic Weisbecker if (hw->ctrl.len == ARM_BREAKPOINT_LEN_8) 604f81ef4a9SWill Deacon alignment_mask = 0x7; 6059d52718cSFrederic Weisbecker offset = hw->address & alignment_mask; 6066ee33c27SWill Deacon switch (offset) { 6076ee33c27SWill Deacon case 0: 6086ee33c27SWill Deacon /* Aligned */ 6096ee33c27SWill Deacon break; 6106ee33c27SWill Deacon case 1: 6116ee33c27SWill Deacon case 2: 6126ee33c27SWill Deacon /* Allow halfword watchpoints and breakpoints. */ 6139d52718cSFrederic Weisbecker if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2) 6146ee33c27SWill Deacon break; 6152d0e988dSGustavo A. R. Silva /* Else, fall through */ 616d968d2b8SWill Deacon case 3: 617d968d2b8SWill Deacon /* Allow single byte watchpoint. */ 6189d52718cSFrederic Weisbecker if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1) 619d968d2b8SWill Deacon break; 6202d0e988dSGustavo A. R. Silva /* Else, fall through */ 6216ee33c27SWill Deacon default: 6226ee33c27SWill Deacon ret = -EINVAL; 623f81ef4a9SWill Deacon goto out; 624f81ef4a9SWill Deacon } 625f81ef4a9SWill Deacon 6269d52718cSFrederic Weisbecker hw->address &= ~alignment_mask; 6279d52718cSFrederic Weisbecker hw->ctrl.len <<= offset; 628f81ef4a9SWill Deacon 6291879445dSWang Nan if (is_default_overflow_handler(bp)) { 630f81ef4a9SWill Deacon /* 631bf880114SWill Deacon * Mismatch breakpoints are required for single-stepping 632bf880114SWill Deacon * breakpoints. 633f81ef4a9SWill Deacon */ 634bf880114SWill Deacon if (!core_has_mismatch_brps()) 635bf880114SWill Deacon return -EINVAL; 636bf880114SWill Deacon 637bf880114SWill Deacon /* We don't allow mismatch breakpoints in kernel space. */ 6389d52718cSFrederic Weisbecker if (arch_check_bp_in_kernelspace(hw)) 639bf880114SWill Deacon return -EPERM; 640bf880114SWill Deacon 641bf880114SWill Deacon /* 642bf880114SWill Deacon * Per-cpu breakpoints are not supported by our stepping 643bf880114SWill Deacon * mechanism. 644bf880114SWill Deacon */ 64550f16a8bSPeter Zijlstra if (!bp->hw.target) 646bf880114SWill Deacon return -EINVAL; 647bf880114SWill Deacon 648bf880114SWill Deacon /* 649bf880114SWill Deacon * We only support specific access types if the fsr 650bf880114SWill Deacon * reports them. 651bf880114SWill Deacon */ 652bf880114SWill Deacon if (!debug_exception_updates_fsr() && 6539d52718cSFrederic Weisbecker (hw->ctrl.type == ARM_BREAKPOINT_LOAD || 6549d52718cSFrederic Weisbecker hw->ctrl.type == ARM_BREAKPOINT_STORE)) 655bf880114SWill Deacon return -EINVAL; 656f81ef4a9SWill Deacon } 657bf880114SWill Deacon 658f81ef4a9SWill Deacon out: 659f81ef4a9SWill Deacon return ret; 660f81ef4a9SWill Deacon } 661f81ef4a9SWill Deacon 6629ebb3cbcSWill Deacon /* 6639ebb3cbcSWill Deacon * Enable/disable single-stepping over the breakpoint bp at address addr. 6649ebb3cbcSWill Deacon */ 6659ebb3cbcSWill Deacon static void enable_single_step(struct perf_event *bp, u32 addr) 666f81ef4a9SWill Deacon { 6679ebb3cbcSWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 668f81ef4a9SWill Deacon 6699ebb3cbcSWill Deacon arch_uninstall_hw_breakpoint(bp); 6709ebb3cbcSWill Deacon info->step_ctrl.mismatch = 1; 6719ebb3cbcSWill Deacon info->step_ctrl.len = ARM_BREAKPOINT_LEN_4; 6729ebb3cbcSWill Deacon info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE; 6739ebb3cbcSWill Deacon info->step_ctrl.privilege = info->ctrl.privilege; 6749ebb3cbcSWill Deacon info->step_ctrl.enabled = 1; 6759ebb3cbcSWill Deacon info->trigger = addr; 6769ebb3cbcSWill Deacon arch_install_hw_breakpoint(bp); 677f81ef4a9SWill Deacon } 6789ebb3cbcSWill Deacon 6799ebb3cbcSWill Deacon static void disable_single_step(struct perf_event *bp) 6809ebb3cbcSWill Deacon { 6819ebb3cbcSWill Deacon arch_uninstall_hw_breakpoint(bp); 6829ebb3cbcSWill Deacon counter_arch_bp(bp)->step_ctrl.enabled = 0; 6839ebb3cbcSWill Deacon arch_install_hw_breakpoint(bp); 684f81ef4a9SWill Deacon } 685f81ef4a9SWill Deacon 686*eec13b42SWill Deacon static int watchpoint_fault_on_uaccess(struct pt_regs *regs, 687*eec13b42SWill Deacon struct arch_hw_breakpoint *info) 688*eec13b42SWill Deacon { 689*eec13b42SWill Deacon return !user_mode(regs) && info->ctrl.privilege == ARM_BREAKPOINT_USER; 690*eec13b42SWill Deacon } 691*eec13b42SWill Deacon 6926f26aa05SWill Deacon static void watchpoint_handler(unsigned long addr, unsigned int fsr, 6936f26aa05SWill Deacon struct pt_regs *regs) 694f81ef4a9SWill Deacon { 6956f26aa05SWill Deacon int i, access; 6966f26aa05SWill Deacon u32 val, ctrl_reg, alignment_mask; 6974a55c18eSWill Deacon struct perf_event *wp, **slots; 698f81ef4a9SWill Deacon struct arch_hw_breakpoint *info; 6996f26aa05SWill Deacon struct arch_hw_breakpoint_ctrl ctrl; 700f81ef4a9SWill Deacon 7011436c1aaSChristoph Lameter slots = this_cpu_ptr(wp_on_reg); 7024a55c18eSWill Deacon 703f81ef4a9SWill Deacon for (i = 0; i < core_num_wrps; ++i) { 704f81ef4a9SWill Deacon rcu_read_lock(); 705f81ef4a9SWill Deacon 70693a04a34SWill Deacon wp = slots[i]; 70793a04a34SWill Deacon 7086f26aa05SWill Deacon if (wp == NULL) 7096f26aa05SWill Deacon goto unlock; 7106f26aa05SWill Deacon 7116f26aa05SWill Deacon info = counter_arch_bp(wp); 7126f26aa05SWill Deacon /* 7136f26aa05SWill Deacon * The DFAR is an unknown value on debug architectures prior 7146f26aa05SWill Deacon * to 7.1. Since we only allow a single watchpoint on these 7156f26aa05SWill Deacon * older CPUs, we can set the trigger to the lowest possible 7166f26aa05SWill Deacon * faulting address. 7176f26aa05SWill Deacon */ 7186f26aa05SWill Deacon if (debug_arch < ARM_DEBUG_ARCH_V7_1) { 7196f26aa05SWill Deacon BUG_ON(i > 0); 7206f26aa05SWill Deacon info->trigger = wp->attr.bp_addr; 7216f26aa05SWill Deacon } else { 7226f26aa05SWill Deacon if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) 7236f26aa05SWill Deacon alignment_mask = 0x7; 7246f26aa05SWill Deacon else 7256f26aa05SWill Deacon alignment_mask = 0x3; 7266f26aa05SWill Deacon 7276f26aa05SWill Deacon /* Check if the watchpoint value matches. */ 7286f26aa05SWill Deacon val = read_wb_reg(ARM_BASE_WVR + i); 7296f26aa05SWill Deacon if (val != (addr & ~alignment_mask)) 7306f26aa05SWill Deacon goto unlock; 7316f26aa05SWill Deacon 7326f26aa05SWill Deacon /* Possible match, check the byte address select. */ 7336f26aa05SWill Deacon ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); 7346f26aa05SWill Deacon decode_ctrl_reg(ctrl_reg, &ctrl); 7356f26aa05SWill Deacon if (!((1 << (addr & alignment_mask)) & ctrl.len)) 7366f26aa05SWill Deacon goto unlock; 7376f26aa05SWill Deacon 7386f26aa05SWill Deacon /* Check that the access type matches. */ 739bf880114SWill Deacon if (debug_exception_updates_fsr()) { 740bf880114SWill Deacon access = (fsr & ARM_FSR_ACCESS_MASK) ? 741bf880114SWill Deacon HW_BREAKPOINT_W : HW_BREAKPOINT_R; 7426f26aa05SWill Deacon if (!(access & hw_breakpoint_type(wp))) 7436f26aa05SWill Deacon goto unlock; 744bf880114SWill Deacon } 7456f26aa05SWill Deacon 7466f26aa05SWill Deacon /* We have a winner. */ 7476f26aa05SWill Deacon info->trigger = addr; 748f81ef4a9SWill Deacon } 749f81ef4a9SWill Deacon 750f81ef4a9SWill Deacon pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); 751*eec13b42SWill Deacon 752*eec13b42SWill Deacon /* 753*eec13b42SWill Deacon * If we triggered a user watchpoint from a uaccess routine, 754*eec13b42SWill Deacon * then handle the stepping ourselves since userspace really 755*eec13b42SWill Deacon * can't help us with this. 756*eec13b42SWill Deacon */ 757*eec13b42SWill Deacon if (watchpoint_fault_on_uaccess(regs, info)) 758*eec13b42SWill Deacon goto step; 759*eec13b42SWill Deacon 76093a04a34SWill Deacon perf_bp_event(wp, regs); 761f81ef4a9SWill Deacon 762f81ef4a9SWill Deacon /* 763*eec13b42SWill Deacon * Defer stepping to the overflow handler if one is installed. 764*eec13b42SWill Deacon * Otherwise, insert a temporary mismatch breakpoint so that 765*eec13b42SWill Deacon * we can single-step over the watchpoint trigger. 766f81ef4a9SWill Deacon */ 767*eec13b42SWill Deacon if (!is_default_overflow_handler(wp)) 768*eec13b42SWill Deacon goto unlock; 769f81ef4a9SWill Deacon 770*eec13b42SWill Deacon step: 771*eec13b42SWill Deacon enable_single_step(wp, instruction_pointer(regs)); 7726f26aa05SWill Deacon unlock: 773f81ef4a9SWill Deacon rcu_read_unlock(); 774f81ef4a9SWill Deacon } 775f81ef4a9SWill Deacon } 776f81ef4a9SWill Deacon 77793a04a34SWill Deacon static void watchpoint_single_step_handler(unsigned long pc) 77893a04a34SWill Deacon { 77993a04a34SWill Deacon int i; 7804a55c18eSWill Deacon struct perf_event *wp, **slots; 78193a04a34SWill Deacon struct arch_hw_breakpoint *info; 78293a04a34SWill Deacon 7831436c1aaSChristoph Lameter slots = this_cpu_ptr(wp_on_reg); 7844a55c18eSWill Deacon 785c512de95SWill Deacon for (i = 0; i < core_num_wrps; ++i) { 78693a04a34SWill Deacon rcu_read_lock(); 78793a04a34SWill Deacon 78893a04a34SWill Deacon wp = slots[i]; 78993a04a34SWill Deacon 79093a04a34SWill Deacon if (wp == NULL) 79193a04a34SWill Deacon goto unlock; 79293a04a34SWill Deacon 79393a04a34SWill Deacon info = counter_arch_bp(wp); 79493a04a34SWill Deacon if (!info->step_ctrl.enabled) 79593a04a34SWill Deacon goto unlock; 79693a04a34SWill Deacon 79793a04a34SWill Deacon /* 79893a04a34SWill Deacon * Restore the original watchpoint if we've completed the 79993a04a34SWill Deacon * single-step. 80093a04a34SWill Deacon */ 8019ebb3cbcSWill Deacon if (info->trigger != pc) 8029ebb3cbcSWill Deacon disable_single_step(wp); 80393a04a34SWill Deacon 80493a04a34SWill Deacon unlock: 80593a04a34SWill Deacon rcu_read_unlock(); 80693a04a34SWill Deacon } 80793a04a34SWill Deacon } 80893a04a34SWill Deacon 809f81ef4a9SWill Deacon static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) 810f81ef4a9SWill Deacon { 811f81ef4a9SWill Deacon int i; 812f81ef4a9SWill Deacon u32 ctrl_reg, val, addr; 8134a55c18eSWill Deacon struct perf_event *bp, **slots; 814f81ef4a9SWill Deacon struct arch_hw_breakpoint *info; 815f81ef4a9SWill Deacon struct arch_hw_breakpoint_ctrl ctrl; 816f81ef4a9SWill Deacon 8171436c1aaSChristoph Lameter slots = this_cpu_ptr(bp_on_reg); 8184a55c18eSWill Deacon 819f81ef4a9SWill Deacon /* The exception entry code places the amended lr in the PC. */ 820f81ef4a9SWill Deacon addr = regs->ARM_pc; 821f81ef4a9SWill Deacon 82293a04a34SWill Deacon /* Check the currently installed breakpoints first. */ 82393a04a34SWill Deacon for (i = 0; i < core_num_brps; ++i) { 824f81ef4a9SWill Deacon rcu_read_lock(); 825f81ef4a9SWill Deacon 826f81ef4a9SWill Deacon bp = slots[i]; 827f81ef4a9SWill Deacon 8289ebb3cbcSWill Deacon if (bp == NULL) 8299ebb3cbcSWill Deacon goto unlock; 830f81ef4a9SWill Deacon 8319ebb3cbcSWill Deacon info = counter_arch_bp(bp); 832f81ef4a9SWill Deacon 833f81ef4a9SWill Deacon /* Check if the breakpoint value matches. */ 834f81ef4a9SWill Deacon val = read_wb_reg(ARM_BASE_BVR + i); 835f81ef4a9SWill Deacon if (val != (addr & ~0x3)) 8369ebb3cbcSWill Deacon goto mismatch; 837f81ef4a9SWill Deacon 838f81ef4a9SWill Deacon /* Possible match, check the byte address select to confirm. */ 839f81ef4a9SWill Deacon ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); 840f81ef4a9SWill Deacon decode_ctrl_reg(ctrl_reg, &ctrl); 841f81ef4a9SWill Deacon if ((1 << (addr & 0x3)) & ctrl.len) { 842f81ef4a9SWill Deacon info->trigger = addr; 843f81ef4a9SWill Deacon pr_debug("breakpoint fired: address = 0x%x\n", addr); 844f81ef4a9SWill Deacon perf_bp_event(bp, regs); 8459ebb3cbcSWill Deacon if (!bp->overflow_handler) 8469ebb3cbcSWill Deacon enable_single_step(bp, addr); 8479ebb3cbcSWill Deacon goto unlock; 848f81ef4a9SWill Deacon } 849f81ef4a9SWill Deacon 8509ebb3cbcSWill Deacon mismatch: 8519ebb3cbcSWill Deacon /* If we're stepping a breakpoint, it can now be restored. */ 8529ebb3cbcSWill Deacon if (info->step_ctrl.enabled) 8539ebb3cbcSWill Deacon disable_single_step(bp); 8549ebb3cbcSWill Deacon unlock: 855f81ef4a9SWill Deacon rcu_read_unlock(); 856f81ef4a9SWill Deacon } 85793a04a34SWill Deacon 85893a04a34SWill Deacon /* Handle any pending watchpoint single-step breakpoints. */ 85993a04a34SWill Deacon watchpoint_single_step_handler(addr); 860f81ef4a9SWill Deacon } 861f81ef4a9SWill Deacon 862f81ef4a9SWill Deacon /* 863f81ef4a9SWill Deacon * Called from either the Data Abort Handler [watchpoint] or the 86402fe2845SRussell King * Prefetch Abort Handler [breakpoint] with interrupts disabled. 865f81ef4a9SWill Deacon */ 866f81ef4a9SWill Deacon static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, 867f81ef4a9SWill Deacon struct pt_regs *regs) 868f81ef4a9SWill Deacon { 8697e202696SWill Deacon int ret = 0; 870f81ef4a9SWill Deacon u32 dscr; 871f81ef4a9SWill Deacon 87202fe2845SRussell King preempt_disable(); 87302fe2845SRussell King 87402fe2845SRussell King if (interrupts_enabled(regs)) 87502fe2845SRussell King local_irq_enable(); 8767e202696SWill Deacon 877f81ef4a9SWill Deacon /* We only handle watchpoints and hardware breakpoints. */ 8789e962f76SDietmar Eggemann ARM_DBG_READ(c0, c1, 0, dscr); 879f81ef4a9SWill Deacon 880f81ef4a9SWill Deacon /* Perform perf callbacks. */ 881f81ef4a9SWill Deacon switch (ARM_DSCR_MOE(dscr)) { 882f81ef4a9SWill Deacon case ARM_ENTRY_BREAKPOINT: 883f81ef4a9SWill Deacon breakpoint_handler(addr, regs); 884f81ef4a9SWill Deacon break; 885f81ef4a9SWill Deacon case ARM_ENTRY_ASYNC_WATCHPOINT: 886235584b6SJoe Perches WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); 8872d0e988dSGustavo A. R. Silva /* Fall through */ 888f81ef4a9SWill Deacon case ARM_ENTRY_SYNC_WATCHPOINT: 8896f26aa05SWill Deacon watchpoint_handler(addr, fsr, regs); 890f81ef4a9SWill Deacon break; 891f81ef4a9SWill Deacon default: 8927e202696SWill Deacon ret = 1; /* Unhandled fault. */ 893f81ef4a9SWill Deacon } 894f81ef4a9SWill Deacon 8957e202696SWill Deacon preempt_enable(); 8967e202696SWill Deacon 897f81ef4a9SWill Deacon return ret; 898f81ef4a9SWill Deacon } 899f81ef4a9SWill Deacon 900f81ef4a9SWill Deacon /* 901f81ef4a9SWill Deacon * One-time initialisation. 902f81ef4a9SWill Deacon */ 9030d352e3dSWill Deacon static cpumask_t debug_err_mask; 9040d352e3dSWill Deacon 9050d352e3dSWill Deacon static int debug_reg_trap(struct pt_regs *regs, unsigned int instr) 9060d352e3dSWill Deacon { 9070d352e3dSWill Deacon int cpu = smp_processor_id(); 9080d352e3dSWill Deacon 9098b521cb2SJoe Perches pr_warn("Debug register access (0x%x) caused undefined instruction on CPU %d\n", 9100d352e3dSWill Deacon instr, cpu); 9110d352e3dSWill Deacon 9120d352e3dSWill Deacon /* Set the error flag for this CPU and skip the faulting instruction. */ 9130d352e3dSWill Deacon cpumask_set_cpu(cpu, &debug_err_mask); 9140d352e3dSWill Deacon instruction_pointer(regs) += 4; 9150d352e3dSWill Deacon return 0; 9160d352e3dSWill Deacon } 9170d352e3dSWill Deacon 9180d352e3dSWill Deacon static struct undef_hook debug_reg_hook = { 9190d352e3dSWill Deacon .instr_mask = 0x0fe80f10, 9200d352e3dSWill Deacon .instr_val = 0x0e000e10, 9210d352e3dSWill Deacon .fn = debug_reg_trap, 9220d352e3dSWill Deacon }; 9230d352e3dSWill Deacon 92457ba8997SDietmar Eggemann /* Does this core support OS Save and Restore? */ 92557ba8997SDietmar Eggemann static bool core_has_os_save_restore(void) 92657ba8997SDietmar Eggemann { 92757ba8997SDietmar Eggemann u32 oslsr; 92857ba8997SDietmar Eggemann 92957ba8997SDietmar Eggemann switch (get_debug_arch()) { 93057ba8997SDietmar Eggemann case ARM_DEBUG_ARCH_V7_1: 93157ba8997SDietmar Eggemann return true; 93257ba8997SDietmar Eggemann case ARM_DEBUG_ARCH_V7_ECP14: 93357ba8997SDietmar Eggemann ARM_DBG_READ(c1, c1, 4, oslsr); 93457ba8997SDietmar Eggemann if (oslsr & ARM_OSLSR_OSLM0) 93557ba8997SDietmar Eggemann return true; 9362d0e988dSGustavo A. R. Silva /* Else, fall through */ 93757ba8997SDietmar Eggemann default: 93857ba8997SDietmar Eggemann return false; 93957ba8997SDietmar Eggemann } 94057ba8997SDietmar Eggemann } 94157ba8997SDietmar Eggemann 9429b377e21SSebastian Andrzej Siewior static void reset_ctrl_regs(unsigned int cpu) 943f81ef4a9SWill Deacon { 9449b377e21SSebastian Andrzej Siewior int i, raw_num_brps, err = 0; 945e64877dcSWill Deacon u32 val; 946f81ef4a9SWill Deacon 947ac88e071SWill Deacon /* 948ac88e071SWill Deacon * v7 debug contains save and restore registers so that debug state 949ed19b739SWill Deacon * can be maintained across low-power modes without leaving the debug 950ed19b739SWill Deacon * logic powered up. It is IMPLEMENTATION DEFINED whether we can access 951ed19b739SWill Deacon * the debug registers out of reset, so we must unlock the OS Lock 952ed19b739SWill Deacon * Access Register to avoid taking undefined instruction exceptions 953ed19b739SWill Deacon * later on. 954ac88e071SWill Deacon */ 955b5d5b8f9SWill Deacon switch (debug_arch) { 956a26bce12SWill Deacon case ARM_DEBUG_ARCH_V6: 957a26bce12SWill Deacon case ARM_DEBUG_ARCH_V6_1: 9587f4050a0SWill Deacon /* ARMv6 cores clear the registers out of reset. */ 9597f4050a0SWill Deacon goto out_mdbgen; 960b5d5b8f9SWill Deacon case ARM_DEBUG_ARCH_V7_ECP14: 961ac88e071SWill Deacon /* 962c09bae70SWill Deacon * Ensure sticky power-down is clear (i.e. debug logic is 963c09bae70SWill Deacon * powered up). 964c09bae70SWill Deacon */ 9659e962f76SDietmar Eggemann ARM_DBG_READ(c1, c5, 4, val); 966e64877dcSWill Deacon if ((val & 0x1) == 0) 967b5d5b8f9SWill Deacon err = -EPERM; 968e64877dcSWill Deacon 96957ba8997SDietmar Eggemann if (!has_ossr) 970e64877dcSWill Deacon goto clear_vcr; 971b5d5b8f9SWill Deacon break; 972b5d5b8f9SWill Deacon case ARM_DEBUG_ARCH_V7_1: 973b5d5b8f9SWill Deacon /* 974b5d5b8f9SWill Deacon * Ensure the OS double lock is clear. 975b5d5b8f9SWill Deacon */ 9769e962f76SDietmar Eggemann ARM_DBG_READ(c1, c3, 4, val); 977e64877dcSWill Deacon if ((val & 0x1) == 1) 978b5d5b8f9SWill Deacon err = -EPERM; 979b5d5b8f9SWill Deacon break; 980b5d5b8f9SWill Deacon } 981b5d5b8f9SWill Deacon 982b5d5b8f9SWill Deacon if (err) { 98368a154fcSSantosh Shilimkar pr_warn_once("CPU %d debug is powered down!\n", cpu); 9840d352e3dSWill Deacon cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); 985c09bae70SWill Deacon return; 986c09bae70SWill Deacon } 987c09bae70SWill Deacon 988c09bae70SWill Deacon /* 989e64877dcSWill Deacon * Unconditionally clear the OS lock by writing a value 99002051eadSDietmar Eggemann * other than CS_LAR_KEY to the access register. 991ac88e071SWill Deacon */ 992184901a0SMathieu Poirier ARM_DBG_WRITE(c1, c0, 4, ~CORESIGHT_UNLOCK); 993ac88e071SWill Deacon isb(); 994e89c0d70SWill Deacon 995e89c0d70SWill Deacon /* 996e89c0d70SWill Deacon * Clear any configured vector-catch events before 997e89c0d70SWill Deacon * enabling monitor mode. 998e89c0d70SWill Deacon */ 999e64877dcSWill Deacon clear_vcr: 10009e962f76SDietmar Eggemann ARM_DBG_WRITE(c0, c7, 0, 0); 1001e89c0d70SWill Deacon isb(); 1002ac88e071SWill Deacon 1003614bea50SWill Deacon if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { 100468a154fcSSantosh Shilimkar pr_warn_once("CPU %d failed to disable vector catch\n", cpu); 1005f81ef4a9SWill Deacon return; 1006614bea50SWill Deacon } 1007f81ef4a9SWill Deacon 1008614bea50SWill Deacon /* 1009614bea50SWill Deacon * The control/value register pairs are UNKNOWN out of reset so 1010614bea50SWill Deacon * clear them to avoid spurious debug events. 1011614bea50SWill Deacon */ 1012c512de95SWill Deacon raw_num_brps = get_num_brp_resources(); 1013c512de95SWill Deacon for (i = 0; i < raw_num_brps; ++i) { 1014f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_BCR + i, 0UL); 1015f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_BVR + i, 0UL); 1016f81ef4a9SWill Deacon } 1017f81ef4a9SWill Deacon 1018f81ef4a9SWill Deacon for (i = 0; i < core_num_wrps; ++i) { 1019f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_WCR + i, 0UL); 1020f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_WVR + i, 0UL); 1021f81ef4a9SWill Deacon } 1022614bea50SWill Deacon 1023614bea50SWill Deacon if (cpumask_intersects(&debug_err_mask, cpumask_of(cpu))) { 102468a154fcSSantosh Shilimkar pr_warn_once("CPU %d failed to clear debug register pairs\n", cpu); 1025614bea50SWill Deacon return; 1026614bea50SWill Deacon } 1027614bea50SWill Deacon 1028614bea50SWill Deacon /* 1029614bea50SWill Deacon * Have a crack at enabling monitor mode. We don't actually need 1030614bea50SWill Deacon * it yet, but reporting an error early is useful if it fails. 1031614bea50SWill Deacon */ 10327f4050a0SWill Deacon out_mdbgen: 1033614bea50SWill Deacon if (enable_monitor_mode()) 1034614bea50SWill Deacon cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu)); 1035f81ef4a9SWill Deacon } 1036f81ef4a9SWill Deacon 10379b377e21SSebastian Andrzej Siewior static int dbg_reset_online(unsigned int cpu) 10387d99331eSWill Deacon { 10399b377e21SSebastian Andrzej Siewior local_irq_disable(); 10409b377e21SSebastian Andrzej Siewior reset_ctrl_regs(cpu); 10419b377e21SSebastian Andrzej Siewior local_irq_enable(); 10429b377e21SSebastian Andrzej Siewior return 0; 10437d99331eSWill Deacon } 10447d99331eSWill Deacon 10459a6eb310SDietmar Eggemann #ifdef CONFIG_CPU_PM 10469a6eb310SDietmar Eggemann static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action, 10479a6eb310SDietmar Eggemann void *v) 10489a6eb310SDietmar Eggemann { 10499a6eb310SDietmar Eggemann if (action == CPU_PM_EXIT) 10509b377e21SSebastian Andrzej Siewior reset_ctrl_regs(smp_processor_id()); 10519a6eb310SDietmar Eggemann 10529a6eb310SDietmar Eggemann return NOTIFY_OK; 10539a6eb310SDietmar Eggemann } 10549a6eb310SDietmar Eggemann 105550acff3cSBastian Hecht static struct notifier_block dbg_cpu_pm_nb = { 10569a6eb310SDietmar Eggemann .notifier_call = dbg_cpu_pm_notify, 10579a6eb310SDietmar Eggemann }; 10589a6eb310SDietmar Eggemann 10599a6eb310SDietmar Eggemann static void __init pm_init(void) 10609a6eb310SDietmar Eggemann { 10619a6eb310SDietmar Eggemann cpu_pm_register_notifier(&dbg_cpu_pm_nb); 10629a6eb310SDietmar Eggemann } 10639a6eb310SDietmar Eggemann #else 10649a6eb310SDietmar Eggemann static inline void pm_init(void) 10659a6eb310SDietmar Eggemann { 10669a6eb310SDietmar Eggemann } 10679a6eb310SDietmar Eggemann #endif 10689a6eb310SDietmar Eggemann 1069f81ef4a9SWill Deacon static int __init arch_hw_breakpoint_init(void) 1070f81ef4a9SWill Deacon { 10719b377e21SSebastian Andrzej Siewior int ret; 10729b377e21SSebastian Andrzej Siewior 1073f81ef4a9SWill Deacon debug_arch = get_debug_arch(); 1074f81ef4a9SWill Deacon 107566e1cfe6SWill Deacon if (!debug_arch_supported()) { 1076f81ef4a9SWill Deacon pr_info("debug architecture 0x%x unsupported.\n", debug_arch); 10778fbf397cSWill Deacon return 0; 1078f81ef4a9SWill Deacon } 1079f81ef4a9SWill Deacon 1080ddc37832SMark Rutland /* 1081ddc37832SMark Rutland * Scorpion CPUs (at least those in APQ8060) seem to set DBGPRSR.SPD 1082ddc37832SMark Rutland * whenever a WFI is issued, even if the core is not powered down, in 1083ddc37832SMark Rutland * violation of the architecture. When DBGPRSR.SPD is set, accesses to 1084ddc37832SMark Rutland * breakpoint and watchpoint registers are treated as undefined, so 1085ddc37832SMark Rutland * this results in boot time and runtime failures when these are 1086ddc37832SMark Rutland * accessed and we unexpectedly take a trap. 1087ddc37832SMark Rutland * 1088ddc37832SMark Rutland * It's not clear if/how this can be worked around, so we blacklist 1089ddc37832SMark Rutland * Scorpion CPUs to avoid these issues. 1090ddc37832SMark Rutland */ 1091ddc37832SMark Rutland if (read_cpuid_part() == ARM_CPU_PART_SCORPION) { 1092ddc37832SMark Rutland pr_info("Scorpion CPU detected. Hardware breakpoints and watchpoints disabled\n"); 1093ddc37832SMark Rutland return 0; 1094ddc37832SMark Rutland } 1095ddc37832SMark Rutland 109657ba8997SDietmar Eggemann has_ossr = core_has_os_save_restore(); 109757ba8997SDietmar Eggemann 1098f81ef4a9SWill Deacon /* Determine how many BRPs/WRPs are available. */ 1099f81ef4a9SWill Deacon core_num_brps = get_num_brps(); 1100f81ef4a9SWill Deacon core_num_wrps = get_num_wrps(); 1101f81ef4a9SWill Deacon 11020d352e3dSWill Deacon /* 11030d352e3dSWill Deacon * We need to tread carefully here because DBGSWENABLE may be 11040d352e3dSWill Deacon * driven low on this core and there isn't an architected way to 11050d352e3dSWill Deacon * determine that. 11060d352e3dSWill Deacon */ 1107fe2a5cd8SSebastian Andrzej Siewior cpus_read_lock(); 11080d352e3dSWill Deacon register_undef_hook(&debug_reg_hook); 1109f81ef4a9SWill Deacon 1110f81ef4a9SWill Deacon /* 11119b377e21SSebastian Andrzej Siewior * Register CPU notifier which resets the breakpoint resources. We 11129b377e21SSebastian Andrzej Siewior * assume that a halting debugger will leave the world in a nice state 11139b377e21SSebastian Andrzej Siewior * for us. 1114f81ef4a9SWill Deacon */ 1115fe2a5cd8SSebastian Andrzej Siewior ret = cpuhp_setup_state_cpuslocked(CPUHP_AP_ONLINE_DYN, 1116fe2a5cd8SSebastian Andrzej Siewior "arm/hw_breakpoint:online", 11179b377e21SSebastian Andrzej Siewior dbg_reset_online, NULL); 11180d352e3dSWill Deacon unregister_undef_hook(&debug_reg_hook); 11199b377e21SSebastian Andrzej Siewior if (WARN_ON(ret < 0) || !cpumask_empty(&debug_err_mask)) { 1120c09bae70SWill Deacon core_num_brps = 0; 1121c09bae70SWill Deacon core_num_wrps = 0; 11229b377e21SSebastian Andrzej Siewior if (ret > 0) 11231b3b2250STony Lindgren cpuhp_remove_state_nocalls_cpuslocked(ret); 1124fe2a5cd8SSebastian Andrzej Siewior cpus_read_unlock(); 1125c09bae70SWill Deacon return 0; 1126c09bae70SWill Deacon } 1127ac88e071SWill Deacon 11280d352e3dSWill Deacon pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n", 11290d352e3dSWill Deacon core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " : 11300d352e3dSWill Deacon "", core_num_wrps); 11310d352e3dSWill Deacon 1132ac88e071SWill Deacon /* Work out the maximum supported watchpoint length. */ 1133ac88e071SWill Deacon max_watchpoint_len = get_max_wp_len(); 1134ac88e071SWill Deacon pr_info("maximum watchpoint size is %u bytes.\n", 1135ac88e071SWill Deacon max_watchpoint_len); 1136f81ef4a9SWill Deacon 1137f81ef4a9SWill Deacon /* Register debug fault handler. */ 1138f7b8156dSCatalin Marinas hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, 1139f7b8156dSCatalin Marinas TRAP_HWBKPT, "watchpoint debug exception"); 1140f7b8156dSCatalin Marinas hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP, 1141f7b8156dSCatalin Marinas TRAP_HWBKPT, "breakpoint debug exception"); 1142fe2a5cd8SSebastian Andrzej Siewior cpus_read_unlock(); 1143f81ef4a9SWill Deacon 11449b377e21SSebastian Andrzej Siewior /* Register PM notifiers. */ 11459a6eb310SDietmar Eggemann pm_init(); 11468fbf397cSWill Deacon return 0; 1147f81ef4a9SWill Deacon } 1148f81ef4a9SWill Deacon arch_initcall(arch_hw_breakpoint_init); 1149f81ef4a9SWill Deacon 1150f81ef4a9SWill Deacon void hw_breakpoint_pmu_read(struct perf_event *bp) 1151f81ef4a9SWill Deacon { 1152f81ef4a9SWill Deacon } 1153f81ef4a9SWill Deacon 1154f81ef4a9SWill Deacon /* 1155f81ef4a9SWill Deacon * Dummy function to register with die_notifier. 1156f81ef4a9SWill Deacon */ 1157f81ef4a9SWill Deacon int hw_breakpoint_exceptions_notify(struct notifier_block *unused, 1158f81ef4a9SWill Deacon unsigned long val, void *data) 1159f81ef4a9SWill Deacon { 1160f81ef4a9SWill Deacon return NOTIFY_DONE; 1161f81ef4a9SWill Deacon } 1162