1f81ef4a9SWill Deacon /* 2f81ef4a9SWill Deacon * This program is free software; you can redistribute it and/or modify 3f81ef4a9SWill Deacon * it under the terms of the GNU General Public License version 2 as 4f81ef4a9SWill Deacon * published by the Free Software Foundation. 5f81ef4a9SWill Deacon * 6f81ef4a9SWill Deacon * This program is distributed in the hope that it will be useful, 7f81ef4a9SWill Deacon * but WITHOUT ANY WARRANTY; without even the implied warranty of 8f81ef4a9SWill Deacon * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9f81ef4a9SWill Deacon * GNU General Public License for more details. 10f81ef4a9SWill Deacon * 11f81ef4a9SWill Deacon * You should have received a copy of the GNU General Public License 12f81ef4a9SWill Deacon * along with this program; if not, write to the Free Software 13f81ef4a9SWill Deacon * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 14f81ef4a9SWill Deacon * 15f81ef4a9SWill Deacon * Copyright (C) 2009, 2010 ARM Limited 16f81ef4a9SWill Deacon * 17f81ef4a9SWill Deacon * Author: Will Deacon <will.deacon@arm.com> 18f81ef4a9SWill Deacon */ 19f81ef4a9SWill Deacon 20f81ef4a9SWill Deacon /* 21f81ef4a9SWill Deacon * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, 22f81ef4a9SWill Deacon * using the CPU's debug registers. 23f81ef4a9SWill Deacon */ 24f81ef4a9SWill Deacon #define pr_fmt(fmt) "hw-breakpoint: " fmt 25f81ef4a9SWill Deacon 26f81ef4a9SWill Deacon #include <linux/errno.h> 277e202696SWill Deacon #include <linux/hardirq.h> 28f81ef4a9SWill Deacon #include <linux/perf_event.h> 29f81ef4a9SWill Deacon #include <linux/hw_breakpoint.h> 30f81ef4a9SWill Deacon #include <linux/smp.h> 31f81ef4a9SWill Deacon 32f81ef4a9SWill Deacon #include <asm/cacheflush.h> 33f81ef4a9SWill Deacon #include <asm/cputype.h> 34f81ef4a9SWill Deacon #include <asm/current.h> 35f81ef4a9SWill Deacon #include <asm/hw_breakpoint.h> 36f81ef4a9SWill Deacon #include <asm/kdebug.h> 37f81ef4a9SWill Deacon #include <asm/system.h> 38f81ef4a9SWill Deacon #include <asm/traps.h> 39f81ef4a9SWill Deacon 40f81ef4a9SWill Deacon /* Breakpoint currently in use for each BRP. */ 41f81ef4a9SWill Deacon static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); 42f81ef4a9SWill Deacon 43f81ef4a9SWill Deacon /* Watchpoint currently in use for each WRP. */ 44f81ef4a9SWill Deacon static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); 45f81ef4a9SWill Deacon 46f81ef4a9SWill Deacon /* Number of BRP/WRP registers on this CPU. */ 47f81ef4a9SWill Deacon static int core_num_brps; 480017ff42SWill Deacon static int core_num_reserved_brps; 49f81ef4a9SWill Deacon static int core_num_wrps; 50f81ef4a9SWill Deacon 51f81ef4a9SWill Deacon /* Debug architecture version. */ 52f81ef4a9SWill Deacon static u8 debug_arch; 53f81ef4a9SWill Deacon 54f81ef4a9SWill Deacon /* Maximum supported watchpoint length. */ 55f81ef4a9SWill Deacon static u8 max_watchpoint_len; 56f81ef4a9SWill Deacon 57f81ef4a9SWill Deacon #define READ_WB_REG_CASE(OP2, M, VAL) \ 58f81ef4a9SWill Deacon case ((OP2 << 4) + M): \ 59f81ef4a9SWill Deacon ARM_DBG_READ(c ## M, OP2, VAL); \ 60f81ef4a9SWill Deacon break 61f81ef4a9SWill Deacon 62f81ef4a9SWill Deacon #define WRITE_WB_REG_CASE(OP2, M, VAL) \ 63f81ef4a9SWill Deacon case ((OP2 << 4) + M): \ 64f81ef4a9SWill Deacon ARM_DBG_WRITE(c ## M, OP2, VAL);\ 65f81ef4a9SWill Deacon break 66f81ef4a9SWill Deacon 67f81ef4a9SWill Deacon #define GEN_READ_WB_REG_CASES(OP2, VAL) \ 68f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 0, VAL); \ 69f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 1, VAL); \ 70f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 2, VAL); \ 71f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 3, VAL); \ 72f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 4, VAL); \ 73f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 5, VAL); \ 74f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 6, VAL); \ 75f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 7, VAL); \ 76f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 8, VAL); \ 77f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 9, VAL); \ 78f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 10, VAL); \ 79f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 11, VAL); \ 80f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 12, VAL); \ 81f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 13, VAL); \ 82f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 14, VAL); \ 83f81ef4a9SWill Deacon READ_WB_REG_CASE(OP2, 15, VAL) 84f81ef4a9SWill Deacon 85f81ef4a9SWill Deacon #define GEN_WRITE_WB_REG_CASES(OP2, VAL) \ 86f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 0, VAL); \ 87f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 1, VAL); \ 88f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 2, VAL); \ 89f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 3, VAL); \ 90f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 4, VAL); \ 91f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 5, VAL); \ 92f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 6, VAL); \ 93f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 7, VAL); \ 94f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 8, VAL); \ 95f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 9, VAL); \ 96f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 10, VAL); \ 97f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 11, VAL); \ 98f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 12, VAL); \ 99f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 13, VAL); \ 100f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 14, VAL); \ 101f81ef4a9SWill Deacon WRITE_WB_REG_CASE(OP2, 15, VAL) 102f81ef4a9SWill Deacon 103f81ef4a9SWill Deacon static u32 read_wb_reg(int n) 104f81ef4a9SWill Deacon { 105f81ef4a9SWill Deacon u32 val = 0; 106f81ef4a9SWill Deacon 107f81ef4a9SWill Deacon switch (n) { 108f81ef4a9SWill Deacon GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val); 109f81ef4a9SWill Deacon GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val); 110f81ef4a9SWill Deacon GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val); 111f81ef4a9SWill Deacon GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val); 112f81ef4a9SWill Deacon default: 113f81ef4a9SWill Deacon pr_warning("attempt to read from unknown breakpoint " 114f81ef4a9SWill Deacon "register %d\n", n); 115f81ef4a9SWill Deacon } 116f81ef4a9SWill Deacon 117f81ef4a9SWill Deacon return val; 118f81ef4a9SWill Deacon } 119f81ef4a9SWill Deacon 120f81ef4a9SWill Deacon static void write_wb_reg(int n, u32 val) 121f81ef4a9SWill Deacon { 122f81ef4a9SWill Deacon switch (n) { 123f81ef4a9SWill Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val); 124f81ef4a9SWill Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val); 125f81ef4a9SWill Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val); 126f81ef4a9SWill Deacon GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val); 127f81ef4a9SWill Deacon default: 128f81ef4a9SWill Deacon pr_warning("attempt to write to unknown breakpoint " 129f81ef4a9SWill Deacon "register %d\n", n); 130f81ef4a9SWill Deacon } 131f81ef4a9SWill Deacon isb(); 132f81ef4a9SWill Deacon } 133f81ef4a9SWill Deacon 1340017ff42SWill Deacon /* Determine debug architecture. */ 1350017ff42SWill Deacon static u8 get_debug_arch(void) 1360017ff42SWill Deacon { 1370017ff42SWill Deacon u32 didr; 1380017ff42SWill Deacon 1390017ff42SWill Deacon /* Do we implement the extended CPUID interface? */ 14066e1cfe6SWill Deacon if (WARN_ONCE((((read_cpuid_id() >> 16) & 0xf) != 0xf), 14166e1cfe6SWill Deacon "CPUID feature registers not supported. " 14266e1cfe6SWill Deacon "Assuming v6 debug is present.\n")) 1430017ff42SWill Deacon return ARM_DEBUG_ARCH_V6; 1440017ff42SWill Deacon 1450017ff42SWill Deacon ARM_DBG_READ(c0, 0, didr); 1460017ff42SWill Deacon return (didr >> 16) & 0xf; 1470017ff42SWill Deacon } 1480017ff42SWill Deacon 1490017ff42SWill Deacon u8 arch_get_debug_arch(void) 1500017ff42SWill Deacon { 1510017ff42SWill Deacon return debug_arch; 1520017ff42SWill Deacon } 1530017ff42SWill Deacon 15466e1cfe6SWill Deacon static int debug_arch_supported(void) 15566e1cfe6SWill Deacon { 15666e1cfe6SWill Deacon u8 arch = get_debug_arch(); 15766e1cfe6SWill Deacon return arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14; 15866e1cfe6SWill Deacon } 15966e1cfe6SWill Deacon 1600017ff42SWill Deacon /* Determine number of BRP register available. */ 1610017ff42SWill Deacon static int get_num_brp_resources(void) 1620017ff42SWill Deacon { 1630017ff42SWill Deacon u32 didr; 1640017ff42SWill Deacon ARM_DBG_READ(c0, 0, didr); 1650017ff42SWill Deacon return ((didr >> 24) & 0xf) + 1; 1660017ff42SWill Deacon } 1670017ff42SWill Deacon 1680017ff42SWill Deacon /* Does this core support mismatch breakpoints? */ 1690017ff42SWill Deacon static int core_has_mismatch_brps(void) 1700017ff42SWill Deacon { 1710017ff42SWill Deacon return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 && 1720017ff42SWill Deacon get_num_brp_resources() > 1); 1730017ff42SWill Deacon } 1740017ff42SWill Deacon 1750017ff42SWill Deacon /* Determine number of usable WRPs available. */ 1760017ff42SWill Deacon static int get_num_wrps(void) 1770017ff42SWill Deacon { 1780017ff42SWill Deacon /* 1790017ff42SWill Deacon * FIXME: When a watchpoint fires, the only way to work out which 1800017ff42SWill Deacon * watchpoint it was is by disassembling the faulting instruction 1810017ff42SWill Deacon * and working out the address of the memory access. 1820017ff42SWill Deacon * 1830017ff42SWill Deacon * Furthermore, we can only do this if the watchpoint was precise 1840017ff42SWill Deacon * since imprecise watchpoints prevent us from calculating register 1850017ff42SWill Deacon * based addresses. 1860017ff42SWill Deacon * 1870017ff42SWill Deacon * Providing we have more than 1 breakpoint register, we only report 1880017ff42SWill Deacon * a single watchpoint register for the time being. This way, we always 1890017ff42SWill Deacon * know which watchpoint fired. In the future we can either add a 1900017ff42SWill Deacon * disassembler and address generation emulator, or we can insert a 1910017ff42SWill Deacon * check to see if the DFAR is set on watchpoint exception entry 1920017ff42SWill Deacon * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows 1930017ff42SWill Deacon * that it is set on some implementations]. 1940017ff42SWill Deacon */ 1950017ff42SWill Deacon 1960017ff42SWill Deacon #if 0 1970017ff42SWill Deacon int wrps; 1980017ff42SWill Deacon u32 didr; 1990017ff42SWill Deacon ARM_DBG_READ(c0, 0, didr); 2000017ff42SWill Deacon wrps = ((didr >> 28) & 0xf) + 1; 2010017ff42SWill Deacon #endif 2020017ff42SWill Deacon int wrps = 1; 2030017ff42SWill Deacon 2040017ff42SWill Deacon if (core_has_mismatch_brps() && wrps >= get_num_brp_resources()) 2050017ff42SWill Deacon wrps = get_num_brp_resources() - 1; 2060017ff42SWill Deacon 2070017ff42SWill Deacon return wrps; 2080017ff42SWill Deacon } 2090017ff42SWill Deacon 2100017ff42SWill Deacon /* We reserve one breakpoint for each watchpoint. */ 2110017ff42SWill Deacon static int get_num_reserved_brps(void) 2120017ff42SWill Deacon { 2130017ff42SWill Deacon if (core_has_mismatch_brps()) 2140017ff42SWill Deacon return get_num_wrps(); 2150017ff42SWill Deacon return 0; 2160017ff42SWill Deacon } 2170017ff42SWill Deacon 2180017ff42SWill Deacon /* Determine number of usable BRPs available. */ 2190017ff42SWill Deacon static int get_num_brps(void) 2200017ff42SWill Deacon { 2210017ff42SWill Deacon int brps = get_num_brp_resources(); 2220017ff42SWill Deacon if (core_has_mismatch_brps()) 2230017ff42SWill Deacon brps -= get_num_reserved_brps(); 2240017ff42SWill Deacon return brps; 2250017ff42SWill Deacon } 2260017ff42SWill Deacon 227f81ef4a9SWill Deacon /* 228f81ef4a9SWill Deacon * In order to access the breakpoint/watchpoint control registers, 229f81ef4a9SWill Deacon * we must be running in debug monitor mode. Unfortunately, we can 230f81ef4a9SWill Deacon * be put into halting debug mode at any time by an external debugger 231f81ef4a9SWill Deacon * but there is nothing we can do to prevent that. 232f81ef4a9SWill Deacon */ 233f81ef4a9SWill Deacon static int enable_monitor_mode(void) 234f81ef4a9SWill Deacon { 235f81ef4a9SWill Deacon u32 dscr; 236f81ef4a9SWill Deacon int ret = 0; 237f81ef4a9SWill Deacon 238f81ef4a9SWill Deacon ARM_DBG_READ(c1, 0, dscr); 239f81ef4a9SWill Deacon 240f81ef4a9SWill Deacon /* Ensure that halting mode is disabled. */ 2417d85d61fSStephen Boyd if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, 2427d85d61fSStephen Boyd "halting debug mode enabled. Unable to access hardware resources.\n")) { 243f81ef4a9SWill Deacon ret = -EPERM; 244f81ef4a9SWill Deacon goto out; 245f81ef4a9SWill Deacon } 246f81ef4a9SWill Deacon 2478fbf397cSWill Deacon /* If monitor mode is already enabled, just return. */ 2488fbf397cSWill Deacon if (dscr & ARM_DSCR_MDBGEN) 2498fbf397cSWill Deacon goto out; 2508fbf397cSWill Deacon 251f81ef4a9SWill Deacon /* Write to the corresponding DSCR. */ 2528fbf397cSWill Deacon switch (get_debug_arch()) { 253f81ef4a9SWill Deacon case ARM_DEBUG_ARCH_V6: 254f81ef4a9SWill Deacon case ARM_DEBUG_ARCH_V6_1: 255f81ef4a9SWill Deacon ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); 256f81ef4a9SWill Deacon break; 257f81ef4a9SWill Deacon case ARM_DEBUG_ARCH_V7_ECP14: 258f81ef4a9SWill Deacon ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); 259f81ef4a9SWill Deacon break; 260f81ef4a9SWill Deacon default: 261f81ef4a9SWill Deacon ret = -ENODEV; 262f81ef4a9SWill Deacon goto out; 263f81ef4a9SWill Deacon } 264f81ef4a9SWill Deacon 265f81ef4a9SWill Deacon /* Check that the write made it through. */ 266f81ef4a9SWill Deacon ARM_DBG_READ(c1, 0, dscr); 2678fbf397cSWill Deacon if (!(dscr & ARM_DSCR_MDBGEN)) 268f81ef4a9SWill Deacon ret = -EPERM; 269f81ef4a9SWill Deacon 270f81ef4a9SWill Deacon out: 271f81ef4a9SWill Deacon return ret; 272f81ef4a9SWill Deacon } 273f81ef4a9SWill Deacon 2748fbf397cSWill Deacon int hw_breakpoint_slots(int type) 2758fbf397cSWill Deacon { 27666e1cfe6SWill Deacon if (!debug_arch_supported()) 27766e1cfe6SWill Deacon return 0; 27866e1cfe6SWill Deacon 2798fbf397cSWill Deacon /* 2808fbf397cSWill Deacon * We can be called early, so don't rely on 2818fbf397cSWill Deacon * our static variables being initialised. 2828fbf397cSWill Deacon */ 2838fbf397cSWill Deacon switch (type) { 2848fbf397cSWill Deacon case TYPE_INST: 2858fbf397cSWill Deacon return get_num_brps(); 2868fbf397cSWill Deacon case TYPE_DATA: 2878fbf397cSWill Deacon return get_num_wrps(); 2888fbf397cSWill Deacon default: 2898fbf397cSWill Deacon pr_warning("unknown slot type: %d\n", type); 2908fbf397cSWill Deacon return 0; 2918fbf397cSWill Deacon } 2928fbf397cSWill Deacon } 2938fbf397cSWill Deacon 294f81ef4a9SWill Deacon /* 295f81ef4a9SWill Deacon * Check if 8-bit byte-address select is available. 296f81ef4a9SWill Deacon * This clobbers WRP 0. 297f81ef4a9SWill Deacon */ 298f81ef4a9SWill Deacon static u8 get_max_wp_len(void) 299f81ef4a9SWill Deacon { 300f81ef4a9SWill Deacon u32 ctrl_reg; 301f81ef4a9SWill Deacon struct arch_hw_breakpoint_ctrl ctrl; 302f81ef4a9SWill Deacon u8 size = 4; 303f81ef4a9SWill Deacon 304f81ef4a9SWill Deacon if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14) 305f81ef4a9SWill Deacon goto out; 306f81ef4a9SWill Deacon 307f81ef4a9SWill Deacon memset(&ctrl, 0, sizeof(ctrl)); 308f81ef4a9SWill Deacon ctrl.len = ARM_BREAKPOINT_LEN_8; 309f81ef4a9SWill Deacon ctrl_reg = encode_ctrl_reg(ctrl); 310f81ef4a9SWill Deacon 311f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_WVR, 0); 312f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_WCR, ctrl_reg); 313f81ef4a9SWill Deacon if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg) 314f81ef4a9SWill Deacon size = 8; 315f81ef4a9SWill Deacon 316f81ef4a9SWill Deacon out: 317f81ef4a9SWill Deacon return size; 318f81ef4a9SWill Deacon } 319f81ef4a9SWill Deacon 320f81ef4a9SWill Deacon u8 arch_get_max_wp_len(void) 321f81ef4a9SWill Deacon { 322f81ef4a9SWill Deacon return max_watchpoint_len; 323f81ef4a9SWill Deacon } 324f81ef4a9SWill Deacon 325f81ef4a9SWill Deacon /* 326f81ef4a9SWill Deacon * Install a perf counter breakpoint. 327f81ef4a9SWill Deacon */ 328f81ef4a9SWill Deacon int arch_install_hw_breakpoint(struct perf_event *bp) 329f81ef4a9SWill Deacon { 330f81ef4a9SWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 331f81ef4a9SWill Deacon struct perf_event **slot, **slots; 332f81ef4a9SWill Deacon int i, max_slots, ctrl_base, val_base, ret = 0; 33393a04a34SWill Deacon u32 addr, ctrl; 334f81ef4a9SWill Deacon 335f81ef4a9SWill Deacon /* Ensure that we are in monitor mode and halting mode is disabled. */ 336f81ef4a9SWill Deacon ret = enable_monitor_mode(); 337f81ef4a9SWill Deacon if (ret) 338f81ef4a9SWill Deacon goto out; 339f81ef4a9SWill Deacon 34093a04a34SWill Deacon addr = info->address; 34193a04a34SWill Deacon ctrl = encode_ctrl_reg(info->ctrl) | 0x1; 34293a04a34SWill Deacon 343f81ef4a9SWill Deacon if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 344f81ef4a9SWill Deacon /* Breakpoint */ 345f81ef4a9SWill Deacon ctrl_base = ARM_BASE_BCR; 346f81ef4a9SWill Deacon val_base = ARM_BASE_BVR; 3474a55c18eSWill Deacon slots = (struct perf_event **)__get_cpu_var(bp_on_reg); 3480017ff42SWill Deacon max_slots = core_num_brps; 3499ebb3cbcSWill Deacon if (info->step_ctrl.enabled) { 3509ebb3cbcSWill Deacon /* Override the breakpoint data with the step data. */ 3519ebb3cbcSWill Deacon addr = info->trigger & ~0x3; 3529ebb3cbcSWill Deacon ctrl = encode_ctrl_reg(info->step_ctrl); 3539ebb3cbcSWill Deacon } 354f81ef4a9SWill Deacon } else { 355f81ef4a9SWill Deacon /* Watchpoint */ 35693a04a34SWill Deacon if (info->step_ctrl.enabled) { 35793a04a34SWill Deacon /* Install into the reserved breakpoint region. */ 35893a04a34SWill Deacon ctrl_base = ARM_BASE_BCR + core_num_brps; 35993a04a34SWill Deacon val_base = ARM_BASE_BVR + core_num_brps; 36093a04a34SWill Deacon /* Override the watchpoint data with the step data. */ 36193a04a34SWill Deacon addr = info->trigger & ~0x3; 36293a04a34SWill Deacon ctrl = encode_ctrl_reg(info->step_ctrl); 36393a04a34SWill Deacon } else { 364f81ef4a9SWill Deacon ctrl_base = ARM_BASE_WCR; 365f81ef4a9SWill Deacon val_base = ARM_BASE_WVR; 36693a04a34SWill Deacon } 3674a55c18eSWill Deacon slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 368f81ef4a9SWill Deacon max_slots = core_num_wrps; 369f81ef4a9SWill Deacon } 370f81ef4a9SWill Deacon 371f81ef4a9SWill Deacon for (i = 0; i < max_slots; ++i) { 372f81ef4a9SWill Deacon slot = &slots[i]; 373f81ef4a9SWill Deacon 374f81ef4a9SWill Deacon if (!*slot) { 375f81ef4a9SWill Deacon *slot = bp; 376f81ef4a9SWill Deacon break; 377f81ef4a9SWill Deacon } 378f81ef4a9SWill Deacon } 379f81ef4a9SWill Deacon 3807d85d61fSStephen Boyd if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) { 381f81ef4a9SWill Deacon ret = -EBUSY; 382f81ef4a9SWill Deacon goto out; 383f81ef4a9SWill Deacon } 384f81ef4a9SWill Deacon 385f81ef4a9SWill Deacon /* Setup the address register. */ 38693a04a34SWill Deacon write_wb_reg(val_base + i, addr); 387f81ef4a9SWill Deacon 388f81ef4a9SWill Deacon /* Setup the control register. */ 38993a04a34SWill Deacon write_wb_reg(ctrl_base + i, ctrl); 390f81ef4a9SWill Deacon 391f81ef4a9SWill Deacon out: 392f81ef4a9SWill Deacon return ret; 393f81ef4a9SWill Deacon } 394f81ef4a9SWill Deacon 395f81ef4a9SWill Deacon void arch_uninstall_hw_breakpoint(struct perf_event *bp) 396f81ef4a9SWill Deacon { 397f81ef4a9SWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 398f81ef4a9SWill Deacon struct perf_event **slot, **slots; 399f81ef4a9SWill Deacon int i, max_slots, base; 400f81ef4a9SWill Deacon 401f81ef4a9SWill Deacon if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { 402f81ef4a9SWill Deacon /* Breakpoint */ 403f81ef4a9SWill Deacon base = ARM_BASE_BCR; 4044a55c18eSWill Deacon slots = (struct perf_event **)__get_cpu_var(bp_on_reg); 4050017ff42SWill Deacon max_slots = core_num_brps; 406f81ef4a9SWill Deacon } else { 407f81ef4a9SWill Deacon /* Watchpoint */ 40893a04a34SWill Deacon if (info->step_ctrl.enabled) 40993a04a34SWill Deacon base = ARM_BASE_BCR + core_num_brps; 41093a04a34SWill Deacon else 411f81ef4a9SWill Deacon base = ARM_BASE_WCR; 4124a55c18eSWill Deacon slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 413f81ef4a9SWill Deacon max_slots = core_num_wrps; 414f81ef4a9SWill Deacon } 415f81ef4a9SWill Deacon 416f81ef4a9SWill Deacon /* Remove the breakpoint. */ 417f81ef4a9SWill Deacon for (i = 0; i < max_slots; ++i) { 418f81ef4a9SWill Deacon slot = &slots[i]; 419f81ef4a9SWill Deacon 420f81ef4a9SWill Deacon if (*slot == bp) { 421f81ef4a9SWill Deacon *slot = NULL; 422f81ef4a9SWill Deacon break; 423f81ef4a9SWill Deacon } 424f81ef4a9SWill Deacon } 425f81ef4a9SWill Deacon 4267d85d61fSStephen Boyd if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) 427f81ef4a9SWill Deacon return; 428f81ef4a9SWill Deacon 429f81ef4a9SWill Deacon /* Reset the control register. */ 430f81ef4a9SWill Deacon write_wb_reg(base + i, 0); 431f81ef4a9SWill Deacon } 432f81ef4a9SWill Deacon 433f81ef4a9SWill Deacon static int get_hbp_len(u8 hbp_len) 434f81ef4a9SWill Deacon { 435f81ef4a9SWill Deacon unsigned int len_in_bytes = 0; 436f81ef4a9SWill Deacon 437f81ef4a9SWill Deacon switch (hbp_len) { 438f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_1: 439f81ef4a9SWill Deacon len_in_bytes = 1; 440f81ef4a9SWill Deacon break; 441f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_2: 442f81ef4a9SWill Deacon len_in_bytes = 2; 443f81ef4a9SWill Deacon break; 444f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_4: 445f81ef4a9SWill Deacon len_in_bytes = 4; 446f81ef4a9SWill Deacon break; 447f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_8: 448f81ef4a9SWill Deacon len_in_bytes = 8; 449f81ef4a9SWill Deacon break; 450f81ef4a9SWill Deacon } 451f81ef4a9SWill Deacon 452f81ef4a9SWill Deacon return len_in_bytes; 453f81ef4a9SWill Deacon } 454f81ef4a9SWill Deacon 455f81ef4a9SWill Deacon /* 456f81ef4a9SWill Deacon * Check whether bp virtual address is in kernel space. 457f81ef4a9SWill Deacon */ 458f81ef4a9SWill Deacon int arch_check_bp_in_kernelspace(struct perf_event *bp) 459f81ef4a9SWill Deacon { 460f81ef4a9SWill Deacon unsigned int len; 461f81ef4a9SWill Deacon unsigned long va; 462f81ef4a9SWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 463f81ef4a9SWill Deacon 464f81ef4a9SWill Deacon va = info->address; 465f81ef4a9SWill Deacon len = get_hbp_len(info->ctrl.len); 466f81ef4a9SWill Deacon 467f81ef4a9SWill Deacon return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); 468f81ef4a9SWill Deacon } 469f81ef4a9SWill Deacon 470f81ef4a9SWill Deacon /* 471f81ef4a9SWill Deacon * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. 472f81ef4a9SWill Deacon * Hopefully this will disappear when ptrace can bypass the conversion 473f81ef4a9SWill Deacon * to generic breakpoint descriptions. 474f81ef4a9SWill Deacon */ 475f81ef4a9SWill Deacon int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, 476f81ef4a9SWill Deacon int *gen_len, int *gen_type) 477f81ef4a9SWill Deacon { 478f81ef4a9SWill Deacon /* Type */ 479f81ef4a9SWill Deacon switch (ctrl.type) { 480f81ef4a9SWill Deacon case ARM_BREAKPOINT_EXECUTE: 481f81ef4a9SWill Deacon *gen_type = HW_BREAKPOINT_X; 482f81ef4a9SWill Deacon break; 483f81ef4a9SWill Deacon case ARM_BREAKPOINT_LOAD: 484f81ef4a9SWill Deacon *gen_type = HW_BREAKPOINT_R; 485f81ef4a9SWill Deacon break; 486f81ef4a9SWill Deacon case ARM_BREAKPOINT_STORE: 487f81ef4a9SWill Deacon *gen_type = HW_BREAKPOINT_W; 488f81ef4a9SWill Deacon break; 489f81ef4a9SWill Deacon case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: 490f81ef4a9SWill Deacon *gen_type = HW_BREAKPOINT_RW; 491f81ef4a9SWill Deacon break; 492f81ef4a9SWill Deacon default: 493f81ef4a9SWill Deacon return -EINVAL; 494f81ef4a9SWill Deacon } 495f81ef4a9SWill Deacon 496f81ef4a9SWill Deacon /* Len */ 497f81ef4a9SWill Deacon switch (ctrl.len) { 498f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_1: 499f81ef4a9SWill Deacon *gen_len = HW_BREAKPOINT_LEN_1; 500f81ef4a9SWill Deacon break; 501f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_2: 502f81ef4a9SWill Deacon *gen_len = HW_BREAKPOINT_LEN_2; 503f81ef4a9SWill Deacon break; 504f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_4: 505f81ef4a9SWill Deacon *gen_len = HW_BREAKPOINT_LEN_4; 506f81ef4a9SWill Deacon break; 507f81ef4a9SWill Deacon case ARM_BREAKPOINT_LEN_8: 508f81ef4a9SWill Deacon *gen_len = HW_BREAKPOINT_LEN_8; 509f81ef4a9SWill Deacon break; 510f81ef4a9SWill Deacon default: 511f81ef4a9SWill Deacon return -EINVAL; 512f81ef4a9SWill Deacon } 513f81ef4a9SWill Deacon 514f81ef4a9SWill Deacon return 0; 515f81ef4a9SWill Deacon } 516f81ef4a9SWill Deacon 517f81ef4a9SWill Deacon /* 518f81ef4a9SWill Deacon * Construct an arch_hw_breakpoint from a perf_event. 519f81ef4a9SWill Deacon */ 520f81ef4a9SWill Deacon static int arch_build_bp_info(struct perf_event *bp) 521f81ef4a9SWill Deacon { 522f81ef4a9SWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 523f81ef4a9SWill Deacon 524f81ef4a9SWill Deacon /* Type */ 525f81ef4a9SWill Deacon switch (bp->attr.bp_type) { 526f81ef4a9SWill Deacon case HW_BREAKPOINT_X: 527f81ef4a9SWill Deacon info->ctrl.type = ARM_BREAKPOINT_EXECUTE; 528f81ef4a9SWill Deacon break; 529f81ef4a9SWill Deacon case HW_BREAKPOINT_R: 530f81ef4a9SWill Deacon info->ctrl.type = ARM_BREAKPOINT_LOAD; 531f81ef4a9SWill Deacon break; 532f81ef4a9SWill Deacon case HW_BREAKPOINT_W: 533f81ef4a9SWill Deacon info->ctrl.type = ARM_BREAKPOINT_STORE; 534f81ef4a9SWill Deacon break; 535f81ef4a9SWill Deacon case HW_BREAKPOINT_RW: 536f81ef4a9SWill Deacon info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; 537f81ef4a9SWill Deacon break; 538f81ef4a9SWill Deacon default: 539f81ef4a9SWill Deacon return -EINVAL; 540f81ef4a9SWill Deacon } 541f81ef4a9SWill Deacon 542f81ef4a9SWill Deacon /* Len */ 543f81ef4a9SWill Deacon switch (bp->attr.bp_len) { 544f81ef4a9SWill Deacon case HW_BREAKPOINT_LEN_1: 545f81ef4a9SWill Deacon info->ctrl.len = ARM_BREAKPOINT_LEN_1; 546f81ef4a9SWill Deacon break; 547f81ef4a9SWill Deacon case HW_BREAKPOINT_LEN_2: 548f81ef4a9SWill Deacon info->ctrl.len = ARM_BREAKPOINT_LEN_2; 549f81ef4a9SWill Deacon break; 550f81ef4a9SWill Deacon case HW_BREAKPOINT_LEN_4: 551f81ef4a9SWill Deacon info->ctrl.len = ARM_BREAKPOINT_LEN_4; 552f81ef4a9SWill Deacon break; 553f81ef4a9SWill Deacon case HW_BREAKPOINT_LEN_8: 554f81ef4a9SWill Deacon info->ctrl.len = ARM_BREAKPOINT_LEN_8; 555f81ef4a9SWill Deacon if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE) 556f81ef4a9SWill Deacon && max_watchpoint_len >= 8) 557f81ef4a9SWill Deacon break; 558f81ef4a9SWill Deacon default: 559f81ef4a9SWill Deacon return -EINVAL; 560f81ef4a9SWill Deacon } 561f81ef4a9SWill Deacon 5626ee33c27SWill Deacon /* 5636ee33c27SWill Deacon * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes. 5646ee33c27SWill Deacon * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported 5656ee33c27SWill Deacon * by the hardware and must be aligned to the appropriate number of 5666ee33c27SWill Deacon * bytes. 5676ee33c27SWill Deacon */ 5686ee33c27SWill Deacon if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && 5696ee33c27SWill Deacon info->ctrl.len != ARM_BREAKPOINT_LEN_2 && 5706ee33c27SWill Deacon info->ctrl.len != ARM_BREAKPOINT_LEN_4) 5716ee33c27SWill Deacon return -EINVAL; 5726ee33c27SWill Deacon 573f81ef4a9SWill Deacon /* Address */ 574f81ef4a9SWill Deacon info->address = bp->attr.bp_addr; 575f81ef4a9SWill Deacon 576f81ef4a9SWill Deacon /* Privilege */ 577f81ef4a9SWill Deacon info->ctrl.privilege = ARM_BREAKPOINT_USER; 57893a04a34SWill Deacon if (arch_check_bp_in_kernelspace(bp)) 579f81ef4a9SWill Deacon info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; 580f81ef4a9SWill Deacon 581f81ef4a9SWill Deacon /* Enabled? */ 582f81ef4a9SWill Deacon info->ctrl.enabled = !bp->attr.disabled; 583f81ef4a9SWill Deacon 584f81ef4a9SWill Deacon /* Mismatch */ 585f81ef4a9SWill Deacon info->ctrl.mismatch = 0; 586f81ef4a9SWill Deacon 587f81ef4a9SWill Deacon return 0; 588f81ef4a9SWill Deacon } 589f81ef4a9SWill Deacon 590f81ef4a9SWill Deacon /* 591f81ef4a9SWill Deacon * Validate the arch-specific HW Breakpoint register settings. 592f81ef4a9SWill Deacon */ 593f81ef4a9SWill Deacon int arch_validate_hwbkpt_settings(struct perf_event *bp) 594f81ef4a9SWill Deacon { 595f81ef4a9SWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 596f81ef4a9SWill Deacon int ret = 0; 5976ee33c27SWill Deacon u32 offset, alignment_mask = 0x3; 598f81ef4a9SWill Deacon 599f81ef4a9SWill Deacon /* Build the arch_hw_breakpoint. */ 600f81ef4a9SWill Deacon ret = arch_build_bp_info(bp); 601f81ef4a9SWill Deacon if (ret) 602f81ef4a9SWill Deacon goto out; 603f81ef4a9SWill Deacon 604f81ef4a9SWill Deacon /* Check address alignment. */ 605f81ef4a9SWill Deacon if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) 606f81ef4a9SWill Deacon alignment_mask = 0x7; 6076ee33c27SWill Deacon offset = info->address & alignment_mask; 6086ee33c27SWill Deacon switch (offset) { 6096ee33c27SWill Deacon case 0: 6106ee33c27SWill Deacon /* Aligned */ 6116ee33c27SWill Deacon break; 6126ee33c27SWill Deacon case 1: 6136ee33c27SWill Deacon /* Allow single byte watchpoint. */ 6146ee33c27SWill Deacon if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) 6156ee33c27SWill Deacon break; 6166ee33c27SWill Deacon case 2: 6176ee33c27SWill Deacon /* Allow halfword watchpoints and breakpoints. */ 6186ee33c27SWill Deacon if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) 6196ee33c27SWill Deacon break; 6206ee33c27SWill Deacon default: 6216ee33c27SWill Deacon ret = -EINVAL; 622f81ef4a9SWill Deacon goto out; 623f81ef4a9SWill Deacon } 624f81ef4a9SWill Deacon 6256ee33c27SWill Deacon info->address &= ~alignment_mask; 626f81ef4a9SWill Deacon info->ctrl.len <<= offset; 627f81ef4a9SWill Deacon 628f81ef4a9SWill Deacon /* 629f81ef4a9SWill Deacon * Currently we rely on an overflow handler to take 630f81ef4a9SWill Deacon * care of single-stepping the breakpoint when it fires. 631f81ef4a9SWill Deacon * In the case of userspace breakpoints on a core with V7 debug, 6323ce70b2eSWill Deacon * we can use the mismatch feature as a poor-man's hardware 6333ce70b2eSWill Deacon * single-step, but this only works for per-task breakpoints. 634f81ef4a9SWill Deacon */ 635f81ef4a9SWill Deacon if (WARN_ONCE(!bp->overflow_handler && 6363ce70b2eSWill Deacon (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps() 6373ce70b2eSWill Deacon || !bp->hw.bp_target), 6387d85d61fSStephen Boyd "overflow handler required but none found\n")) { 639f81ef4a9SWill Deacon ret = -EINVAL; 640f81ef4a9SWill Deacon } 641f81ef4a9SWill Deacon out: 642f81ef4a9SWill Deacon return ret; 643f81ef4a9SWill Deacon } 644f81ef4a9SWill Deacon 6459ebb3cbcSWill Deacon /* 6469ebb3cbcSWill Deacon * Enable/disable single-stepping over the breakpoint bp at address addr. 6479ebb3cbcSWill Deacon */ 6489ebb3cbcSWill Deacon static void enable_single_step(struct perf_event *bp, u32 addr) 649f81ef4a9SWill Deacon { 6509ebb3cbcSWill Deacon struct arch_hw_breakpoint *info = counter_arch_bp(bp); 651f81ef4a9SWill Deacon 6529ebb3cbcSWill Deacon arch_uninstall_hw_breakpoint(bp); 6539ebb3cbcSWill Deacon info->step_ctrl.mismatch = 1; 6549ebb3cbcSWill Deacon info->step_ctrl.len = ARM_BREAKPOINT_LEN_4; 6559ebb3cbcSWill Deacon info->step_ctrl.type = ARM_BREAKPOINT_EXECUTE; 6569ebb3cbcSWill Deacon info->step_ctrl.privilege = info->ctrl.privilege; 6579ebb3cbcSWill Deacon info->step_ctrl.enabled = 1; 6589ebb3cbcSWill Deacon info->trigger = addr; 6599ebb3cbcSWill Deacon arch_install_hw_breakpoint(bp); 660f81ef4a9SWill Deacon } 6619ebb3cbcSWill Deacon 6629ebb3cbcSWill Deacon static void disable_single_step(struct perf_event *bp) 6639ebb3cbcSWill Deacon { 6649ebb3cbcSWill Deacon arch_uninstall_hw_breakpoint(bp); 6659ebb3cbcSWill Deacon counter_arch_bp(bp)->step_ctrl.enabled = 0; 6669ebb3cbcSWill Deacon arch_install_hw_breakpoint(bp); 667f81ef4a9SWill Deacon } 668f81ef4a9SWill Deacon 669f81ef4a9SWill Deacon static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) 670f81ef4a9SWill Deacon { 671f81ef4a9SWill Deacon int i; 6724a55c18eSWill Deacon struct perf_event *wp, **slots; 673f81ef4a9SWill Deacon struct arch_hw_breakpoint *info; 674f81ef4a9SWill Deacon 6754a55c18eSWill Deacon slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 6764a55c18eSWill Deacon 677f81ef4a9SWill Deacon /* Without a disassembler, we can only handle 1 watchpoint. */ 678f81ef4a9SWill Deacon BUG_ON(core_num_wrps > 1); 679f81ef4a9SWill Deacon 680f81ef4a9SWill Deacon for (i = 0; i < core_num_wrps; ++i) { 681f81ef4a9SWill Deacon rcu_read_lock(); 682f81ef4a9SWill Deacon 68393a04a34SWill Deacon wp = slots[i]; 68493a04a34SWill Deacon 68593a04a34SWill Deacon if (wp == NULL) { 686f81ef4a9SWill Deacon rcu_read_unlock(); 687f81ef4a9SWill Deacon continue; 688f81ef4a9SWill Deacon } 689f81ef4a9SWill Deacon 690f81ef4a9SWill Deacon /* 691f81ef4a9SWill Deacon * The DFAR is an unknown value. Since we only allow a 692f81ef4a9SWill Deacon * single watchpoint, we can set the trigger to the lowest 693f81ef4a9SWill Deacon * possible faulting address. 694f81ef4a9SWill Deacon */ 69593a04a34SWill Deacon info = counter_arch_bp(wp); 69693a04a34SWill Deacon info->trigger = wp->attr.bp_addr; 697f81ef4a9SWill Deacon pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); 69893a04a34SWill Deacon perf_bp_event(wp, regs); 699f81ef4a9SWill Deacon 700f81ef4a9SWill Deacon /* 701f81ef4a9SWill Deacon * If no overflow handler is present, insert a temporary 702f81ef4a9SWill Deacon * mismatch breakpoint so we can single-step over the 703f81ef4a9SWill Deacon * watchpoint trigger. 704f81ef4a9SWill Deacon */ 7059ebb3cbcSWill Deacon if (!wp->overflow_handler) 7069ebb3cbcSWill Deacon enable_single_step(wp, instruction_pointer(regs)); 707f81ef4a9SWill Deacon 708f81ef4a9SWill Deacon rcu_read_unlock(); 709f81ef4a9SWill Deacon } 710f81ef4a9SWill Deacon } 711f81ef4a9SWill Deacon 71293a04a34SWill Deacon static void watchpoint_single_step_handler(unsigned long pc) 71393a04a34SWill Deacon { 71493a04a34SWill Deacon int i; 7154a55c18eSWill Deacon struct perf_event *wp, **slots; 71693a04a34SWill Deacon struct arch_hw_breakpoint *info; 71793a04a34SWill Deacon 7184a55c18eSWill Deacon slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 7194a55c18eSWill Deacon 72093a04a34SWill Deacon for (i = 0; i < core_num_reserved_brps; ++i) { 72193a04a34SWill Deacon rcu_read_lock(); 72293a04a34SWill Deacon 72393a04a34SWill Deacon wp = slots[i]; 72493a04a34SWill Deacon 72593a04a34SWill Deacon if (wp == NULL) 72693a04a34SWill Deacon goto unlock; 72793a04a34SWill Deacon 72893a04a34SWill Deacon info = counter_arch_bp(wp); 72993a04a34SWill Deacon if (!info->step_ctrl.enabled) 73093a04a34SWill Deacon goto unlock; 73193a04a34SWill Deacon 73293a04a34SWill Deacon /* 73393a04a34SWill Deacon * Restore the original watchpoint if we've completed the 73493a04a34SWill Deacon * single-step. 73593a04a34SWill Deacon */ 7369ebb3cbcSWill Deacon if (info->trigger != pc) 7379ebb3cbcSWill Deacon disable_single_step(wp); 73893a04a34SWill Deacon 73993a04a34SWill Deacon unlock: 74093a04a34SWill Deacon rcu_read_unlock(); 74193a04a34SWill Deacon } 74293a04a34SWill Deacon } 74393a04a34SWill Deacon 744f81ef4a9SWill Deacon static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) 745f81ef4a9SWill Deacon { 746f81ef4a9SWill Deacon int i; 747f81ef4a9SWill Deacon u32 ctrl_reg, val, addr; 7484a55c18eSWill Deacon struct perf_event *bp, **slots; 749f81ef4a9SWill Deacon struct arch_hw_breakpoint *info; 750f81ef4a9SWill Deacon struct arch_hw_breakpoint_ctrl ctrl; 751f81ef4a9SWill Deacon 7524a55c18eSWill Deacon slots = (struct perf_event **)__get_cpu_var(bp_on_reg); 7534a55c18eSWill Deacon 754f81ef4a9SWill Deacon /* The exception entry code places the amended lr in the PC. */ 755f81ef4a9SWill Deacon addr = regs->ARM_pc; 756f81ef4a9SWill Deacon 75793a04a34SWill Deacon /* Check the currently installed breakpoints first. */ 75893a04a34SWill Deacon for (i = 0; i < core_num_brps; ++i) { 759f81ef4a9SWill Deacon rcu_read_lock(); 760f81ef4a9SWill Deacon 761f81ef4a9SWill Deacon bp = slots[i]; 762f81ef4a9SWill Deacon 7639ebb3cbcSWill Deacon if (bp == NULL) 7649ebb3cbcSWill Deacon goto unlock; 765f81ef4a9SWill Deacon 7669ebb3cbcSWill Deacon info = counter_arch_bp(bp); 767f81ef4a9SWill Deacon 768f81ef4a9SWill Deacon /* Check if the breakpoint value matches. */ 769f81ef4a9SWill Deacon val = read_wb_reg(ARM_BASE_BVR + i); 770f81ef4a9SWill Deacon if (val != (addr & ~0x3)) 7719ebb3cbcSWill Deacon goto mismatch; 772f81ef4a9SWill Deacon 773f81ef4a9SWill Deacon /* Possible match, check the byte address select to confirm. */ 774f81ef4a9SWill Deacon ctrl_reg = read_wb_reg(ARM_BASE_BCR + i); 775f81ef4a9SWill Deacon decode_ctrl_reg(ctrl_reg, &ctrl); 776f81ef4a9SWill Deacon if ((1 << (addr & 0x3)) & ctrl.len) { 777f81ef4a9SWill Deacon info->trigger = addr; 778f81ef4a9SWill Deacon pr_debug("breakpoint fired: address = 0x%x\n", addr); 779f81ef4a9SWill Deacon perf_bp_event(bp, regs); 7809ebb3cbcSWill Deacon if (!bp->overflow_handler) 7819ebb3cbcSWill Deacon enable_single_step(bp, addr); 7829ebb3cbcSWill Deacon goto unlock; 783f81ef4a9SWill Deacon } 784f81ef4a9SWill Deacon 7859ebb3cbcSWill Deacon mismatch: 7869ebb3cbcSWill Deacon /* If we're stepping a breakpoint, it can now be restored. */ 7879ebb3cbcSWill Deacon if (info->step_ctrl.enabled) 7889ebb3cbcSWill Deacon disable_single_step(bp); 7899ebb3cbcSWill Deacon unlock: 790f81ef4a9SWill Deacon rcu_read_unlock(); 791f81ef4a9SWill Deacon } 79293a04a34SWill Deacon 79393a04a34SWill Deacon /* Handle any pending watchpoint single-step breakpoints. */ 79493a04a34SWill Deacon watchpoint_single_step_handler(addr); 795f81ef4a9SWill Deacon } 796f81ef4a9SWill Deacon 797f81ef4a9SWill Deacon /* 798f81ef4a9SWill Deacon * Called from either the Data Abort Handler [watchpoint] or the 799*02fe2845SRussell King * Prefetch Abort Handler [breakpoint] with interrupts disabled. 800f81ef4a9SWill Deacon */ 801f81ef4a9SWill Deacon static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr, 802f81ef4a9SWill Deacon struct pt_regs *regs) 803f81ef4a9SWill Deacon { 8047e202696SWill Deacon int ret = 0; 805f81ef4a9SWill Deacon u32 dscr; 806f81ef4a9SWill Deacon 807*02fe2845SRussell King preempt_disable(); 808*02fe2845SRussell King 809*02fe2845SRussell King if (interrupts_enabled(regs)) 810*02fe2845SRussell King local_irq_enable(); 8117e202696SWill Deacon 812f81ef4a9SWill Deacon /* We only handle watchpoints and hardware breakpoints. */ 813f81ef4a9SWill Deacon ARM_DBG_READ(c1, 0, dscr); 814f81ef4a9SWill Deacon 815f81ef4a9SWill Deacon /* Perform perf callbacks. */ 816f81ef4a9SWill Deacon switch (ARM_DSCR_MOE(dscr)) { 817f81ef4a9SWill Deacon case ARM_ENTRY_BREAKPOINT: 818f81ef4a9SWill Deacon breakpoint_handler(addr, regs); 819f81ef4a9SWill Deacon break; 820f81ef4a9SWill Deacon case ARM_ENTRY_ASYNC_WATCHPOINT: 821235584b6SJoe Perches WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); 822f81ef4a9SWill Deacon case ARM_ENTRY_SYNC_WATCHPOINT: 823f81ef4a9SWill Deacon watchpoint_handler(addr, regs); 824f81ef4a9SWill Deacon break; 825f81ef4a9SWill Deacon default: 8267e202696SWill Deacon ret = 1; /* Unhandled fault. */ 827f81ef4a9SWill Deacon } 828f81ef4a9SWill Deacon 8297e202696SWill Deacon preempt_enable(); 8307e202696SWill Deacon 831f81ef4a9SWill Deacon return ret; 832f81ef4a9SWill Deacon } 833f81ef4a9SWill Deacon 834f81ef4a9SWill Deacon /* 835f81ef4a9SWill Deacon * One-time initialisation. 836f81ef4a9SWill Deacon */ 837c09bae70SWill Deacon static void reset_ctrl_regs(void *info) 838f81ef4a9SWill Deacon { 839c09bae70SWill Deacon int i, cpu = smp_processor_id(); 840c09bae70SWill Deacon u32 dbg_power; 841c09bae70SWill Deacon cpumask_t *cpumask = info; 842f81ef4a9SWill Deacon 843ac88e071SWill Deacon /* 844ac88e071SWill Deacon * v7 debug contains save and restore registers so that debug state 845ed19b739SWill Deacon * can be maintained across low-power modes without leaving the debug 846ed19b739SWill Deacon * logic powered up. It is IMPLEMENTATION DEFINED whether we can access 847ed19b739SWill Deacon * the debug registers out of reset, so we must unlock the OS Lock 848ed19b739SWill Deacon * Access Register to avoid taking undefined instruction exceptions 849ed19b739SWill Deacon * later on. 850ac88e071SWill Deacon */ 851ac88e071SWill Deacon if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) { 852ac88e071SWill Deacon /* 853c09bae70SWill Deacon * Ensure sticky power-down is clear (i.e. debug logic is 854c09bae70SWill Deacon * powered up). 855c09bae70SWill Deacon */ 856c09bae70SWill Deacon asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power)); 857c09bae70SWill Deacon if ((dbg_power & 0x1) == 0) { 858c09bae70SWill Deacon pr_warning("CPU %d debug is powered down!\n", cpu); 859c09bae70SWill Deacon cpumask_or(cpumask, cpumask, cpumask_of(cpu)); 860c09bae70SWill Deacon return; 861c09bae70SWill Deacon } 862c09bae70SWill Deacon 863c09bae70SWill Deacon /* 864ac88e071SWill Deacon * Unconditionally clear the lock by writing a value 865ac88e071SWill Deacon * other than 0xC5ACCE55 to the access register. 866ac88e071SWill Deacon */ 867ac88e071SWill Deacon asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); 868ac88e071SWill Deacon isb(); 869e89c0d70SWill Deacon 870e89c0d70SWill Deacon /* 871e89c0d70SWill Deacon * Clear any configured vector-catch events before 872e89c0d70SWill Deacon * enabling monitor mode. 873e89c0d70SWill Deacon */ 874e89c0d70SWill Deacon asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0)); 875e89c0d70SWill Deacon isb(); 876ac88e071SWill Deacon } 877ac88e071SWill Deacon 878f81ef4a9SWill Deacon if (enable_monitor_mode()) 879f81ef4a9SWill Deacon return; 880f81ef4a9SWill Deacon 8810017ff42SWill Deacon /* We must also reset any reserved registers. */ 8820017ff42SWill Deacon for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) { 883f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_BCR + i, 0UL); 884f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_BVR + i, 0UL); 885f81ef4a9SWill Deacon } 886f81ef4a9SWill Deacon 887f81ef4a9SWill Deacon for (i = 0; i < core_num_wrps; ++i) { 888f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_WCR + i, 0UL); 889f81ef4a9SWill Deacon write_wb_reg(ARM_BASE_WVR + i, 0UL); 890f81ef4a9SWill Deacon } 891f81ef4a9SWill Deacon } 892f81ef4a9SWill Deacon 8937d99331eSWill Deacon static int __cpuinit dbg_reset_notify(struct notifier_block *self, 8947d99331eSWill Deacon unsigned long action, void *cpu) 8957d99331eSWill Deacon { 8967d99331eSWill Deacon if (action == CPU_ONLINE) 8977d99331eSWill Deacon smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); 8987d99331eSWill Deacon return NOTIFY_OK; 8997d99331eSWill Deacon } 9007d99331eSWill Deacon 9017d99331eSWill Deacon static struct notifier_block __cpuinitdata dbg_reset_nb = { 9027d99331eSWill Deacon .notifier_call = dbg_reset_notify, 9037d99331eSWill Deacon }; 9047d99331eSWill Deacon 905f81ef4a9SWill Deacon static int __init arch_hw_breakpoint_init(void) 906f81ef4a9SWill Deacon { 907f81ef4a9SWill Deacon u32 dscr; 908c09bae70SWill Deacon cpumask_t cpumask = { CPU_BITS_NONE }; 909f81ef4a9SWill Deacon 910f81ef4a9SWill Deacon debug_arch = get_debug_arch(); 911f81ef4a9SWill Deacon 91266e1cfe6SWill Deacon if (!debug_arch_supported()) { 913f81ef4a9SWill Deacon pr_info("debug architecture 0x%x unsupported.\n", debug_arch); 9148fbf397cSWill Deacon return 0; 915f81ef4a9SWill Deacon } 916f81ef4a9SWill Deacon 917f81ef4a9SWill Deacon /* Determine how many BRPs/WRPs are available. */ 918f81ef4a9SWill Deacon core_num_brps = get_num_brps(); 9190017ff42SWill Deacon core_num_reserved_brps = get_num_reserved_brps(); 920f81ef4a9SWill Deacon core_num_wrps = get_num_wrps(); 921f81ef4a9SWill Deacon 922f81ef4a9SWill Deacon pr_info("found %d breakpoint and %d watchpoint registers.\n", 9230017ff42SWill Deacon core_num_brps + core_num_reserved_brps, core_num_wrps); 924f81ef4a9SWill Deacon 9250017ff42SWill Deacon if (core_num_reserved_brps) 9260017ff42SWill Deacon pr_info("%d breakpoint(s) reserved for watchpoint " 9270017ff42SWill Deacon "single-step.\n", core_num_reserved_brps); 928f81ef4a9SWill Deacon 929f81ef4a9SWill Deacon /* 930f81ef4a9SWill Deacon * Reset the breakpoint resources. We assume that a halting 931f81ef4a9SWill Deacon * debugger will leave the world in a nice state for us. 932f81ef4a9SWill Deacon */ 933c09bae70SWill Deacon on_each_cpu(reset_ctrl_regs, &cpumask, 1); 934c09bae70SWill Deacon if (!cpumask_empty(&cpumask)) { 935c09bae70SWill Deacon core_num_brps = 0; 936c09bae70SWill Deacon core_num_reserved_brps = 0; 937c09bae70SWill Deacon core_num_wrps = 0; 938c09bae70SWill Deacon return 0; 939c09bae70SWill Deacon } 940ac88e071SWill Deacon 941ed19b739SWill Deacon ARM_DBG_READ(c1, 0, dscr); 942ed19b739SWill Deacon if (dscr & ARM_DSCR_HDBGEN) { 943ed19b739SWill Deacon max_watchpoint_len = 4; 9447d85d61fSStephen Boyd pr_warning("halting debug mode enabled. Assuming maximum watchpoint size of %u bytes.\n", 9457d85d61fSStephen Boyd max_watchpoint_len); 946ed19b739SWill Deacon } else { 947ac88e071SWill Deacon /* Work out the maximum supported watchpoint length. */ 948ac88e071SWill Deacon max_watchpoint_len = get_max_wp_len(); 949ac88e071SWill Deacon pr_info("maximum watchpoint size is %u bytes.\n", 950ac88e071SWill Deacon max_watchpoint_len); 951f81ef4a9SWill Deacon } 952f81ef4a9SWill Deacon 953f81ef4a9SWill Deacon /* Register debug fault handler. */ 954f81ef4a9SWill Deacon hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, 955f81ef4a9SWill Deacon "watchpoint debug exception"); 956f81ef4a9SWill Deacon hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT, 957f81ef4a9SWill Deacon "breakpoint debug exception"); 958f81ef4a9SWill Deacon 9597d99331eSWill Deacon /* Register hotplug notifier. */ 9607d99331eSWill Deacon register_cpu_notifier(&dbg_reset_nb); 9618fbf397cSWill Deacon return 0; 962f81ef4a9SWill Deacon } 963f81ef4a9SWill Deacon arch_initcall(arch_hw_breakpoint_init); 964f81ef4a9SWill Deacon 965f81ef4a9SWill Deacon void hw_breakpoint_pmu_read(struct perf_event *bp) 966f81ef4a9SWill Deacon { 967f81ef4a9SWill Deacon } 968f81ef4a9SWill Deacon 969f81ef4a9SWill Deacon /* 970f81ef4a9SWill Deacon * Dummy function to register with die_notifier. 971f81ef4a9SWill Deacon */ 972f81ef4a9SWill Deacon int hw_breakpoint_exceptions_notify(struct notifier_block *unused, 973f81ef4a9SWill Deacon unsigned long val, void *data) 974f81ef4a9SWill Deacon { 975f81ef4a9SWill Deacon return NOTIFY_DONE; 976f81ef4a9SWill Deacon } 977