1/* 2 * linux/arch/arm/kernel/entry-armv.S 3 * 4 * Copyright (C) 1996,1997,1998 Russell King. 5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Low-level vector interface routines 13 * 14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes 15 * it to save wrong values... Be aware! 16 */ 17 18#include <asm/memory.h> 19#include <asm/glue.h> 20#include <asm/vfpmacros.h> 21#include <asm/arch/entry-macro.S> 22#include <asm/thread_notify.h> 23 24#include "entry-header.S" 25 26/* 27 * Interrupt handling. Preserves r7, r8, r9 28 */ 29 .macro irq_handler 30 get_irqnr_preamble r5, lr 311: get_irqnr_and_base r0, r6, r5, lr 32 movne r1, sp 33 @ 34 @ routine called with r0 = irq number, r1 = struct pt_regs * 35 @ 36 adrne lr, 1b 37 bne asm_do_IRQ 38 39#ifdef CONFIG_SMP 40 /* 41 * XXX 42 * 43 * this macro assumes that irqstat (r6) and base (r5) are 44 * preserved from get_irqnr_and_base above 45 */ 46 test_for_ipi r0, r6, r5, lr 47 movne r0, sp 48 adrne lr, 1b 49 bne do_IPI 50 51#ifdef CONFIG_LOCAL_TIMERS 52 test_for_ltirq r0, r6, r5, lr 53 movne r0, sp 54 adrne lr, 1b 55 bne do_local_timer 56#endif 57#endif 58 59 .endm 60 61/* 62 * Invalid mode handlers 63 */ 64 .macro inv_entry, reason 65 sub sp, sp, #S_FRAME_SIZE 66 stmib sp, {r1 - lr} 67 mov r1, #\reason 68 .endm 69 70__pabt_invalid: 71 inv_entry BAD_PREFETCH 72 b common_invalid 73 74__dabt_invalid: 75 inv_entry BAD_DATA 76 b common_invalid 77 78__irq_invalid: 79 inv_entry BAD_IRQ 80 b common_invalid 81 82__und_invalid: 83 inv_entry BAD_UNDEFINSTR 84 85 @ 86 @ XXX fall through to common_invalid 87 @ 88 89@ 90@ common_invalid - generic code for failed exception (re-entrant version of handlers) 91@ 92common_invalid: 93 zero_fp 94 95 ldmia r0, {r4 - r6} 96 add r0, sp, #S_PC @ here for interlock avoidance 97 mov r7, #-1 @ "" "" "" "" 98 str r4, [sp] @ save preserved r0 99 stmia r0, {r5 - r7} @ lr_<exception>, 100 @ cpsr_<exception>, "old_r0" 101 102 mov r0, sp 103 b bad_mode 104 105/* 106 * SVC mode handlers 107 */ 108 109#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 110#define SPFIX(code...) code 111#else 112#define SPFIX(code...) 113#endif 114 115 .macro svc_entry 116 sub sp, sp, #S_FRAME_SIZE 117 SPFIX( tst sp, #4 ) 118 SPFIX( bicne sp, sp, #4 ) 119 stmib sp, {r1 - r12} 120 121 ldmia r0, {r1 - r3} 122 add r5, sp, #S_SP @ here for interlock avoidance 123 mov r4, #-1 @ "" "" "" "" 124 add r0, sp, #S_FRAME_SIZE @ "" "" "" "" 125 SPFIX( addne r0, r0, #4 ) 126 str r1, [sp] @ save the "real" r0 copied 127 @ from the exception stack 128 129 mov r1, lr 130 131 @ 132 @ We are now ready to fill in the remaining blanks on the stack: 133 @ 134 @ r0 - sp_svc 135 @ r1 - lr_svc 136 @ r2 - lr_<exception>, already fixed up for correct return/restart 137 @ r3 - spsr_<exception> 138 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 139 @ 140 stmia r5, {r0 - r4} 141 .endm 142 143 .align 5 144__dabt_svc: 145 svc_entry 146 147 @ 148 @ get ready to re-enable interrupts if appropriate 149 @ 150 mrs r9, cpsr 151 tst r3, #PSR_I_BIT 152 biceq r9, r9, #PSR_I_BIT 153 154 @ 155 @ Call the processor-specific abort handler: 156 @ 157 @ r2 - aborted context pc 158 @ r3 - aborted context cpsr 159 @ 160 @ The abort handler must return the aborted address in r0, and 161 @ the fault status register in r1. r9 must be preserved. 162 @ 163#ifdef MULTI_ABORT 164 ldr r4, .LCprocfns 165 mov lr, pc 166 ldr pc, [r4] 167#else 168 bl CPU_ABORT_HANDLER 169#endif 170 171 @ 172 @ set desired IRQ state, then call main handler 173 @ 174 msr cpsr_c, r9 175 mov r2, sp 176 bl do_DataAbort 177 178 @ 179 @ IRQs off again before pulling preserved data off the stack 180 @ 181 disable_irq 182 183 @ 184 @ restore SPSR and restart the instruction 185 @ 186 ldr r0, [sp, #S_PSR] 187 msr spsr_cxsf, r0 188 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 189 190 .align 5 191__irq_svc: 192 svc_entry 193 194#ifdef CONFIG_TRACE_IRQFLAGS 195 bl trace_hardirqs_off 196#endif 197#ifdef CONFIG_PREEMPT 198 get_thread_info tsk 199 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 200 add r7, r8, #1 @ increment it 201 str r7, [tsk, #TI_PREEMPT] 202#endif 203 204 irq_handler 205#ifdef CONFIG_PREEMPT 206 ldr r0, [tsk, #TI_FLAGS] @ get flags 207 tst r0, #_TIF_NEED_RESCHED 208 blne svc_preempt 209preempt_return: 210 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value 211 str r8, [tsk, #TI_PREEMPT] @ restore preempt count 212 teq r0, r7 213 strne r0, [r0, -r0] @ bug() 214#endif 215 ldr r0, [sp, #S_PSR] @ irqs are already disabled 216 msr spsr_cxsf, r0 217#ifdef CONFIG_TRACE_IRQFLAGS 218 tst r0, #PSR_I_BIT 219 bleq trace_hardirqs_on 220#endif 221 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 222 223 .ltorg 224 225#ifdef CONFIG_PREEMPT 226svc_preempt: 227 teq r8, #0 @ was preempt count = 0 228 ldreq r6, .LCirq_stat 229 movne pc, lr @ no 230 ldr r0, [r6, #4] @ local_irq_count 231 ldr r1, [r6, #8] @ local_bh_count 232 adds r0, r0, r1 233 movne pc, lr 234 mov r7, #0 @ preempt_schedule_irq 235 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0 2361: bl preempt_schedule_irq @ irq en/disable is done inside 237 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 238 tst r0, #_TIF_NEED_RESCHED 239 beq preempt_return @ go again 240 b 1b 241#endif 242 243 .align 5 244__und_svc: 245 svc_entry 246 247 @ 248 @ call emulation code, which returns using r9 if it has emulated 249 @ the instruction, or the more conventional lr if we are to treat 250 @ this as a real undefined instruction 251 @ 252 @ r0 - instruction 253 @ 254 ldr r0, [r2, #-4] 255 adr r9, 1f 256 bl call_fpe 257 258 mov r0, sp @ struct pt_regs *regs 259 bl do_undefinstr 260 261 @ 262 @ IRQs off again before pulling preserved data off the stack 263 @ 2641: disable_irq 265 266 @ 267 @ restore SPSR and restart the instruction 268 @ 269 ldr lr, [sp, #S_PSR] @ Get SVC cpsr 270 msr spsr_cxsf, lr 271 ldmia sp, {r0 - pc}^ @ Restore SVC registers 272 273 .align 5 274__pabt_svc: 275 svc_entry 276 277 @ 278 @ re-enable interrupts if appropriate 279 @ 280 mrs r9, cpsr 281 tst r3, #PSR_I_BIT 282 biceq r9, r9, #PSR_I_BIT 283 msr cpsr_c, r9 284 285 @ 286 @ set args, then call main handler 287 @ 288 @ r0 - address of faulting instruction 289 @ r1 - pointer to registers on stack 290 @ 291 mov r0, r2 @ address (pc) 292 mov r1, sp @ regs 293 bl do_PrefetchAbort @ call abort handler 294 295 @ 296 @ IRQs off again before pulling preserved data off the stack 297 @ 298 disable_irq 299 300 @ 301 @ restore SPSR and restart the instruction 302 @ 303 ldr r0, [sp, #S_PSR] 304 msr spsr_cxsf, r0 305 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 306 307 .align 5 308.LCcralign: 309 .word cr_alignment 310#ifdef MULTI_ABORT 311.LCprocfns: 312 .word processor 313#endif 314.LCfp: 315 .word fp_enter 316#ifdef CONFIG_PREEMPT 317.LCirq_stat: 318 .word irq_stat 319#endif 320 321/* 322 * User mode handlers 323 * 324 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 325 */ 326 327#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 328#error "sizeof(struct pt_regs) must be a multiple of 8" 329#endif 330 331 .macro usr_entry 332 sub sp, sp, #S_FRAME_SIZE 333 stmib sp, {r1 - r12} 334 335 ldmia r0, {r1 - r3} 336 add r0, sp, #S_PC @ here for interlock avoidance 337 mov r4, #-1 @ "" "" "" "" 338 339 str r1, [sp] @ save the "real" r0 copied 340 @ from the exception stack 341 342#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 343#ifndef CONFIG_MMU 344#warning "NPTL on non MMU needs fixing" 345#else 346 @ make sure our user space atomic helper is aborted 347 cmp r2, #TASK_SIZE 348 bichs r3, r3, #PSR_Z_BIT 349#endif 350#endif 351 352 @ 353 @ We are now ready to fill in the remaining blanks on the stack: 354 @ 355 @ r2 - lr_<exception>, already fixed up for correct return/restart 356 @ r3 - spsr_<exception> 357 @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 358 @ 359 @ Also, separately save sp_usr and lr_usr 360 @ 361 stmia r0, {r2 - r4} 362 stmdb r0, {sp, lr}^ 363 364 @ 365 @ Enable the alignment trap while in kernel mode 366 @ 367 alignment_trap r0 368 369 @ 370 @ Clear FP to mark the first stack frame 371 @ 372 zero_fp 373 .endm 374 375 .align 5 376__dabt_usr: 377 usr_entry 378 379 @ 380 @ Call the processor-specific abort handler: 381 @ 382 @ r2 - aborted context pc 383 @ r3 - aborted context cpsr 384 @ 385 @ The abort handler must return the aborted address in r0, and 386 @ the fault status register in r1. 387 @ 388#ifdef MULTI_ABORT 389 ldr r4, .LCprocfns 390 mov lr, pc 391 ldr pc, [r4] 392#else 393 bl CPU_ABORT_HANDLER 394#endif 395 396 @ 397 @ IRQs on, then call the main handler 398 @ 399 enable_irq 400 mov r2, sp 401 adr lr, ret_from_exception 402 b do_DataAbort 403 404 .align 5 405__irq_usr: 406 usr_entry 407 408#ifdef CONFIG_TRACE_IRQFLAGS 409 bl trace_hardirqs_off 410#endif 411 get_thread_info tsk 412#ifdef CONFIG_PREEMPT 413 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 414 add r7, r8, #1 @ increment it 415 str r7, [tsk, #TI_PREEMPT] 416#endif 417 418 irq_handler 419#ifdef CONFIG_PREEMPT 420 ldr r0, [tsk, #TI_PREEMPT] 421 str r8, [tsk, #TI_PREEMPT] 422 teq r0, r7 423 strne r0, [r0, -r0] 424#endif 425#ifdef CONFIG_TRACE_IRQFLAGS 426 bl trace_hardirqs_on 427#endif 428 429 mov why, #0 430 b ret_to_user 431 432 .ltorg 433 434 .align 5 435__und_usr: 436 usr_entry 437 438 tst r3, #PSR_T_BIT @ Thumb mode? 439 bne __und_usr_unknown @ ignore FP 440 sub r4, r2, #4 441 442 @ 443 @ fall through to the emulation code, which returns using r9 if 444 @ it has emulated the instruction, or the more conventional lr 445 @ if we are to treat this as a real undefined instruction 446 @ 447 @ r0 - instruction 448 @ 4491: ldrt r0, [r4] 450 adr r9, ret_from_exception 451 adr lr, __und_usr_unknown 452 @ 453 @ fallthrough to call_fpe 454 @ 455 456/* 457 * The out of line fixup for the ldrt above. 458 */ 459 .section .fixup, "ax" 4602: mov pc, r9 461 .previous 462 .section __ex_table,"a" 463 .long 1b, 2b 464 .previous 465 466/* 467 * Check whether the instruction is a co-processor instruction. 468 * If yes, we need to call the relevant co-processor handler. 469 * 470 * Note that we don't do a full check here for the co-processor 471 * instructions; all instructions with bit 27 set are well 472 * defined. The only instructions that should fault are the 473 * co-processor instructions. However, we have to watch out 474 * for the ARM6/ARM7 SWI bug. 475 * 476 * Emulators may wish to make use of the following registers: 477 * r0 = instruction opcode. 478 * r2 = PC+4 479 * r9 = normal "successful" return address 480 * r10 = this threads thread_info structure. 481 * lr = unrecognised instruction return address 482 */ 483call_fpe: 484 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 485#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 486 and r8, r0, #0x0f000000 @ mask out op-code bits 487 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 488#endif 489 moveq pc, lr 490 get_thread_info r10 @ get current thread 491 and r8, r0, #0x00000f00 @ mask out CP number 492 mov r7, #1 493 add r6, r10, #TI_USED_CP 494 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[] 495#ifdef CONFIG_IWMMXT 496 @ Test if we need to give access to iWMMXt coprocessors 497 ldr r5, [r10, #TI_FLAGS] 498 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 499 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 500 bcs iwmmxt_task_enable 501#endif 502 add pc, pc, r8, lsr #6 503 mov r0, r0 504 505 mov pc, lr @ CP#0 506 b do_fpe @ CP#1 (FPE) 507 b do_fpe @ CP#2 (FPE) 508 mov pc, lr @ CP#3 509#ifdef CONFIG_CRUNCH 510 b crunch_task_enable @ CP#4 (MaverickCrunch) 511 b crunch_task_enable @ CP#5 (MaverickCrunch) 512 b crunch_task_enable @ CP#6 (MaverickCrunch) 513#else 514 mov pc, lr @ CP#4 515 mov pc, lr @ CP#5 516 mov pc, lr @ CP#6 517#endif 518 mov pc, lr @ CP#7 519 mov pc, lr @ CP#8 520 mov pc, lr @ CP#9 521#ifdef CONFIG_VFP 522 b do_vfp @ CP#10 (VFP) 523 b do_vfp @ CP#11 (VFP) 524#else 525 mov pc, lr @ CP#10 (VFP) 526 mov pc, lr @ CP#11 (VFP) 527#endif 528 mov pc, lr @ CP#12 529 mov pc, lr @ CP#13 530 mov pc, lr @ CP#14 (Debug) 531 mov pc, lr @ CP#15 (Control) 532 533do_fpe: 534 enable_irq 535 ldr r4, .LCfp 536 add r10, r10, #TI_FPSTATE @ r10 = workspace 537 ldr pc, [r4] @ Call FP module USR entry point 538 539/* 540 * The FP module is called with these registers set: 541 * r0 = instruction 542 * r2 = PC+4 543 * r9 = normal "successful" return address 544 * r10 = FP workspace 545 * lr = unrecognised FP instruction return address 546 */ 547 548 .data 549ENTRY(fp_enter) 550 .word no_fp 551 .text 552 553no_fp: mov pc, lr 554 555__und_usr_unknown: 556 mov r0, sp 557 adr lr, ret_from_exception 558 b do_undefinstr 559 560 .align 5 561__pabt_usr: 562 usr_entry 563 564 enable_irq @ Enable interrupts 565 mov r0, r2 @ address (pc) 566 mov r1, sp @ regs 567 bl do_PrefetchAbort @ call abort handler 568 /* fall through */ 569/* 570 * This is the return code to user mode for abort handlers 571 */ 572ENTRY(ret_from_exception) 573 get_thread_info tsk 574 mov why, #0 575 b ret_to_user 576 577/* 578 * Register switch for ARMv3 and ARMv4 processors 579 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 580 * previous and next are guaranteed not to be the same. 581 */ 582ENTRY(__switch_to) 583 add ip, r1, #TI_CPU_SAVE 584 ldr r3, [r2, #TI_TP_VALUE] 585 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack 586#ifdef CONFIG_MMU 587 ldr r6, [r2, #TI_CPU_DOMAIN] 588#endif 589#if __LINUX_ARM_ARCH__ >= 6 590#ifdef CONFIG_CPU_32v6K 591 clrex 592#else 593 strex r5, r4, [ip] @ Clear exclusive monitor 594#endif 595#endif 596#if defined(CONFIG_HAS_TLS_REG) 597 mcr p15, 0, r3, c13, c0, 3 @ set TLS register 598#elif !defined(CONFIG_TLS_REG_EMUL) 599 mov r4, #0xffff0fff 600 str r3, [r4, #-15] @ TLS val at 0xffff0ff0 601#endif 602#ifdef CONFIG_MMU 603 mcr p15, 0, r6, c3, c0, 0 @ Set domain register 604#endif 605 mov r5, r0 606 add r4, r2, #TI_CPU_SAVE 607 ldr r0, =thread_notify_head 608 mov r1, #THREAD_NOTIFY_SWITCH 609 bl atomic_notifier_call_chain 610 mov r0, r5 611 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously 612 613 __INIT 614 615/* 616 * User helpers. 617 * 618 * These are segment of kernel provided user code reachable from user space 619 * at a fixed address in kernel memory. This is used to provide user space 620 * with some operations which require kernel help because of unimplemented 621 * native feature and/or instructions in many ARM CPUs. The idea is for 622 * this code to be executed directly in user mode for best efficiency but 623 * which is too intimate with the kernel counter part to be left to user 624 * libraries. In fact this code might even differ from one CPU to another 625 * depending on the available instruction set and restrictions like on 626 * SMP systems. In other words, the kernel reserves the right to change 627 * this code as needed without warning. Only the entry points and their 628 * results are guaranteed to be stable. 629 * 630 * Each segment is 32-byte aligned and will be moved to the top of the high 631 * vector page. New segments (if ever needed) must be added in front of 632 * existing ones. This mechanism should be used only for things that are 633 * really small and justified, and not be abused freely. 634 * 635 * User space is expected to implement those things inline when optimizing 636 * for a processor that has the necessary native support, but only if such 637 * resulting binaries are already to be incompatible with earlier ARM 638 * processors due to the use of unsupported instructions other than what 639 * is provided here. In other words don't make binaries unable to run on 640 * earlier processors just for the sake of not using these kernel helpers 641 * if your compiled code is not going to use the new instructions for other 642 * purpose. 643 */ 644 645 .macro usr_ret, reg 646#ifdef CONFIG_ARM_THUMB 647 bx \reg 648#else 649 mov pc, \reg 650#endif 651 .endm 652 653 .align 5 654 .globl __kuser_helper_start 655__kuser_helper_start: 656 657/* 658 * Reference prototype: 659 * 660 * void __kernel_memory_barrier(void) 661 * 662 * Input: 663 * 664 * lr = return address 665 * 666 * Output: 667 * 668 * none 669 * 670 * Clobbered: 671 * 672 * the Z flag might be lost 673 * 674 * Definition and user space usage example: 675 * 676 * typedef void (__kernel_dmb_t)(void); 677 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 678 * 679 * Apply any needed memory barrier to preserve consistency with data modified 680 * manually and __kuser_cmpxchg usage. 681 * 682 * This could be used as follows: 683 * 684 * #define __kernel_dmb() \ 685 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 686 * : : : "r0", "lr","cc" ) 687 */ 688 689__kuser_memory_barrier: @ 0xffff0fa0 690 691#if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) 692 mcr p15, 0, r0, c7, c10, 5 @ dmb 693#endif 694 usr_ret lr 695 696 .align 5 697 698/* 699 * Reference prototype: 700 * 701 * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 702 * 703 * Input: 704 * 705 * r0 = oldval 706 * r1 = newval 707 * r2 = ptr 708 * lr = return address 709 * 710 * Output: 711 * 712 * r0 = returned value (zero or non-zero) 713 * C flag = set if r0 == 0, clear if r0 != 0 714 * 715 * Clobbered: 716 * 717 * r3, ip, flags 718 * 719 * Definition and user space usage example: 720 * 721 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 722 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 723 * 724 * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 725 * Return zero if *ptr was changed or non-zero if no exchange happened. 726 * The C flag is also set if *ptr was changed to allow for assembly 727 * optimization in the calling code. 728 * 729 * Notes: 730 * 731 * - This routine already includes memory barriers as needed. 732 * 733 * - A failure might be transient, i.e. it is possible, although unlikely, 734 * that "failure" be returned even if *ptr == oldval. 735 * 736 * For example, a user space atomic_add implementation could look like this: 737 * 738 * #define atomic_add(ptr, val) \ 739 * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 740 * register unsigned int __result asm("r1"); \ 741 * asm volatile ( \ 742 * "1: @ atomic_add\n\t" \ 743 * "ldr r0, [r2]\n\t" \ 744 * "mov r3, #0xffff0fff\n\t" \ 745 * "add lr, pc, #4\n\t" \ 746 * "add r1, r0, %2\n\t" \ 747 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 748 * "bcc 1b" \ 749 * : "=&r" (__result) \ 750 * : "r" (__ptr), "rIL" (val) \ 751 * : "r0","r3","ip","lr","cc","memory" ); \ 752 * __result; }) 753 */ 754 755__kuser_cmpxchg: @ 0xffff0fc0 756 757#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 758 759 /* 760 * Poor you. No fast solution possible... 761 * The kernel itself must perform the operation. 762 * A special ghost syscall is used for that (see traps.c). 763 */ 764 stmfd sp!, {r7, lr} 765 mov r7, #0xff00 @ 0xfff0 into r7 for EABI 766 orr r7, r7, #0xf0 767 swi #0x9ffff0 768 ldmfd sp!, {r7, pc} 769 770#elif __LINUX_ARM_ARCH__ < 6 771 772 /* 773 * Theory of operation: 774 * 775 * We set the Z flag before loading oldval. If ever an exception 776 * occurs we can not be sure the loaded value will still be the same 777 * when the exception returns, therefore the user exception handler 778 * will clear the Z flag whenever the interrupted user code was 779 * actually from the kernel address space (see the usr_entry macro). 780 * 781 * The post-increment on the str is used to prevent a race with an 782 * exception happening just after the str instruction which would 783 * clear the Z flag although the exchange was done. 784 */ 785#ifdef CONFIG_MMU 786 teq ip, ip @ set Z flag 787 ldr ip, [r2] @ load current val 788 add r3, r2, #1 @ prepare store ptr 789 teqeq ip, r0 @ compare with oldval if still allowed 790 streq r1, [r3, #-1]! @ store newval if still allowed 791 subs r0, r2, r3 @ if r2 == r3 the str occured 792#else 793#warning "NPTL on non MMU needs fixing" 794 mov r0, #-1 795 adds r0, r0, #0 796#endif 797 usr_ret lr 798 799#else 800 801#ifdef CONFIG_SMP 802 mcr p15, 0, r0, c7, c10, 5 @ dmb 803#endif 804 ldrex r3, [r2] 805 subs r3, r3, r0 806 strexeq r3, r1, [r2] 807 rsbs r0, r3, #0 808#ifdef CONFIG_SMP 809 mcr p15, 0, r0, c7, c10, 5 @ dmb 810#endif 811 usr_ret lr 812 813#endif 814 815 .align 5 816 817/* 818 * Reference prototype: 819 * 820 * int __kernel_get_tls(void) 821 * 822 * Input: 823 * 824 * lr = return address 825 * 826 * Output: 827 * 828 * r0 = TLS value 829 * 830 * Clobbered: 831 * 832 * the Z flag might be lost 833 * 834 * Definition and user space usage example: 835 * 836 * typedef int (__kernel_get_tls_t)(void); 837 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 838 * 839 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 840 * 841 * This could be used as follows: 842 * 843 * #define __kernel_get_tls() \ 844 * ({ register unsigned int __val asm("r0"); \ 845 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 846 * : "=r" (__val) : : "lr","cc" ); \ 847 * __val; }) 848 */ 849 850__kuser_get_tls: @ 0xffff0fe0 851 852#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) 853 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 854#else 855 mrc p15, 0, r0, c13, c0, 3 @ read TLS register 856#endif 857 usr_ret lr 858 859 .rep 5 860 .word 0 @ pad up to __kuser_helper_version 861 .endr 862 863/* 864 * Reference declaration: 865 * 866 * extern unsigned int __kernel_helper_version; 867 * 868 * Definition and user space usage example: 869 * 870 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 871 * 872 * User space may read this to determine the curent number of helpers 873 * available. 874 */ 875 876__kuser_helper_version: @ 0xffff0ffc 877 .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 878 879 .globl __kuser_helper_end 880__kuser_helper_end: 881 882 883/* 884 * Vector stubs. 885 * 886 * This code is copied to 0xffff0200 so we can use branches in the 887 * vectors, rather than ldr's. Note that this code must not 888 * exceed 0x300 bytes. 889 * 890 * Common stub entry macro: 891 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 892 * 893 * SP points to a minimal amount of processor-private memory, the address 894 * of which is copied into r0 for the mode specific abort handler. 895 */ 896 .macro vector_stub, name, mode, correction=0 897 .align 5 898 899vector_\name: 900 .if \correction 901 sub lr, lr, #\correction 902 .endif 903 904 @ 905 @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 906 @ (parent CPSR) 907 @ 908 stmia sp, {r0, lr} @ save r0, lr 909 mrs lr, spsr 910 str lr, [sp, #8] @ save spsr 911 912 @ 913 @ Prepare for SVC32 mode. IRQs remain disabled. 914 @ 915 mrs r0, cpsr 916 eor r0, r0, #(\mode ^ SVC_MODE) 917 msr spsr_cxsf, r0 918 919 @ 920 @ the branch table must immediately follow this code 921 @ 922 and lr, lr, #0x0f 923 mov r0, sp 924 ldr lr, [pc, lr, lsl #2] 925 movs pc, lr @ branch to handler in SVC mode 926 .endm 927 928 .globl __stubs_start 929__stubs_start: 930/* 931 * Interrupt dispatcher 932 */ 933 vector_stub irq, IRQ_MODE, 4 934 935 .long __irq_usr @ 0 (USR_26 / USR_32) 936 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 937 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 938 .long __irq_svc @ 3 (SVC_26 / SVC_32) 939 .long __irq_invalid @ 4 940 .long __irq_invalid @ 5 941 .long __irq_invalid @ 6 942 .long __irq_invalid @ 7 943 .long __irq_invalid @ 8 944 .long __irq_invalid @ 9 945 .long __irq_invalid @ a 946 .long __irq_invalid @ b 947 .long __irq_invalid @ c 948 .long __irq_invalid @ d 949 .long __irq_invalid @ e 950 .long __irq_invalid @ f 951 952/* 953 * Data abort dispatcher 954 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 955 */ 956 vector_stub dabt, ABT_MODE, 8 957 958 .long __dabt_usr @ 0 (USR_26 / USR_32) 959 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 960 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 961 .long __dabt_svc @ 3 (SVC_26 / SVC_32) 962 .long __dabt_invalid @ 4 963 .long __dabt_invalid @ 5 964 .long __dabt_invalid @ 6 965 .long __dabt_invalid @ 7 966 .long __dabt_invalid @ 8 967 .long __dabt_invalid @ 9 968 .long __dabt_invalid @ a 969 .long __dabt_invalid @ b 970 .long __dabt_invalid @ c 971 .long __dabt_invalid @ d 972 .long __dabt_invalid @ e 973 .long __dabt_invalid @ f 974 975/* 976 * Prefetch abort dispatcher 977 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 978 */ 979 vector_stub pabt, ABT_MODE, 4 980 981 .long __pabt_usr @ 0 (USR_26 / USR_32) 982 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 983 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 984 .long __pabt_svc @ 3 (SVC_26 / SVC_32) 985 .long __pabt_invalid @ 4 986 .long __pabt_invalid @ 5 987 .long __pabt_invalid @ 6 988 .long __pabt_invalid @ 7 989 .long __pabt_invalid @ 8 990 .long __pabt_invalid @ 9 991 .long __pabt_invalid @ a 992 .long __pabt_invalid @ b 993 .long __pabt_invalid @ c 994 .long __pabt_invalid @ d 995 .long __pabt_invalid @ e 996 .long __pabt_invalid @ f 997 998/* 999 * Undef instr entry dispatcher 1000 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1001 */ 1002 vector_stub und, UND_MODE 1003 1004 .long __und_usr @ 0 (USR_26 / USR_32) 1005 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 1006 .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 1007 .long __und_svc @ 3 (SVC_26 / SVC_32) 1008 .long __und_invalid @ 4 1009 .long __und_invalid @ 5 1010 .long __und_invalid @ 6 1011 .long __und_invalid @ 7 1012 .long __und_invalid @ 8 1013 .long __und_invalid @ 9 1014 .long __und_invalid @ a 1015 .long __und_invalid @ b 1016 .long __und_invalid @ c 1017 .long __und_invalid @ d 1018 .long __und_invalid @ e 1019 .long __und_invalid @ f 1020 1021 .align 5 1022 1023/*============================================================================= 1024 * Undefined FIQs 1025 *----------------------------------------------------------------------------- 1026 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 1027 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 1028 * Basically to switch modes, we *HAVE* to clobber one register... brain 1029 * damage alert! I don't think that we can execute any code in here in any 1030 * other mode than FIQ... Ok you can switch to another mode, but you can't 1031 * get out of that mode without clobbering one register. 1032 */ 1033vector_fiq: 1034 disable_fiq 1035 subs pc, lr, #4 1036 1037/*============================================================================= 1038 * Address exception handler 1039 *----------------------------------------------------------------------------- 1040 * These aren't too critical. 1041 * (they're not supposed to happen, and won't happen in 32-bit data mode). 1042 */ 1043 1044vector_addrexcptn: 1045 b vector_addrexcptn 1046 1047/* 1048 * We group all the following data together to optimise 1049 * for CPUs with separate I & D caches. 1050 */ 1051 .align 5 1052 1053.LCvswi: 1054 .word vector_swi 1055 1056 .globl __stubs_end 1057__stubs_end: 1058 1059 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 1060 1061 .globl __vectors_start 1062__vectors_start: 1063 swi SYS_ERROR0 1064 b vector_und + stubs_offset 1065 ldr pc, .LCvswi + stubs_offset 1066 b vector_pabt + stubs_offset 1067 b vector_dabt + stubs_offset 1068 b vector_addrexcptn + stubs_offset 1069 b vector_irq + stubs_offset 1070 b vector_fiq + stubs_offset 1071 1072 .globl __vectors_end 1073__vectors_end: 1074 1075 .data 1076 1077 .globl cr_alignment 1078 .globl cr_no_alignment 1079cr_alignment: 1080 .space 4 1081cr_no_alignment: 1082 .space 4 1083