11da177e4SLinus Torvalds/* 21da177e4SLinus Torvalds * linux/arch/arm/kernel/entry-armv.S 31da177e4SLinus Torvalds * 41da177e4SLinus Torvalds * Copyright (C) 1996,1997,1998 Russell King. 51da177e4SLinus Torvalds * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) 6afeb90caSHyok S. Choi * nommu support by Hyok S. Choi (hyok.choi@samsung.com) 71da177e4SLinus Torvalds * 81da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify 91da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as 101da177e4SLinus Torvalds * published by the Free Software Foundation. 111da177e4SLinus Torvalds * 121da177e4SLinus Torvalds * Low-level vector interface routines 131da177e4SLinus Torvalds * 1470b6f2b4SNicolas Pitre * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction 1570b6f2b4SNicolas Pitre * that causes it to save wrong values... Be aware! 161da177e4SLinus Torvalds */ 171da177e4SLinus Torvalds 18f09b9979SNicolas Pitre#include <asm/memory.h> 191da177e4SLinus Torvalds#include <asm/glue.h> 201da177e4SLinus Torvalds#include <asm/vfpmacros.h> 21a09e64fbSRussell King#include <mach/entry-macro.S> 22d6551e88SRussell King#include <asm/thread_notify.h> 23c4c5716eSCatalin Marinas#include <asm/unwind.h> 24*cc20d429SRussell King#include <asm/unistd.h> 251da177e4SLinus Torvalds 261da177e4SLinus Torvalds#include "entry-header.S" 271da177e4SLinus Torvalds 281da177e4SLinus Torvalds/* 29187a51adSRussell King * Interrupt handling. Preserves r7, r8, r9 30187a51adSRussell King */ 31187a51adSRussell King .macro irq_handler 32f80dff9dSDan Williams get_irqnr_preamble r5, lr 33187a51adSRussell King1: get_irqnr_and_base r0, r6, r5, lr 34187a51adSRussell King movne r1, sp 35187a51adSRussell King @ 36187a51adSRussell King @ routine called with r0 = irq number, r1 = struct pt_regs * 37187a51adSRussell King @ 38b86040a5SCatalin Marinas adrne lr, BSYM(1b) 39187a51adSRussell King bne asm_do_IRQ 40791be9b9SRussell King 41791be9b9SRussell King#ifdef CONFIG_SMP 42791be9b9SRussell King /* 43791be9b9SRussell King * XXX 44791be9b9SRussell King * 45791be9b9SRussell King * this macro assumes that irqstat (r6) and base (r5) are 46791be9b9SRussell King * preserved from get_irqnr_and_base above 47791be9b9SRussell King */ 48791be9b9SRussell King test_for_ipi r0, r6, r5, lr 49791be9b9SRussell King movne r0, sp 50b86040a5SCatalin Marinas adrne lr, BSYM(1b) 51791be9b9SRussell King bne do_IPI 5237ee16aeSRussell King 5337ee16aeSRussell King#ifdef CONFIG_LOCAL_TIMERS 5437ee16aeSRussell King test_for_ltirq r0, r6, r5, lr 5537ee16aeSRussell King movne r0, sp 56b86040a5SCatalin Marinas adrne lr, BSYM(1b) 5737ee16aeSRussell King bne do_local_timer 5837ee16aeSRussell King#endif 59791be9b9SRussell King#endif 60791be9b9SRussell King 61187a51adSRussell King .endm 62187a51adSRussell King 63785d3cd2SNicolas Pitre#ifdef CONFIG_KPROBES 64785d3cd2SNicolas Pitre .section .kprobes.text,"ax",%progbits 65785d3cd2SNicolas Pitre#else 66785d3cd2SNicolas Pitre .text 67785d3cd2SNicolas Pitre#endif 68785d3cd2SNicolas Pitre 69187a51adSRussell King/* 701da177e4SLinus Torvalds * Invalid mode handlers 711da177e4SLinus Torvalds */ 72ccea7a19SRussell King .macro inv_entry, reason 73ccea7a19SRussell King sub sp, sp, #S_FRAME_SIZE 74b86040a5SCatalin Marinas ARM( stmib sp, {r1 - lr} ) 75b86040a5SCatalin Marinas THUMB( stmia sp, {r0 - r12} ) 76b86040a5SCatalin Marinas THUMB( str sp, [sp, #S_SP] ) 77b86040a5SCatalin Marinas THUMB( str lr, [sp, #S_LR] ) 781da177e4SLinus Torvalds mov r1, #\reason 791da177e4SLinus Torvalds .endm 801da177e4SLinus Torvalds 811da177e4SLinus Torvalds__pabt_invalid: 82ccea7a19SRussell King inv_entry BAD_PREFETCH 83ccea7a19SRussell King b common_invalid 8493ed3970SCatalin MarinasENDPROC(__pabt_invalid) 851da177e4SLinus Torvalds 861da177e4SLinus Torvalds__dabt_invalid: 87ccea7a19SRussell King inv_entry BAD_DATA 88ccea7a19SRussell King b common_invalid 8993ed3970SCatalin MarinasENDPROC(__dabt_invalid) 901da177e4SLinus Torvalds 911da177e4SLinus Torvalds__irq_invalid: 92ccea7a19SRussell King inv_entry BAD_IRQ 93ccea7a19SRussell King b common_invalid 9493ed3970SCatalin MarinasENDPROC(__irq_invalid) 951da177e4SLinus Torvalds 961da177e4SLinus Torvalds__und_invalid: 97ccea7a19SRussell King inv_entry BAD_UNDEFINSTR 981da177e4SLinus Torvalds 99ccea7a19SRussell King @ 100ccea7a19SRussell King @ XXX fall through to common_invalid 101ccea7a19SRussell King @ 102ccea7a19SRussell King 103ccea7a19SRussell King@ 104ccea7a19SRussell King@ common_invalid - generic code for failed exception (re-entrant version of handlers) 105ccea7a19SRussell King@ 106ccea7a19SRussell Kingcommon_invalid: 107ccea7a19SRussell King zero_fp 108ccea7a19SRussell King 109ccea7a19SRussell King ldmia r0, {r4 - r6} 110ccea7a19SRussell King add r0, sp, #S_PC @ here for interlock avoidance 111ccea7a19SRussell King mov r7, #-1 @ "" "" "" "" 112ccea7a19SRussell King str r4, [sp] @ save preserved r0 113ccea7a19SRussell King stmia r0, {r5 - r7} @ lr_<exception>, 114ccea7a19SRussell King @ cpsr_<exception>, "old_r0" 115ccea7a19SRussell King 1161da177e4SLinus Torvalds mov r0, sp 1171da177e4SLinus Torvalds b bad_mode 11893ed3970SCatalin MarinasENDPROC(__und_invalid) 1191da177e4SLinus Torvalds 1201da177e4SLinus Torvalds/* 1211da177e4SLinus Torvalds * SVC mode handlers 1221da177e4SLinus Torvalds */ 1232dede2d8SNicolas Pitre 1242dede2d8SNicolas Pitre#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 1252dede2d8SNicolas Pitre#define SPFIX(code...) code 1262dede2d8SNicolas Pitre#else 1272dede2d8SNicolas Pitre#define SPFIX(code...) 1282dede2d8SNicolas Pitre#endif 1292dede2d8SNicolas Pitre 130d30a0c8bSNicolas Pitre .macro svc_entry, stack_hole=0 131c4c5716eSCatalin Marinas UNWIND(.fnstart ) 132c4c5716eSCatalin Marinas UNWIND(.save {r0 - pc} ) 133b86040a5SCatalin Marinas sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4) 134b86040a5SCatalin Marinas#ifdef CONFIG_THUMB2_KERNEL 135b86040a5SCatalin Marinas SPFIX( str r0, [sp] ) @ temporarily saved 136b86040a5SCatalin Marinas SPFIX( mov r0, sp ) 137b86040a5SCatalin Marinas SPFIX( tst r0, #4 ) @ test original stack alignment 138b86040a5SCatalin Marinas SPFIX( ldr r0, [sp] ) @ restored 139b86040a5SCatalin Marinas#else 1402dede2d8SNicolas Pitre SPFIX( tst sp, #4 ) 141b86040a5SCatalin Marinas#endif 142b86040a5SCatalin Marinas SPFIX( subeq sp, sp, #4 ) 143b86040a5SCatalin Marinas stmia sp, {r1 - r12} 144ccea7a19SRussell King 145ccea7a19SRussell King ldmia r0, {r1 - r3} 146b86040a5SCatalin Marinas add r5, sp, #S_SP - 4 @ here for interlock avoidance 147ccea7a19SRussell King mov r4, #-1 @ "" "" "" "" 148b86040a5SCatalin Marinas add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4) 149b86040a5SCatalin Marinas SPFIX( addeq r0, r0, #4 ) 150b86040a5SCatalin Marinas str r1, [sp, #-4]! @ save the "real" r0 copied 151ccea7a19SRussell King @ from the exception stack 152ccea7a19SRussell King 1531da177e4SLinus Torvalds mov r1, lr 1541da177e4SLinus Torvalds 1551da177e4SLinus Torvalds @ 1561da177e4SLinus Torvalds @ We are now ready to fill in the remaining blanks on the stack: 1571da177e4SLinus Torvalds @ 1581da177e4SLinus Torvalds @ r0 - sp_svc 1591da177e4SLinus Torvalds @ r1 - lr_svc 1601da177e4SLinus Torvalds @ r2 - lr_<exception>, already fixed up for correct return/restart 1611da177e4SLinus Torvalds @ r3 - spsr_<exception> 1621da177e4SLinus Torvalds @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 1631da177e4SLinus Torvalds @ 1641da177e4SLinus Torvalds stmia r5, {r0 - r4} 1650d928b0bSUwe Kleine-König 1660d928b0bSUwe Kleine-König asm_trace_hardirqs_off 1671da177e4SLinus Torvalds .endm 1681da177e4SLinus Torvalds 1691da177e4SLinus Torvalds .align 5 1701da177e4SLinus Torvalds__dabt_svc: 171ccea7a19SRussell King svc_entry 1721da177e4SLinus Torvalds 1731da177e4SLinus Torvalds @ 1741da177e4SLinus Torvalds @ get ready to re-enable interrupts if appropriate 1751da177e4SLinus Torvalds @ 1761da177e4SLinus Torvalds mrs r9, cpsr 1771da177e4SLinus Torvalds tst r3, #PSR_I_BIT 1781da177e4SLinus Torvalds biceq r9, r9, #PSR_I_BIT 1791da177e4SLinus Torvalds 1801da177e4SLinus Torvalds @ 1811da177e4SLinus Torvalds @ Call the processor-specific abort handler: 1821da177e4SLinus Torvalds @ 1831da177e4SLinus Torvalds @ r2 - aborted context pc 1841da177e4SLinus Torvalds @ r3 - aborted context cpsr 1851da177e4SLinus Torvalds @ 1861da177e4SLinus Torvalds @ The abort handler must return the aborted address in r0, and 1871da177e4SLinus Torvalds @ the fault status register in r1. r9 must be preserved. 1881da177e4SLinus Torvalds @ 18948d7927bSPaul Brook#ifdef MULTI_DABORT 1901da177e4SLinus Torvalds ldr r4, .LCprocfns 1911da177e4SLinus Torvalds mov lr, pc 19248d7927bSPaul Brook ldr pc, [r4, #PROCESSOR_DABT_FUNC] 1931da177e4SLinus Torvalds#else 19448d7927bSPaul Brook bl CPU_DABORT_HANDLER 1951da177e4SLinus Torvalds#endif 1961da177e4SLinus Torvalds 1971da177e4SLinus Torvalds @ 1981da177e4SLinus Torvalds @ set desired IRQ state, then call main handler 1991da177e4SLinus Torvalds @ 2001da177e4SLinus Torvalds msr cpsr_c, r9 2011da177e4SLinus Torvalds mov r2, sp 2021da177e4SLinus Torvalds bl do_DataAbort 2031da177e4SLinus Torvalds 2041da177e4SLinus Torvalds @ 2051da177e4SLinus Torvalds @ IRQs off again before pulling preserved data off the stack 2061da177e4SLinus Torvalds @ 2071ec42c0cSRussell King disable_irq 2081da177e4SLinus Torvalds 2091da177e4SLinus Torvalds @ 2101da177e4SLinus Torvalds @ restore SPSR and restart the instruction 2111da177e4SLinus Torvalds @ 212b86040a5SCatalin Marinas ldr r2, [sp, #S_PSR] 213b86040a5SCatalin Marinas svc_exit r2 @ return from exception 214c4c5716eSCatalin Marinas UNWIND(.fnend ) 21593ed3970SCatalin MarinasENDPROC(__dabt_svc) 2161da177e4SLinus Torvalds 2171da177e4SLinus Torvalds .align 5 2181da177e4SLinus Torvalds__irq_svc: 219ccea7a19SRussell King svc_entry 220ccea7a19SRussell King 2211da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT 222706fdd9fSRussell King get_thread_info tsk 223706fdd9fSRussell King ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 224706fdd9fSRussell King add r7, r8, #1 @ increment it 225706fdd9fSRussell King str r7, [tsk, #TI_PREEMPT] 2261da177e4SLinus Torvalds#endif 227ccea7a19SRussell King 228187a51adSRussell King irq_handler 2291da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT 23028fab1a2SRussell King str r8, [tsk, #TI_PREEMPT] @ restore preempt count 231706fdd9fSRussell King ldr r0, [tsk, #TI_FLAGS] @ get flags 23228fab1a2SRussell King teq r8, #0 @ if preempt count != 0 23328fab1a2SRussell King movne r0, #0 @ force flags to 0 2341da177e4SLinus Torvalds tst r0, #_TIF_NEED_RESCHED 2351da177e4SLinus Torvalds blne svc_preempt 2361da177e4SLinus Torvalds#endif 237b86040a5SCatalin Marinas ldr r4, [sp, #S_PSR] @ irqs are already disabled 2387ad1bcb2SRussell King#ifdef CONFIG_TRACE_IRQFLAGS 239b86040a5SCatalin Marinas tst r4, #PSR_I_BIT 2407ad1bcb2SRussell King bleq trace_hardirqs_on 2417ad1bcb2SRussell King#endif 242b86040a5SCatalin Marinas svc_exit r4 @ return from exception 243c4c5716eSCatalin Marinas UNWIND(.fnend ) 24493ed3970SCatalin MarinasENDPROC(__irq_svc) 2451da177e4SLinus Torvalds 2461da177e4SLinus Torvalds .ltorg 2471da177e4SLinus Torvalds 2481da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT 2491da177e4SLinus Torvaldssvc_preempt: 25028fab1a2SRussell King mov r8, lr 2511da177e4SLinus Torvalds1: bl preempt_schedule_irq @ irq en/disable is done inside 252706fdd9fSRussell King ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS 2531da177e4SLinus Torvalds tst r0, #_TIF_NEED_RESCHED 25428fab1a2SRussell King moveq pc, r8 @ go again 2551da177e4SLinus Torvalds b 1b 2561da177e4SLinus Torvalds#endif 2571da177e4SLinus Torvalds 2581da177e4SLinus Torvalds .align 5 2591da177e4SLinus Torvalds__und_svc: 260d30a0c8bSNicolas Pitre#ifdef CONFIG_KPROBES 261d30a0c8bSNicolas Pitre @ If a kprobe is about to simulate a "stmdb sp..." instruction, 262d30a0c8bSNicolas Pitre @ it obviously needs free stack space which then will belong to 263d30a0c8bSNicolas Pitre @ the saved context. 264d30a0c8bSNicolas Pitre svc_entry 64 265d30a0c8bSNicolas Pitre#else 266ccea7a19SRussell King svc_entry 267d30a0c8bSNicolas Pitre#endif 2681da177e4SLinus Torvalds 2691da177e4SLinus Torvalds @ 2701da177e4SLinus Torvalds @ call emulation code, which returns using r9 if it has emulated 2711da177e4SLinus Torvalds @ the instruction, or the more conventional lr if we are to treat 2721da177e4SLinus Torvalds @ this as a real undefined instruction 2731da177e4SLinus Torvalds @ 2741da177e4SLinus Torvalds @ r0 - instruction 2751da177e4SLinus Torvalds @ 27683e686eaSCatalin Marinas#ifndef CONFIG_THUMB2_KERNEL 2771da177e4SLinus Torvalds ldr r0, [r2, #-4] 27883e686eaSCatalin Marinas#else 27983e686eaSCatalin Marinas ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2 28083e686eaSCatalin Marinas and r9, r0, #0xf800 28183e686eaSCatalin Marinas cmp r9, #0xe800 @ 32-bit instruction if xx >= 0 28283e686eaSCatalin Marinas ldrhhs r9, [r2] @ bottom 16 bits 28383e686eaSCatalin Marinas orrhs r0, r9, r0, lsl #16 28483e686eaSCatalin Marinas#endif 285b86040a5SCatalin Marinas adr r9, BSYM(1f) 2861da177e4SLinus Torvalds bl call_fpe 2871da177e4SLinus Torvalds 2881da177e4SLinus Torvalds mov r0, sp @ struct pt_regs *regs 2891da177e4SLinus Torvalds bl do_undefinstr 2901da177e4SLinus Torvalds 2911da177e4SLinus Torvalds @ 2921da177e4SLinus Torvalds @ IRQs off again before pulling preserved data off the stack 2931da177e4SLinus Torvalds @ 2941ec42c0cSRussell King1: disable_irq 2951da177e4SLinus Torvalds 2961da177e4SLinus Torvalds @ 2971da177e4SLinus Torvalds @ restore SPSR and restart the instruction 2981da177e4SLinus Torvalds @ 299b86040a5SCatalin Marinas ldr r2, [sp, #S_PSR] @ Get SVC cpsr 300b86040a5SCatalin Marinas svc_exit r2 @ return from exception 301c4c5716eSCatalin Marinas UNWIND(.fnend ) 30293ed3970SCatalin MarinasENDPROC(__und_svc) 3031da177e4SLinus Torvalds 3041da177e4SLinus Torvalds .align 5 3051da177e4SLinus Torvalds__pabt_svc: 306ccea7a19SRussell King svc_entry 3071da177e4SLinus Torvalds 3081da177e4SLinus Torvalds @ 3091da177e4SLinus Torvalds @ re-enable interrupts if appropriate 3101da177e4SLinus Torvalds @ 3111da177e4SLinus Torvalds mrs r9, cpsr 3121da177e4SLinus Torvalds tst r3, #PSR_I_BIT 3131da177e4SLinus Torvalds biceq r9, r9, #PSR_I_BIT 3141da177e4SLinus Torvalds 31548d7927bSPaul Brook mov r0, r2 @ pass address of aborted instruction. 3164fb28474SKirill A. Shutemov#ifdef MULTI_PABORT 31748d7927bSPaul Brook ldr r4, .LCprocfns 31848d7927bSPaul Brook mov lr, pc 31948d7927bSPaul Brook ldr pc, [r4, #PROCESSOR_PABT_FUNC] 32048d7927bSPaul Brook#else 3214fb28474SKirill A. Shutemov bl CPU_PABORT_HANDLER 32248d7927bSPaul Brook#endif 32348d7927bSPaul Brook msr cpsr_c, r9 @ Maybe enable interrupts 3244fb28474SKirill A. Shutemov mov r2, sp @ regs 3251da177e4SLinus Torvalds bl do_PrefetchAbort @ call abort handler 3261da177e4SLinus Torvalds 3271da177e4SLinus Torvalds @ 3281da177e4SLinus Torvalds @ IRQs off again before pulling preserved data off the stack 3291da177e4SLinus Torvalds @ 3301ec42c0cSRussell King disable_irq 3311da177e4SLinus Torvalds 3321da177e4SLinus Torvalds @ 3331da177e4SLinus Torvalds @ restore SPSR and restart the instruction 3341da177e4SLinus Torvalds @ 335b86040a5SCatalin Marinas ldr r2, [sp, #S_PSR] 336b86040a5SCatalin Marinas svc_exit r2 @ return from exception 337c4c5716eSCatalin Marinas UNWIND(.fnend ) 33893ed3970SCatalin MarinasENDPROC(__pabt_svc) 3391da177e4SLinus Torvalds 3401da177e4SLinus Torvalds .align 5 34149f680eaSRussell King.LCcralign: 34249f680eaSRussell King .word cr_alignment 34348d7927bSPaul Brook#ifdef MULTI_DABORT 3441da177e4SLinus Torvalds.LCprocfns: 3451da177e4SLinus Torvalds .word processor 3461da177e4SLinus Torvalds#endif 3471da177e4SLinus Torvalds.LCfp: 3481da177e4SLinus Torvalds .word fp_enter 3491da177e4SLinus Torvalds 3501da177e4SLinus Torvalds/* 3511da177e4SLinus Torvalds * User mode handlers 3522dede2d8SNicolas Pitre * 3532dede2d8SNicolas Pitre * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE 3541da177e4SLinus Torvalds */ 3552dede2d8SNicolas Pitre 3562dede2d8SNicolas Pitre#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) 3572dede2d8SNicolas Pitre#error "sizeof(struct pt_regs) must be a multiple of 8" 3582dede2d8SNicolas Pitre#endif 3592dede2d8SNicolas Pitre 360ccea7a19SRussell King .macro usr_entry 361c4c5716eSCatalin Marinas UNWIND(.fnstart ) 362c4c5716eSCatalin Marinas UNWIND(.cantunwind ) @ don't unwind the user space 363ccea7a19SRussell King sub sp, sp, #S_FRAME_SIZE 364b86040a5SCatalin Marinas ARM( stmib sp, {r1 - r12} ) 365b86040a5SCatalin Marinas THUMB( stmia sp, {r0 - r12} ) 366ccea7a19SRussell King 367ccea7a19SRussell King ldmia r0, {r1 - r3} 368ccea7a19SRussell King add r0, sp, #S_PC @ here for interlock avoidance 369ccea7a19SRussell King mov r4, #-1 @ "" "" "" "" 370ccea7a19SRussell King 371ccea7a19SRussell King str r1, [sp] @ save the "real" r0 copied 372ccea7a19SRussell King @ from the exception stack 3731da177e4SLinus Torvalds 3741da177e4SLinus Torvalds @ 3751da177e4SLinus Torvalds @ We are now ready to fill in the remaining blanks on the stack: 3761da177e4SLinus Torvalds @ 3771da177e4SLinus Torvalds @ r2 - lr_<exception>, already fixed up for correct return/restart 3781da177e4SLinus Torvalds @ r3 - spsr_<exception> 3791da177e4SLinus Torvalds @ r4 - orig_r0 (see pt_regs definition in ptrace.h) 3801da177e4SLinus Torvalds @ 3811da177e4SLinus Torvalds @ Also, separately save sp_usr and lr_usr 3821da177e4SLinus Torvalds @ 383ccea7a19SRussell King stmia r0, {r2 - r4} 384b86040a5SCatalin Marinas ARM( stmdb r0, {sp, lr}^ ) 385b86040a5SCatalin Marinas THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) 3861da177e4SLinus Torvalds 3871da177e4SLinus Torvalds @ 3881da177e4SLinus Torvalds @ Enable the alignment trap while in kernel mode 3891da177e4SLinus Torvalds @ 39049f680eaSRussell King alignment_trap r0 3911da177e4SLinus Torvalds 3921da177e4SLinus Torvalds @ 3931da177e4SLinus Torvalds @ Clear FP to mark the first stack frame 3941da177e4SLinus Torvalds @ 3951da177e4SLinus Torvalds zero_fp 3960d928b0bSUwe Kleine-König 3970d928b0bSUwe Kleine-König asm_trace_hardirqs_off 3981da177e4SLinus Torvalds .endm 3991da177e4SLinus Torvalds 400b49c0f24SNicolas Pitre .macro kuser_cmpxchg_check 401b49c0f24SNicolas Pitre#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 402b49c0f24SNicolas Pitre#ifndef CONFIG_MMU 403b49c0f24SNicolas Pitre#warning "NPTL on non MMU needs fixing" 404b49c0f24SNicolas Pitre#else 405b49c0f24SNicolas Pitre @ Make sure our user space atomic helper is restarted 406b49c0f24SNicolas Pitre @ if it was interrupted in a critical region. Here we 407b49c0f24SNicolas Pitre @ perform a quick test inline since it should be false 408b49c0f24SNicolas Pitre @ 99.9999% of the time. The rest is done out of line. 409b49c0f24SNicolas Pitre cmp r2, #TASK_SIZE 410b49c0f24SNicolas Pitre blhs kuser_cmpxchg_fixup 411b49c0f24SNicolas Pitre#endif 412b49c0f24SNicolas Pitre#endif 413b49c0f24SNicolas Pitre .endm 414b49c0f24SNicolas Pitre 4151da177e4SLinus Torvalds .align 5 4161da177e4SLinus Torvalds__dabt_usr: 417ccea7a19SRussell King usr_entry 418b49c0f24SNicolas Pitre kuser_cmpxchg_check 4191da177e4SLinus Torvalds 4201da177e4SLinus Torvalds @ 4211da177e4SLinus Torvalds @ Call the processor-specific abort handler: 4221da177e4SLinus Torvalds @ 4231da177e4SLinus Torvalds @ r2 - aborted context pc 4241da177e4SLinus Torvalds @ r3 - aborted context cpsr 4251da177e4SLinus Torvalds @ 4261da177e4SLinus Torvalds @ The abort handler must return the aborted address in r0, and 4271da177e4SLinus Torvalds @ the fault status register in r1. 4281da177e4SLinus Torvalds @ 42948d7927bSPaul Brook#ifdef MULTI_DABORT 4301da177e4SLinus Torvalds ldr r4, .LCprocfns 4311da177e4SLinus Torvalds mov lr, pc 43248d7927bSPaul Brook ldr pc, [r4, #PROCESSOR_DABT_FUNC] 4331da177e4SLinus Torvalds#else 43448d7927bSPaul Brook bl CPU_DABORT_HANDLER 4351da177e4SLinus Torvalds#endif 4361da177e4SLinus Torvalds 4371da177e4SLinus Torvalds @ 4381da177e4SLinus Torvalds @ IRQs on, then call the main handler 4391da177e4SLinus Torvalds @ 4401ec42c0cSRussell King enable_irq 4411da177e4SLinus Torvalds mov r2, sp 442b86040a5SCatalin Marinas adr lr, BSYM(ret_from_exception) 4431da177e4SLinus Torvalds b do_DataAbort 444c4c5716eSCatalin Marinas UNWIND(.fnend ) 44593ed3970SCatalin MarinasENDPROC(__dabt_usr) 4461da177e4SLinus Torvalds 4471da177e4SLinus Torvalds .align 5 4481da177e4SLinus Torvalds__irq_usr: 449ccea7a19SRussell King usr_entry 450b49c0f24SNicolas Pitre kuser_cmpxchg_check 4511da177e4SLinus Torvalds 4521da177e4SLinus Torvalds get_thread_info tsk 4531da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT 454706fdd9fSRussell King ldr r8, [tsk, #TI_PREEMPT] @ get preempt count 455706fdd9fSRussell King add r7, r8, #1 @ increment it 456706fdd9fSRussell King str r7, [tsk, #TI_PREEMPT] 4571da177e4SLinus Torvalds#endif 458ccea7a19SRussell King 459187a51adSRussell King irq_handler 4601da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT 461706fdd9fSRussell King ldr r0, [tsk, #TI_PREEMPT] 462706fdd9fSRussell King str r8, [tsk, #TI_PREEMPT] 4631da177e4SLinus Torvalds teq r0, r7 464b86040a5SCatalin Marinas ARM( strne r0, [r0, -r0] ) 465b86040a5SCatalin Marinas THUMB( movne r0, #0 ) 466b86040a5SCatalin Marinas THUMB( strne r0, [r0] ) 4671da177e4SLinus Torvalds#endif 4687ad1bcb2SRussell King#ifdef CONFIG_TRACE_IRQFLAGS 4697ad1bcb2SRussell King bl trace_hardirqs_on 4707ad1bcb2SRussell King#endif 471ccea7a19SRussell King 4721da177e4SLinus Torvalds mov why, #0 4731da177e4SLinus Torvalds b ret_to_user 474c4c5716eSCatalin Marinas UNWIND(.fnend ) 47593ed3970SCatalin MarinasENDPROC(__irq_usr) 4761da177e4SLinus Torvalds 4771da177e4SLinus Torvalds .ltorg 4781da177e4SLinus Torvalds 4791da177e4SLinus Torvalds .align 5 4801da177e4SLinus Torvalds__und_usr: 481ccea7a19SRussell King usr_entry 4821da177e4SLinus Torvalds 4831da177e4SLinus Torvalds @ 4841da177e4SLinus Torvalds @ fall through to the emulation code, which returns using r9 if 4851da177e4SLinus Torvalds @ it has emulated the instruction, or the more conventional lr 4861da177e4SLinus Torvalds @ if we are to treat this as a real undefined instruction 4871da177e4SLinus Torvalds @ 4881da177e4SLinus Torvalds @ r0 - instruction 4891da177e4SLinus Torvalds @ 490b86040a5SCatalin Marinas adr r9, BSYM(ret_from_exception) 491b86040a5SCatalin Marinas adr lr, BSYM(__und_usr_unknown) 492cb170a45SPaul Brook tst r3, #PSR_T_BIT @ Thumb mode? 493b86040a5SCatalin Marinas itet eq @ explicit IT needed for the 1f label 494cb170a45SPaul Brook subeq r4, r2, #4 @ ARM instr at LR - 4 495cb170a45SPaul Brook subne r4, r2, #2 @ Thumb instr at LR - 2 496cb170a45SPaul Brook1: ldreqt r0, [r4] 49726584853SCatalin Marinas#ifdef CONFIG_CPU_ENDIAN_BE8 49826584853SCatalin Marinas reveq r0, r0 @ little endian instruction 49926584853SCatalin Marinas#endif 500cb170a45SPaul Brook beq call_fpe 501cb170a45SPaul Brook @ Thumb instruction 502cb170a45SPaul Brook#if __LINUX_ARM_ARCH__ >= 7 503b86040a5SCatalin Marinas2: 504b86040a5SCatalin Marinas ARM( ldrht r5, [r4], #2 ) 505b86040a5SCatalin Marinas THUMB( ldrht r5, [r4] ) 506b86040a5SCatalin Marinas THUMB( add r4, r4, #2 ) 507cb170a45SPaul Brook and r0, r5, #0xf800 @ mask bits 111x x... .... .... 508cb170a45SPaul Brook cmp r0, #0xe800 @ 32bit instruction if xx != 0 509cb170a45SPaul Brook blo __und_usr_unknown 510cb170a45SPaul Brook3: ldrht r0, [r4] 511cb170a45SPaul Brook add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 512cb170a45SPaul Brook orr r0, r0, r5, lsl #16 513cb170a45SPaul Brook#else 514cb170a45SPaul Brook b __und_usr_unknown 515cb170a45SPaul Brook#endif 516c4c5716eSCatalin Marinas UNWIND(.fnend ) 51793ed3970SCatalin MarinasENDPROC(__und_usr) 518cb170a45SPaul Brook 5191da177e4SLinus Torvalds @ 5201da177e4SLinus Torvalds @ fallthrough to call_fpe 5211da177e4SLinus Torvalds @ 5221da177e4SLinus Torvalds 5231da177e4SLinus Torvalds/* 5241da177e4SLinus Torvalds * The out of line fixup for the ldrt above. 5251da177e4SLinus Torvalds */ 5261da177e4SLinus Torvalds .section .fixup, "ax" 527cb170a45SPaul Brook4: mov pc, r9 5281da177e4SLinus Torvalds .previous 5291da177e4SLinus Torvalds .section __ex_table,"a" 530cb170a45SPaul Brook .long 1b, 4b 531cb170a45SPaul Brook#if __LINUX_ARM_ARCH__ >= 7 532cb170a45SPaul Brook .long 2b, 4b 533cb170a45SPaul Brook .long 3b, 4b 534cb170a45SPaul Brook#endif 5351da177e4SLinus Torvalds .previous 5361da177e4SLinus Torvalds 5371da177e4SLinus Torvalds/* 5381da177e4SLinus Torvalds * Check whether the instruction is a co-processor instruction. 5391da177e4SLinus Torvalds * If yes, we need to call the relevant co-processor handler. 5401da177e4SLinus Torvalds * 5411da177e4SLinus Torvalds * Note that we don't do a full check here for the co-processor 5421da177e4SLinus Torvalds * instructions; all instructions with bit 27 set are well 5431da177e4SLinus Torvalds * defined. The only instructions that should fault are the 5441da177e4SLinus Torvalds * co-processor instructions. However, we have to watch out 5451da177e4SLinus Torvalds * for the ARM6/ARM7 SWI bug. 5461da177e4SLinus Torvalds * 547b5872db4SCatalin Marinas * NEON is a special case that has to be handled here. Not all 548b5872db4SCatalin Marinas * NEON instructions are co-processor instructions, so we have 549b5872db4SCatalin Marinas * to make a special case of checking for them. Plus, there's 550b5872db4SCatalin Marinas * five groups of them, so we have a table of mask/opcode pairs 551b5872db4SCatalin Marinas * to check against, and if any match then we branch off into the 552b5872db4SCatalin Marinas * NEON handler code. 553b5872db4SCatalin Marinas * 5541da177e4SLinus Torvalds * Emulators may wish to make use of the following registers: 5551da177e4SLinus Torvalds * r0 = instruction opcode. 5561da177e4SLinus Torvalds * r2 = PC+4 557db6ccbb6SRussell King * r9 = normal "successful" return address 5581da177e4SLinus Torvalds * r10 = this threads thread_info structure. 559db6ccbb6SRussell King * lr = unrecognised instruction return address 5601da177e4SLinus Torvalds */ 561cb170a45SPaul Brook @ 562cb170a45SPaul Brook @ Fall-through from Thumb-2 __und_usr 563cb170a45SPaul Brook @ 564cb170a45SPaul Brook#ifdef CONFIG_NEON 565cb170a45SPaul Brook adr r6, .LCneon_thumb_opcodes 566cb170a45SPaul Brook b 2f 567cb170a45SPaul Brook#endif 5681da177e4SLinus Torvaldscall_fpe: 569b5872db4SCatalin Marinas#ifdef CONFIG_NEON 570cb170a45SPaul Brook adr r6, .LCneon_arm_opcodes 571b5872db4SCatalin Marinas2: 572b5872db4SCatalin Marinas ldr r7, [r6], #4 @ mask value 573b5872db4SCatalin Marinas cmp r7, #0 @ end mask? 574b5872db4SCatalin Marinas beq 1f 575b5872db4SCatalin Marinas and r8, r0, r7 576b5872db4SCatalin Marinas ldr r7, [r6], #4 @ opcode bits matching in mask 577b5872db4SCatalin Marinas cmp r8, r7 @ NEON instruction? 578b5872db4SCatalin Marinas bne 2b 579b5872db4SCatalin Marinas get_thread_info r10 580b5872db4SCatalin Marinas mov r7, #1 581b5872db4SCatalin Marinas strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used 582b5872db4SCatalin Marinas strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used 583b5872db4SCatalin Marinas b do_vfp @ let VFP handler handle this 584b5872db4SCatalin Marinas1: 585b5872db4SCatalin Marinas#endif 5861da177e4SLinus Torvalds tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 587cb170a45SPaul Brook tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 5881da177e4SLinus Torvalds#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710) 5891da177e4SLinus Torvalds and r8, r0, #0x0f000000 @ mask out op-code bits 5901da177e4SLinus Torvalds teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)? 5911da177e4SLinus Torvalds#endif 5921da177e4SLinus Torvalds moveq pc, lr 5931da177e4SLinus Torvalds get_thread_info r10 @ get current thread 5941da177e4SLinus Torvalds and r8, r0, #0x00000f00 @ mask out CP number 595b86040a5SCatalin Marinas THUMB( lsr r8, r8, #8 ) 5961da177e4SLinus Torvalds mov r7, #1 5971da177e4SLinus Torvalds add r6, r10, #TI_USED_CP 598b86040a5SCatalin Marinas ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] 599b86040a5SCatalin Marinas THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] 6001da177e4SLinus Torvalds#ifdef CONFIG_IWMMXT 6011da177e4SLinus Torvalds @ Test if we need to give access to iWMMXt coprocessors 6021da177e4SLinus Torvalds ldr r5, [r10, #TI_FLAGS] 6031da177e4SLinus Torvalds rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only 6041da177e4SLinus Torvalds movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) 6051da177e4SLinus Torvalds bcs iwmmxt_task_enable 6061da177e4SLinus Torvalds#endif 607b86040a5SCatalin Marinas ARM( add pc, pc, r8, lsr #6 ) 608b86040a5SCatalin Marinas THUMB( lsl r8, r8, #2 ) 609b86040a5SCatalin Marinas THUMB( add pc, r8 ) 610b86040a5SCatalin Marinas nop 6111da177e4SLinus Torvalds 612a771fe6eSCatalin Marinas movw_pc lr @ CP#0 613b86040a5SCatalin Marinas W(b) do_fpe @ CP#1 (FPE) 614b86040a5SCatalin Marinas W(b) do_fpe @ CP#2 (FPE) 615a771fe6eSCatalin Marinas movw_pc lr @ CP#3 616c17fad11SLennert Buytenhek#ifdef CONFIG_CRUNCH 617c17fad11SLennert Buytenhek b crunch_task_enable @ CP#4 (MaverickCrunch) 618c17fad11SLennert Buytenhek b crunch_task_enable @ CP#5 (MaverickCrunch) 619c17fad11SLennert Buytenhek b crunch_task_enable @ CP#6 (MaverickCrunch) 620c17fad11SLennert Buytenhek#else 621a771fe6eSCatalin Marinas movw_pc lr @ CP#4 622a771fe6eSCatalin Marinas movw_pc lr @ CP#5 623a771fe6eSCatalin Marinas movw_pc lr @ CP#6 624c17fad11SLennert Buytenhek#endif 625a771fe6eSCatalin Marinas movw_pc lr @ CP#7 626a771fe6eSCatalin Marinas movw_pc lr @ CP#8 627a771fe6eSCatalin Marinas movw_pc lr @ CP#9 6281da177e4SLinus Torvalds#ifdef CONFIG_VFP 629b86040a5SCatalin Marinas W(b) do_vfp @ CP#10 (VFP) 630b86040a5SCatalin Marinas W(b) do_vfp @ CP#11 (VFP) 6311da177e4SLinus Torvalds#else 632a771fe6eSCatalin Marinas movw_pc lr @ CP#10 (VFP) 633a771fe6eSCatalin Marinas movw_pc lr @ CP#11 (VFP) 6341da177e4SLinus Torvalds#endif 635a771fe6eSCatalin Marinas movw_pc lr @ CP#12 636a771fe6eSCatalin Marinas movw_pc lr @ CP#13 637a771fe6eSCatalin Marinas movw_pc lr @ CP#14 (Debug) 638a771fe6eSCatalin Marinas movw_pc lr @ CP#15 (Control) 6391da177e4SLinus Torvalds 640b5872db4SCatalin Marinas#ifdef CONFIG_NEON 641b5872db4SCatalin Marinas .align 6 642b5872db4SCatalin Marinas 643cb170a45SPaul Brook.LCneon_arm_opcodes: 644b5872db4SCatalin Marinas .word 0xfe000000 @ mask 645b5872db4SCatalin Marinas .word 0xf2000000 @ opcode 646b5872db4SCatalin Marinas 647b5872db4SCatalin Marinas .word 0xff100000 @ mask 648b5872db4SCatalin Marinas .word 0xf4000000 @ opcode 649b5872db4SCatalin Marinas 650b5872db4SCatalin Marinas .word 0x00000000 @ mask 651b5872db4SCatalin Marinas .word 0x00000000 @ opcode 652cb170a45SPaul Brook 653cb170a45SPaul Brook.LCneon_thumb_opcodes: 654cb170a45SPaul Brook .word 0xef000000 @ mask 655cb170a45SPaul Brook .word 0xef000000 @ opcode 656cb170a45SPaul Brook 657cb170a45SPaul Brook .word 0xff100000 @ mask 658cb170a45SPaul Brook .word 0xf9000000 @ opcode 659cb170a45SPaul Brook 660cb170a45SPaul Brook .word 0x00000000 @ mask 661cb170a45SPaul Brook .word 0x00000000 @ opcode 662b5872db4SCatalin Marinas#endif 663b5872db4SCatalin Marinas 6641da177e4SLinus Torvaldsdo_fpe: 6655d25ac03SRussell King enable_irq 6661da177e4SLinus Torvalds ldr r4, .LCfp 6671da177e4SLinus Torvalds add r10, r10, #TI_FPSTATE @ r10 = workspace 6681da177e4SLinus Torvalds ldr pc, [r4] @ Call FP module USR entry point 6691da177e4SLinus Torvalds 6701da177e4SLinus Torvalds/* 6711da177e4SLinus Torvalds * The FP module is called with these registers set: 6721da177e4SLinus Torvalds * r0 = instruction 6731da177e4SLinus Torvalds * r2 = PC+4 6741da177e4SLinus Torvalds * r9 = normal "successful" return address 6751da177e4SLinus Torvalds * r10 = FP workspace 6761da177e4SLinus Torvalds * lr = unrecognised FP instruction return address 6771da177e4SLinus Torvalds */ 6781da177e4SLinus Torvalds 6791da177e4SLinus Torvalds .data 6801da177e4SLinus TorvaldsENTRY(fp_enter) 681db6ccbb6SRussell King .word no_fp 682785d3cd2SNicolas Pitre .previous 6831da177e4SLinus Torvalds 68483e686eaSCatalin MarinasENTRY(no_fp) 68583e686eaSCatalin Marinas mov pc, lr 68683e686eaSCatalin MarinasENDPROC(no_fp) 687db6ccbb6SRussell King 688db6ccbb6SRussell King__und_usr_unknown: 689ecbab71cSRussell King enable_irq 6901da177e4SLinus Torvalds mov r0, sp 691b86040a5SCatalin Marinas adr lr, BSYM(ret_from_exception) 6921da177e4SLinus Torvalds b do_undefinstr 69393ed3970SCatalin MarinasENDPROC(__und_usr_unknown) 6941da177e4SLinus Torvalds 6951da177e4SLinus Torvalds .align 5 6961da177e4SLinus Torvalds__pabt_usr: 697ccea7a19SRussell King usr_entry 6981da177e4SLinus Torvalds 69948d7927bSPaul Brook mov r0, r2 @ pass address of aborted instruction. 7004fb28474SKirill A. Shutemov#ifdef MULTI_PABORT 70148d7927bSPaul Brook ldr r4, .LCprocfns 70248d7927bSPaul Brook mov lr, pc 70348d7927bSPaul Brook ldr pc, [r4, #PROCESSOR_PABT_FUNC] 70448d7927bSPaul Brook#else 7054fb28474SKirill A. Shutemov bl CPU_PABORT_HANDLER 70648d7927bSPaul Brook#endif 7071ec42c0cSRussell King enable_irq @ Enable interrupts 7084fb28474SKirill A. Shutemov mov r2, sp @ regs 7091da177e4SLinus Torvalds bl do_PrefetchAbort @ call abort handler 710c4c5716eSCatalin Marinas UNWIND(.fnend ) 7111da177e4SLinus Torvalds /* fall through */ 7121da177e4SLinus Torvalds/* 7131da177e4SLinus Torvalds * This is the return code to user mode for abort handlers 7141da177e4SLinus Torvalds */ 7151da177e4SLinus TorvaldsENTRY(ret_from_exception) 716c4c5716eSCatalin Marinas UNWIND(.fnstart ) 717c4c5716eSCatalin Marinas UNWIND(.cantunwind ) 7181da177e4SLinus Torvalds get_thread_info tsk 7191da177e4SLinus Torvalds mov why, #0 7201da177e4SLinus Torvalds b ret_to_user 721c4c5716eSCatalin Marinas UNWIND(.fnend ) 72293ed3970SCatalin MarinasENDPROC(__pabt_usr) 72393ed3970SCatalin MarinasENDPROC(ret_from_exception) 7241da177e4SLinus Torvalds 7251da177e4SLinus Torvalds/* 7261da177e4SLinus Torvalds * Register switch for ARMv3 and ARMv4 processors 7271da177e4SLinus Torvalds * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info 7281da177e4SLinus Torvalds * previous and next are guaranteed not to be the same. 7291da177e4SLinus Torvalds */ 7301da177e4SLinus TorvaldsENTRY(__switch_to) 731c4c5716eSCatalin Marinas UNWIND(.fnstart ) 732c4c5716eSCatalin Marinas UNWIND(.cantunwind ) 7331da177e4SLinus Torvalds add ip, r1, #TI_CPU_SAVE 7341da177e4SLinus Torvalds ldr r3, [r2, #TI_TP_VALUE] 735b86040a5SCatalin Marinas ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack 736b86040a5SCatalin Marinas THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack 737b86040a5SCatalin Marinas THUMB( str sp, [ip], #4 ) 738b86040a5SCatalin Marinas THUMB( str lr, [ip], #4 ) 739d6551e88SRussell King#ifdef CONFIG_MMU 740d6551e88SRussell King ldr r6, [r2, #TI_CPU_DOMAIN] 741afeb90caSHyok S. Choi#endif 7424b0e07a5SNicolas Pitre#if defined(CONFIG_HAS_TLS_REG) 7432d2669b6SNicolas Pitre mcr p15, 0, r3, c13, c0, 3 @ set TLS register 7444b0e07a5SNicolas Pitre#elif !defined(CONFIG_TLS_REG_EMUL) 7451da177e4SLinus Torvalds mov r4, #0xffff0fff 7462d2669b6SNicolas Pitre str r3, [r4, #-15] @ TLS val at 0xffff0ff0 7472d2669b6SNicolas Pitre#endif 748afeb90caSHyok S. Choi#ifdef CONFIG_MMU 7491da177e4SLinus Torvalds mcr p15, 0, r6, c3, c0, 0 @ Set domain register 750afeb90caSHyok S. Choi#endif 751d6551e88SRussell King mov r5, r0 752d6551e88SRussell King add r4, r2, #TI_CPU_SAVE 753d6551e88SRussell King ldr r0, =thread_notify_head 754d6551e88SRussell King mov r1, #THREAD_NOTIFY_SWITCH 755d6551e88SRussell King bl atomic_notifier_call_chain 756b86040a5SCatalin Marinas THUMB( mov ip, r4 ) 757d6551e88SRussell King mov r0, r5 758b86040a5SCatalin Marinas ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously 759b86040a5SCatalin Marinas THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously 760b86040a5SCatalin Marinas THUMB( ldr sp, [ip], #4 ) 761b86040a5SCatalin Marinas THUMB( ldr pc, [ip] ) 762c4c5716eSCatalin Marinas UNWIND(.fnend ) 76393ed3970SCatalin MarinasENDPROC(__switch_to) 7641da177e4SLinus Torvalds 7651da177e4SLinus Torvalds __INIT 7662d2669b6SNicolas Pitre 7672d2669b6SNicolas Pitre/* 7682d2669b6SNicolas Pitre * User helpers. 7692d2669b6SNicolas Pitre * 7702d2669b6SNicolas Pitre * These are segment of kernel provided user code reachable from user space 7712d2669b6SNicolas Pitre * at a fixed address in kernel memory. This is used to provide user space 7722d2669b6SNicolas Pitre * with some operations which require kernel help because of unimplemented 7732d2669b6SNicolas Pitre * native feature and/or instructions in many ARM CPUs. The idea is for 7742d2669b6SNicolas Pitre * this code to be executed directly in user mode for best efficiency but 7752d2669b6SNicolas Pitre * which is too intimate with the kernel counter part to be left to user 7762d2669b6SNicolas Pitre * libraries. In fact this code might even differ from one CPU to another 7772d2669b6SNicolas Pitre * depending on the available instruction set and restrictions like on 7782d2669b6SNicolas Pitre * SMP systems. In other words, the kernel reserves the right to change 7792d2669b6SNicolas Pitre * this code as needed without warning. Only the entry points and their 7802d2669b6SNicolas Pitre * results are guaranteed to be stable. 7812d2669b6SNicolas Pitre * 7822d2669b6SNicolas Pitre * Each segment is 32-byte aligned and will be moved to the top of the high 7832d2669b6SNicolas Pitre * vector page. New segments (if ever needed) must be added in front of 7842d2669b6SNicolas Pitre * existing ones. This mechanism should be used only for things that are 7852d2669b6SNicolas Pitre * really small and justified, and not be abused freely. 7862d2669b6SNicolas Pitre * 7872d2669b6SNicolas Pitre * User space is expected to implement those things inline when optimizing 7882d2669b6SNicolas Pitre * for a processor that has the necessary native support, but only if such 7892d2669b6SNicolas Pitre * resulting binaries are already to be incompatible with earlier ARM 7902d2669b6SNicolas Pitre * processors due to the use of unsupported instructions other than what 7912d2669b6SNicolas Pitre * is provided here. In other words don't make binaries unable to run on 7922d2669b6SNicolas Pitre * earlier processors just for the sake of not using these kernel helpers 7932d2669b6SNicolas Pitre * if your compiled code is not going to use the new instructions for other 7942d2669b6SNicolas Pitre * purpose. 7952d2669b6SNicolas Pitre */ 796b86040a5SCatalin Marinas THUMB( .arm ) 7972d2669b6SNicolas Pitre 798ba9b5d76SNicolas Pitre .macro usr_ret, reg 799ba9b5d76SNicolas Pitre#ifdef CONFIG_ARM_THUMB 800ba9b5d76SNicolas Pitre bx \reg 801ba9b5d76SNicolas Pitre#else 802ba9b5d76SNicolas Pitre mov pc, \reg 803ba9b5d76SNicolas Pitre#endif 804ba9b5d76SNicolas Pitre .endm 805ba9b5d76SNicolas Pitre 8062d2669b6SNicolas Pitre .align 5 8072d2669b6SNicolas Pitre .globl __kuser_helper_start 8082d2669b6SNicolas Pitre__kuser_helper_start: 8092d2669b6SNicolas Pitre 8102d2669b6SNicolas Pitre/* 8112d2669b6SNicolas Pitre * Reference prototype: 8122d2669b6SNicolas Pitre * 8137c612bfdSNicolas Pitre * void __kernel_memory_barrier(void) 8147c612bfdSNicolas Pitre * 8157c612bfdSNicolas Pitre * Input: 8167c612bfdSNicolas Pitre * 8177c612bfdSNicolas Pitre * lr = return address 8187c612bfdSNicolas Pitre * 8197c612bfdSNicolas Pitre * Output: 8207c612bfdSNicolas Pitre * 8217c612bfdSNicolas Pitre * none 8227c612bfdSNicolas Pitre * 8237c612bfdSNicolas Pitre * Clobbered: 8247c612bfdSNicolas Pitre * 825b49c0f24SNicolas Pitre * none 8267c612bfdSNicolas Pitre * 8277c612bfdSNicolas Pitre * Definition and user space usage example: 8287c612bfdSNicolas Pitre * 8297c612bfdSNicolas Pitre * typedef void (__kernel_dmb_t)(void); 8307c612bfdSNicolas Pitre * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0) 8317c612bfdSNicolas Pitre * 8327c612bfdSNicolas Pitre * Apply any needed memory barrier to preserve consistency with data modified 8337c612bfdSNicolas Pitre * manually and __kuser_cmpxchg usage. 8347c612bfdSNicolas Pitre * 8357c612bfdSNicolas Pitre * This could be used as follows: 8367c612bfdSNicolas Pitre * 8377c612bfdSNicolas Pitre * #define __kernel_dmb() \ 8387c612bfdSNicolas Pitre * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \ 8396896eec0SPaul Brook * : : : "r0", "lr","cc" ) 8407c612bfdSNicolas Pitre */ 8417c612bfdSNicolas Pitre 8427c612bfdSNicolas Pitre__kuser_memory_barrier: @ 0xffff0fa0 843bac4e960SRussell King smp_dmb 844ba9b5d76SNicolas Pitre usr_ret lr 8457c612bfdSNicolas Pitre 8467c612bfdSNicolas Pitre .align 5 8477c612bfdSNicolas Pitre 8487c612bfdSNicolas Pitre/* 8497c612bfdSNicolas Pitre * Reference prototype: 8507c612bfdSNicolas Pitre * 8512d2669b6SNicolas Pitre * int __kernel_cmpxchg(int oldval, int newval, int *ptr) 8522d2669b6SNicolas Pitre * 8532d2669b6SNicolas Pitre * Input: 8542d2669b6SNicolas Pitre * 8552d2669b6SNicolas Pitre * r0 = oldval 8562d2669b6SNicolas Pitre * r1 = newval 8572d2669b6SNicolas Pitre * r2 = ptr 8582d2669b6SNicolas Pitre * lr = return address 8592d2669b6SNicolas Pitre * 8602d2669b6SNicolas Pitre * Output: 8612d2669b6SNicolas Pitre * 8622d2669b6SNicolas Pitre * r0 = returned value (zero or non-zero) 8632d2669b6SNicolas Pitre * C flag = set if r0 == 0, clear if r0 != 0 8642d2669b6SNicolas Pitre * 8652d2669b6SNicolas Pitre * Clobbered: 8662d2669b6SNicolas Pitre * 8672d2669b6SNicolas Pitre * r3, ip, flags 8682d2669b6SNicolas Pitre * 8692d2669b6SNicolas Pitre * Definition and user space usage example: 8702d2669b6SNicolas Pitre * 8712d2669b6SNicolas Pitre * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr); 8722d2669b6SNicolas Pitre * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0) 8732d2669b6SNicolas Pitre * 8742d2669b6SNicolas Pitre * Atomically store newval in *ptr if *ptr is equal to oldval for user space. 8752d2669b6SNicolas Pitre * Return zero if *ptr was changed or non-zero if no exchange happened. 8762d2669b6SNicolas Pitre * The C flag is also set if *ptr was changed to allow for assembly 8772d2669b6SNicolas Pitre * optimization in the calling code. 8782d2669b6SNicolas Pitre * 8795964eae8SNicolas Pitre * Notes: 8805964eae8SNicolas Pitre * 8815964eae8SNicolas Pitre * - This routine already includes memory barriers as needed. 8825964eae8SNicolas Pitre * 8832d2669b6SNicolas Pitre * For example, a user space atomic_add implementation could look like this: 8842d2669b6SNicolas Pitre * 8852d2669b6SNicolas Pitre * #define atomic_add(ptr, val) \ 8862d2669b6SNicolas Pitre * ({ register unsigned int *__ptr asm("r2") = (ptr); \ 8872d2669b6SNicolas Pitre * register unsigned int __result asm("r1"); \ 8882d2669b6SNicolas Pitre * asm volatile ( \ 8892d2669b6SNicolas Pitre * "1: @ atomic_add\n\t" \ 8902d2669b6SNicolas Pitre * "ldr r0, [r2]\n\t" \ 8912d2669b6SNicolas Pitre * "mov r3, #0xffff0fff\n\t" \ 8922d2669b6SNicolas Pitre * "add lr, pc, #4\n\t" \ 8932d2669b6SNicolas Pitre * "add r1, r0, %2\n\t" \ 8942d2669b6SNicolas Pitre * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \ 8952d2669b6SNicolas Pitre * "bcc 1b" \ 8962d2669b6SNicolas Pitre * : "=&r" (__result) \ 8972d2669b6SNicolas Pitre * : "r" (__ptr), "rIL" (val) \ 8982d2669b6SNicolas Pitre * : "r0","r3","ip","lr","cc","memory" ); \ 8992d2669b6SNicolas Pitre * __result; }) 9002d2669b6SNicolas Pitre */ 9012d2669b6SNicolas Pitre 9022d2669b6SNicolas Pitre__kuser_cmpxchg: @ 0xffff0fc0 9032d2669b6SNicolas Pitre 904dcef1f63SNicolas Pitre#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG) 9052d2669b6SNicolas Pitre 906dcef1f63SNicolas Pitre /* 907dcef1f63SNicolas Pitre * Poor you. No fast solution possible... 908dcef1f63SNicolas Pitre * The kernel itself must perform the operation. 909dcef1f63SNicolas Pitre * A special ghost syscall is used for that (see traps.c). 910dcef1f63SNicolas Pitre */ 9115e097445SNicolas Pitre stmfd sp!, {r7, lr} 912*cc20d429SRussell King ldr r7, =1f @ it's 20 bits 913*cc20d429SRussell King swi __ARM_NR_cmpxchg 9145e097445SNicolas Pitre ldmfd sp!, {r7, pc} 915*cc20d429SRussell King1: .word __ARM_NR_cmpxchg 916dcef1f63SNicolas Pitre 917dcef1f63SNicolas Pitre#elif __LINUX_ARM_ARCH__ < 6 9182d2669b6SNicolas Pitre 91949bca4c2SNicolas Pitre#ifdef CONFIG_MMU 920b49c0f24SNicolas Pitre 921b49c0f24SNicolas Pitre /* 922b49c0f24SNicolas Pitre * The only thing that can break atomicity in this cmpxchg 923b49c0f24SNicolas Pitre * implementation is either an IRQ or a data abort exception 924b49c0f24SNicolas Pitre * causing another process/thread to be scheduled in the middle 925b49c0f24SNicolas Pitre * of the critical sequence. To prevent this, code is added to 926b49c0f24SNicolas Pitre * the IRQ and data abort exception handlers to set the pc back 927b49c0f24SNicolas Pitre * to the beginning of the critical section if it is found to be 928b49c0f24SNicolas Pitre * within that critical section (see kuser_cmpxchg_fixup). 929b49c0f24SNicolas Pitre */ 930b49c0f24SNicolas Pitre1: ldr r3, [r2] @ load current val 931b49c0f24SNicolas Pitre subs r3, r3, r0 @ compare with oldval 932b49c0f24SNicolas Pitre2: streq r1, [r2] @ store newval if eq 933b49c0f24SNicolas Pitre rsbs r0, r3, #0 @ set return val and C flag 934b49c0f24SNicolas Pitre usr_ret lr 935b49c0f24SNicolas Pitre 936b49c0f24SNicolas Pitre .text 937b49c0f24SNicolas Pitrekuser_cmpxchg_fixup: 938b49c0f24SNicolas Pitre @ Called from kuser_cmpxchg_check macro. 939b49c0f24SNicolas Pitre @ r2 = address of interrupted insn (must be preserved). 940b49c0f24SNicolas Pitre @ sp = saved regs. r7 and r8 are clobbered. 941b49c0f24SNicolas Pitre @ 1b = first critical insn, 2b = last critical insn. 942b49c0f24SNicolas Pitre @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b. 943b49c0f24SNicolas Pitre mov r7, #0xffff0fff 944b49c0f24SNicolas Pitre sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) 945b49c0f24SNicolas Pitre subs r8, r2, r7 946b49c0f24SNicolas Pitre rsbcss r8, r8, #(2b - 1b) 947b49c0f24SNicolas Pitre strcs r7, [sp, #S_PC] 948b49c0f24SNicolas Pitre mov pc, lr 949b49c0f24SNicolas Pitre .previous 950b49c0f24SNicolas Pitre 95149bca4c2SNicolas Pitre#else 95249bca4c2SNicolas Pitre#warning "NPTL on non MMU needs fixing" 95349bca4c2SNicolas Pitre mov r0, #-1 95449bca4c2SNicolas Pitre adds r0, r0, #0 955ba9b5d76SNicolas Pitre usr_ret lr 956b49c0f24SNicolas Pitre#endif 9572d2669b6SNicolas Pitre 9582d2669b6SNicolas Pitre#else 9592d2669b6SNicolas Pitre 9607c612bfdSNicolas Pitre#ifdef CONFIG_SMP 9617c612bfdSNicolas Pitre mcr p15, 0, r0, c7, c10, 5 @ dmb 9627c612bfdSNicolas Pitre#endif 963b49c0f24SNicolas Pitre1: ldrex r3, [r2] 9642d2669b6SNicolas Pitre subs r3, r3, r0 9652d2669b6SNicolas Pitre strexeq r3, r1, [r2] 966b49c0f24SNicolas Pitre teqeq r3, #1 967b49c0f24SNicolas Pitre beq 1b 9682d2669b6SNicolas Pitre rsbs r0, r3, #0 969b49c0f24SNicolas Pitre /* beware -- each __kuser slot must be 8 instructions max */ 9707c612bfdSNicolas Pitre#ifdef CONFIG_SMP 971b49c0f24SNicolas Pitre b __kuser_memory_barrier 972b49c0f24SNicolas Pitre#else 973ba9b5d76SNicolas Pitre usr_ret lr 974b49c0f24SNicolas Pitre#endif 9752d2669b6SNicolas Pitre 9762d2669b6SNicolas Pitre#endif 9772d2669b6SNicolas Pitre 9782d2669b6SNicolas Pitre .align 5 9792d2669b6SNicolas Pitre 9802d2669b6SNicolas Pitre/* 9812d2669b6SNicolas Pitre * Reference prototype: 9822d2669b6SNicolas Pitre * 9832d2669b6SNicolas Pitre * int __kernel_get_tls(void) 9842d2669b6SNicolas Pitre * 9852d2669b6SNicolas Pitre * Input: 9862d2669b6SNicolas Pitre * 9872d2669b6SNicolas Pitre * lr = return address 9882d2669b6SNicolas Pitre * 9892d2669b6SNicolas Pitre * Output: 9902d2669b6SNicolas Pitre * 9912d2669b6SNicolas Pitre * r0 = TLS value 9922d2669b6SNicolas Pitre * 9932d2669b6SNicolas Pitre * Clobbered: 9942d2669b6SNicolas Pitre * 995b49c0f24SNicolas Pitre * none 9962d2669b6SNicolas Pitre * 9972d2669b6SNicolas Pitre * Definition and user space usage example: 9982d2669b6SNicolas Pitre * 9992d2669b6SNicolas Pitre * typedef int (__kernel_get_tls_t)(void); 10002d2669b6SNicolas Pitre * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0) 10012d2669b6SNicolas Pitre * 10022d2669b6SNicolas Pitre * Get the TLS value as previously set via the __ARM_NR_set_tls syscall. 10032d2669b6SNicolas Pitre * 10042d2669b6SNicolas Pitre * This could be used as follows: 10052d2669b6SNicolas Pitre * 10062d2669b6SNicolas Pitre * #define __kernel_get_tls() \ 10072d2669b6SNicolas Pitre * ({ register unsigned int __val asm("r0"); \ 10082d2669b6SNicolas Pitre * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \ 10092d2669b6SNicolas Pitre * : "=r" (__val) : : "lr","cc" ); \ 10102d2669b6SNicolas Pitre * __val; }) 10112d2669b6SNicolas Pitre */ 10122d2669b6SNicolas Pitre 10132d2669b6SNicolas Pitre__kuser_get_tls: @ 0xffff0fe0 10142d2669b6SNicolas Pitre 10154b0e07a5SNicolas Pitre#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) 10162d2669b6SNicolas Pitre ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 10172d2669b6SNicolas Pitre#else 10182d2669b6SNicolas Pitre mrc p15, 0, r0, c13, c0, 3 @ read TLS register 10192d2669b6SNicolas Pitre#endif 1020ba9b5d76SNicolas Pitre usr_ret lr 10212d2669b6SNicolas Pitre 10222d2669b6SNicolas Pitre .rep 5 10232d2669b6SNicolas Pitre .word 0 @ pad up to __kuser_helper_version 10242d2669b6SNicolas Pitre .endr 10252d2669b6SNicolas Pitre 10262d2669b6SNicolas Pitre/* 10272d2669b6SNicolas Pitre * Reference declaration: 10282d2669b6SNicolas Pitre * 10292d2669b6SNicolas Pitre * extern unsigned int __kernel_helper_version; 10302d2669b6SNicolas Pitre * 10312d2669b6SNicolas Pitre * Definition and user space usage example: 10322d2669b6SNicolas Pitre * 10332d2669b6SNicolas Pitre * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc) 10342d2669b6SNicolas Pitre * 10352d2669b6SNicolas Pitre * User space may read this to determine the curent number of helpers 10362d2669b6SNicolas Pitre * available. 10372d2669b6SNicolas Pitre */ 10382d2669b6SNicolas Pitre 10392d2669b6SNicolas Pitre__kuser_helper_version: @ 0xffff0ffc 10402d2669b6SNicolas Pitre .word ((__kuser_helper_end - __kuser_helper_start) >> 5) 10412d2669b6SNicolas Pitre 10422d2669b6SNicolas Pitre .globl __kuser_helper_end 10432d2669b6SNicolas Pitre__kuser_helper_end: 10442d2669b6SNicolas Pitre 1045b86040a5SCatalin Marinas THUMB( .thumb ) 10462d2669b6SNicolas Pitre 10471da177e4SLinus Torvalds/* 10481da177e4SLinus Torvalds * Vector stubs. 10491da177e4SLinus Torvalds * 10507933523dSRussell King * This code is copied to 0xffff0200 so we can use branches in the 10517933523dSRussell King * vectors, rather than ldr's. Note that this code must not 10527933523dSRussell King * exceed 0x300 bytes. 10531da177e4SLinus Torvalds * 10541da177e4SLinus Torvalds * Common stub entry macro: 10551da177e4SLinus Torvalds * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 1056ccea7a19SRussell King * 1057ccea7a19SRussell King * SP points to a minimal amount of processor-private memory, the address 1058ccea7a19SRussell King * of which is copied into r0 for the mode specific abort handler. 10591da177e4SLinus Torvalds */ 1060b7ec4795SNicolas Pitre .macro vector_stub, name, mode, correction=0 10611da177e4SLinus Torvalds .align 5 10621da177e4SLinus Torvalds 10631da177e4SLinus Torvaldsvector_\name: 10641da177e4SLinus Torvalds .if \correction 10651da177e4SLinus Torvalds sub lr, lr, #\correction 10661da177e4SLinus Torvalds .endif 10671da177e4SLinus Torvalds 1068ccea7a19SRussell King @ 1069ccea7a19SRussell King @ Save r0, lr_<exception> (parent PC) and spsr_<exception> 1070ccea7a19SRussell King @ (parent CPSR) 1071ccea7a19SRussell King @ 1072ccea7a19SRussell King stmia sp, {r0, lr} @ save r0, lr 1073ccea7a19SRussell King mrs lr, spsr 1074ccea7a19SRussell King str lr, [sp, #8] @ save spsr 1075ccea7a19SRussell King 1076ccea7a19SRussell King @ 1077ccea7a19SRussell King @ Prepare for SVC32 mode. IRQs remain disabled. 1078ccea7a19SRussell King @ 1079ccea7a19SRussell King mrs r0, cpsr 1080b86040a5SCatalin Marinas eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) 1081ccea7a19SRussell King msr spsr_cxsf, r0 1082ccea7a19SRussell King 1083ccea7a19SRussell King @ 1084ccea7a19SRussell King @ the branch table must immediately follow this code 1085ccea7a19SRussell King @ 1086ccea7a19SRussell King and lr, lr, #0x0f 1087b86040a5SCatalin Marinas THUMB( adr r0, 1f ) 1088b86040a5SCatalin Marinas THUMB( ldr lr, [r0, lr, lsl #2] ) 1089b7ec4795SNicolas Pitre mov r0, sp 1090b86040a5SCatalin Marinas ARM( ldr lr, [pc, lr, lsl #2] ) 1091ccea7a19SRussell King movs pc, lr @ branch to handler in SVC mode 109293ed3970SCatalin MarinasENDPROC(vector_\name) 109388987ef9SCatalin Marinas 109488987ef9SCatalin Marinas .align 2 109588987ef9SCatalin Marinas @ handler addresses follow this label 109688987ef9SCatalin Marinas1: 10971da177e4SLinus Torvalds .endm 10981da177e4SLinus Torvalds 10997933523dSRussell King .globl __stubs_start 11001da177e4SLinus Torvalds__stubs_start: 11011da177e4SLinus Torvalds/* 11021da177e4SLinus Torvalds * Interrupt dispatcher 11031da177e4SLinus Torvalds */ 1104b7ec4795SNicolas Pitre vector_stub irq, IRQ_MODE, 4 11051da177e4SLinus Torvalds 11061da177e4SLinus Torvalds .long __irq_usr @ 0 (USR_26 / USR_32) 11071da177e4SLinus Torvalds .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 11081da177e4SLinus Torvalds .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) 11091da177e4SLinus Torvalds .long __irq_svc @ 3 (SVC_26 / SVC_32) 11101da177e4SLinus Torvalds .long __irq_invalid @ 4 11111da177e4SLinus Torvalds .long __irq_invalid @ 5 11121da177e4SLinus Torvalds .long __irq_invalid @ 6 11131da177e4SLinus Torvalds .long __irq_invalid @ 7 11141da177e4SLinus Torvalds .long __irq_invalid @ 8 11151da177e4SLinus Torvalds .long __irq_invalid @ 9 11161da177e4SLinus Torvalds .long __irq_invalid @ a 11171da177e4SLinus Torvalds .long __irq_invalid @ b 11181da177e4SLinus Torvalds .long __irq_invalid @ c 11191da177e4SLinus Torvalds .long __irq_invalid @ d 11201da177e4SLinus Torvalds .long __irq_invalid @ e 11211da177e4SLinus Torvalds .long __irq_invalid @ f 11221da177e4SLinus Torvalds 11231da177e4SLinus Torvalds/* 11241da177e4SLinus Torvalds * Data abort dispatcher 11251da177e4SLinus Torvalds * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 11261da177e4SLinus Torvalds */ 1127b7ec4795SNicolas Pitre vector_stub dabt, ABT_MODE, 8 11281da177e4SLinus Torvalds 11291da177e4SLinus Torvalds .long __dabt_usr @ 0 (USR_26 / USR_32) 11301da177e4SLinus Torvalds .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 11311da177e4SLinus Torvalds .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) 11321da177e4SLinus Torvalds .long __dabt_svc @ 3 (SVC_26 / SVC_32) 11331da177e4SLinus Torvalds .long __dabt_invalid @ 4 11341da177e4SLinus Torvalds .long __dabt_invalid @ 5 11351da177e4SLinus Torvalds .long __dabt_invalid @ 6 11361da177e4SLinus Torvalds .long __dabt_invalid @ 7 11371da177e4SLinus Torvalds .long __dabt_invalid @ 8 11381da177e4SLinus Torvalds .long __dabt_invalid @ 9 11391da177e4SLinus Torvalds .long __dabt_invalid @ a 11401da177e4SLinus Torvalds .long __dabt_invalid @ b 11411da177e4SLinus Torvalds .long __dabt_invalid @ c 11421da177e4SLinus Torvalds .long __dabt_invalid @ d 11431da177e4SLinus Torvalds .long __dabt_invalid @ e 11441da177e4SLinus Torvalds .long __dabt_invalid @ f 11451da177e4SLinus Torvalds 11461da177e4SLinus Torvalds/* 11471da177e4SLinus Torvalds * Prefetch abort dispatcher 11481da177e4SLinus Torvalds * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 11491da177e4SLinus Torvalds */ 1150b7ec4795SNicolas Pitre vector_stub pabt, ABT_MODE, 4 11511da177e4SLinus Torvalds 11521da177e4SLinus Torvalds .long __pabt_usr @ 0 (USR_26 / USR_32) 11531da177e4SLinus Torvalds .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 11541da177e4SLinus Torvalds .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) 11551da177e4SLinus Torvalds .long __pabt_svc @ 3 (SVC_26 / SVC_32) 11561da177e4SLinus Torvalds .long __pabt_invalid @ 4 11571da177e4SLinus Torvalds .long __pabt_invalid @ 5 11581da177e4SLinus Torvalds .long __pabt_invalid @ 6 11591da177e4SLinus Torvalds .long __pabt_invalid @ 7 11601da177e4SLinus Torvalds .long __pabt_invalid @ 8 11611da177e4SLinus Torvalds .long __pabt_invalid @ 9 11621da177e4SLinus Torvalds .long __pabt_invalid @ a 11631da177e4SLinus Torvalds .long __pabt_invalid @ b 11641da177e4SLinus Torvalds .long __pabt_invalid @ c 11651da177e4SLinus Torvalds .long __pabt_invalid @ d 11661da177e4SLinus Torvalds .long __pabt_invalid @ e 11671da177e4SLinus Torvalds .long __pabt_invalid @ f 11681da177e4SLinus Torvalds 11691da177e4SLinus Torvalds/* 11701da177e4SLinus Torvalds * Undef instr entry dispatcher 11711da177e4SLinus Torvalds * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 11721da177e4SLinus Torvalds */ 1173b7ec4795SNicolas Pitre vector_stub und, UND_MODE 11741da177e4SLinus Torvalds 11751da177e4SLinus Torvalds .long __und_usr @ 0 (USR_26 / USR_32) 11761da177e4SLinus Torvalds .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 11771da177e4SLinus Torvalds .long __und_invalid @ 2 (IRQ_26 / IRQ_32) 11781da177e4SLinus Torvalds .long __und_svc @ 3 (SVC_26 / SVC_32) 11791da177e4SLinus Torvalds .long __und_invalid @ 4 11801da177e4SLinus Torvalds .long __und_invalid @ 5 11811da177e4SLinus Torvalds .long __und_invalid @ 6 11821da177e4SLinus Torvalds .long __und_invalid @ 7 11831da177e4SLinus Torvalds .long __und_invalid @ 8 11841da177e4SLinus Torvalds .long __und_invalid @ 9 11851da177e4SLinus Torvalds .long __und_invalid @ a 11861da177e4SLinus Torvalds .long __und_invalid @ b 11871da177e4SLinus Torvalds .long __und_invalid @ c 11881da177e4SLinus Torvalds .long __und_invalid @ d 11891da177e4SLinus Torvalds .long __und_invalid @ e 11901da177e4SLinus Torvalds .long __und_invalid @ f 11911da177e4SLinus Torvalds 11921da177e4SLinus Torvalds .align 5 11931da177e4SLinus Torvalds 11941da177e4SLinus Torvalds/*============================================================================= 11951da177e4SLinus Torvalds * Undefined FIQs 11961da177e4SLinus Torvalds *----------------------------------------------------------------------------- 11971da177e4SLinus Torvalds * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC 11981da177e4SLinus Torvalds * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg. 11991da177e4SLinus Torvalds * Basically to switch modes, we *HAVE* to clobber one register... brain 12001da177e4SLinus Torvalds * damage alert! I don't think that we can execute any code in here in any 12011da177e4SLinus Torvalds * other mode than FIQ... Ok you can switch to another mode, but you can't 12021da177e4SLinus Torvalds * get out of that mode without clobbering one register. 12031da177e4SLinus Torvalds */ 12041da177e4SLinus Torvaldsvector_fiq: 12051da177e4SLinus Torvalds disable_fiq 12061da177e4SLinus Torvalds subs pc, lr, #4 12071da177e4SLinus Torvalds 12081da177e4SLinus Torvalds/*============================================================================= 12091da177e4SLinus Torvalds * Address exception handler 12101da177e4SLinus Torvalds *----------------------------------------------------------------------------- 12111da177e4SLinus Torvalds * These aren't too critical. 12121da177e4SLinus Torvalds * (they're not supposed to happen, and won't happen in 32-bit data mode). 12131da177e4SLinus Torvalds */ 12141da177e4SLinus Torvalds 12151da177e4SLinus Torvaldsvector_addrexcptn: 12161da177e4SLinus Torvalds b vector_addrexcptn 12171da177e4SLinus Torvalds 12181da177e4SLinus Torvalds/* 12191da177e4SLinus Torvalds * We group all the following data together to optimise 12201da177e4SLinus Torvalds * for CPUs with separate I & D caches. 12211da177e4SLinus Torvalds */ 12221da177e4SLinus Torvalds .align 5 12231da177e4SLinus Torvalds 12241da177e4SLinus Torvalds.LCvswi: 12251da177e4SLinus Torvalds .word vector_swi 12261da177e4SLinus Torvalds 12277933523dSRussell King .globl __stubs_end 12281da177e4SLinus Torvalds__stubs_end: 12291da177e4SLinus Torvalds 12307933523dSRussell King .equ stubs_offset, __vectors_start + 0x200 - __stubs_start 12311da177e4SLinus Torvalds 12327933523dSRussell King .globl __vectors_start 12337933523dSRussell King__vectors_start: 1234b86040a5SCatalin Marinas ARM( swi SYS_ERROR0 ) 1235b86040a5SCatalin Marinas THUMB( svc #0 ) 1236b86040a5SCatalin Marinas THUMB( nop ) 1237b86040a5SCatalin Marinas W(b) vector_und + stubs_offset 1238b86040a5SCatalin Marinas W(ldr) pc, .LCvswi + stubs_offset 1239b86040a5SCatalin Marinas W(b) vector_pabt + stubs_offset 1240b86040a5SCatalin Marinas W(b) vector_dabt + stubs_offset 1241b86040a5SCatalin Marinas W(b) vector_addrexcptn + stubs_offset 1242b86040a5SCatalin Marinas W(b) vector_irq + stubs_offset 1243b86040a5SCatalin Marinas W(b) vector_fiq + stubs_offset 12441da177e4SLinus Torvalds 12457933523dSRussell King .globl __vectors_end 12467933523dSRussell King__vectors_end: 12471da177e4SLinus Torvalds 12481da177e4SLinus Torvalds .data 12491da177e4SLinus Torvalds 12501da177e4SLinus Torvalds .globl cr_alignment 12511da177e4SLinus Torvalds .globl cr_no_alignment 12521da177e4SLinus Torvaldscr_alignment: 12531da177e4SLinus Torvalds .space 4 12541da177e4SLinus Torvaldscr_no_alignment: 12551da177e4SLinus Torvalds .space 4 1256