xref: /openbmc/linux/arch/arm/kernel/entry-armv.S (revision 7e20269647169e7ea08a62bdc4979a3ba32e615c)
11da177e4SLinus Torvalds/*
21da177e4SLinus Torvalds *  linux/arch/arm/kernel/entry-armv.S
31da177e4SLinus Torvalds *
41da177e4SLinus Torvalds *  Copyright (C) 1996,1997,1998 Russell King.
51da177e4SLinus Torvalds *  ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6afeb90caSHyok S. Choi *  nommu support by Hyok S. Choi (hyok.choi@samsung.com)
71da177e4SLinus Torvalds *
81da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or modify
91da177e4SLinus Torvalds * it under the terms of the GNU General Public License version 2 as
101da177e4SLinus Torvalds * published by the Free Software Foundation.
111da177e4SLinus Torvalds *
121da177e4SLinus Torvalds *  Low-level vector interface routines
131da177e4SLinus Torvalds *
1470b6f2b4SNicolas Pitre *  Note:  there is a StrongARM bug in the STMIA rn, {regs}^ instruction
1570b6f2b4SNicolas Pitre *  that causes it to save wrong values...  Be aware!
161da177e4SLinus Torvalds */
171da177e4SLinus Torvalds
18f09b9979SNicolas Pitre#include <asm/memory.h>
191da177e4SLinus Torvalds#include <asm/glue.h>
201da177e4SLinus Torvalds#include <asm/vfpmacros.h>
21a09e64fbSRussell King#include <mach/entry-macro.S>
22d6551e88SRussell King#include <asm/thread_notify.h>
23c4c5716eSCatalin Marinas#include <asm/unwind.h>
24cc20d429SRussell King#include <asm/unistd.h>
25f159f4edSTony Lindgren#include <asm/tls.h>
261da177e4SLinus Torvalds
271da177e4SLinus Torvalds#include "entry-header.S"
281da177e4SLinus Torvalds
291da177e4SLinus Torvalds/*
30187a51adSRussell King * Interrupt handling.  Preserves r7, r8, r9
31187a51adSRussell King */
32187a51adSRussell King	.macro	irq_handler
33f80dff9dSDan Williams	get_irqnr_preamble r5, lr
34187a51adSRussell King1:	get_irqnr_and_base r0, r6, r5, lr
35187a51adSRussell King	movne	r1, sp
36187a51adSRussell King	@
37187a51adSRussell King	@ routine called with r0 = irq number, r1 = struct pt_regs *
38187a51adSRussell King	@
39b86040a5SCatalin Marinas	adrne	lr, BSYM(1b)
40187a51adSRussell King	bne	asm_do_IRQ
41791be9b9SRussell King
42791be9b9SRussell King#ifdef CONFIG_SMP
43791be9b9SRussell King	/*
44791be9b9SRussell King	 * XXX
45791be9b9SRussell King	 *
46791be9b9SRussell King	 * this macro assumes that irqstat (r6) and base (r5) are
47791be9b9SRussell King	 * preserved from get_irqnr_and_base above
48791be9b9SRussell King	 */
49f00ec48fSRussell King	ALT_SMP(test_for_ipi r0, r6, r5, lr)
50f00ec48fSRussell King	ALT_UP_B(9997f)
51791be9b9SRussell King	movne	r0, sp
52b86040a5SCatalin Marinas	adrne	lr, BSYM(1b)
53791be9b9SRussell King	bne	do_IPI
5437ee16aeSRussell King
5537ee16aeSRussell King#ifdef CONFIG_LOCAL_TIMERS
5637ee16aeSRussell King	test_for_ltirq r0, r6, r5, lr
5737ee16aeSRussell King	movne	r0, sp
58b86040a5SCatalin Marinas	adrne	lr, BSYM(1b)
5937ee16aeSRussell King	bne	do_local_timer
6037ee16aeSRussell King#endif
61f00ec48fSRussell King9997:
62791be9b9SRussell King#endif
63791be9b9SRussell King
64187a51adSRussell King	.endm
65187a51adSRussell King
66785d3cd2SNicolas Pitre#ifdef CONFIG_KPROBES
67785d3cd2SNicolas Pitre	.section	.kprobes.text,"ax",%progbits
68785d3cd2SNicolas Pitre#else
69785d3cd2SNicolas Pitre	.text
70785d3cd2SNicolas Pitre#endif
71785d3cd2SNicolas Pitre
72187a51adSRussell King/*
731da177e4SLinus Torvalds * Invalid mode handlers
741da177e4SLinus Torvalds */
75ccea7a19SRussell King	.macro	inv_entry, reason
76ccea7a19SRussell King	sub	sp, sp, #S_FRAME_SIZE
77b86040a5SCatalin Marinas ARM(	stmib	sp, {r1 - lr}		)
78b86040a5SCatalin Marinas THUMB(	stmia	sp, {r0 - r12}		)
79b86040a5SCatalin Marinas THUMB(	str	sp, [sp, #S_SP]		)
80b86040a5SCatalin Marinas THUMB(	str	lr, [sp, #S_LR]		)
811da177e4SLinus Torvalds	mov	r1, #\reason
821da177e4SLinus Torvalds	.endm
831da177e4SLinus Torvalds
841da177e4SLinus Torvalds__pabt_invalid:
85ccea7a19SRussell King	inv_entry BAD_PREFETCH
86ccea7a19SRussell King	b	common_invalid
8793ed3970SCatalin MarinasENDPROC(__pabt_invalid)
881da177e4SLinus Torvalds
891da177e4SLinus Torvalds__dabt_invalid:
90ccea7a19SRussell King	inv_entry BAD_DATA
91ccea7a19SRussell King	b	common_invalid
9293ed3970SCatalin MarinasENDPROC(__dabt_invalid)
931da177e4SLinus Torvalds
941da177e4SLinus Torvalds__irq_invalid:
95ccea7a19SRussell King	inv_entry BAD_IRQ
96ccea7a19SRussell King	b	common_invalid
9793ed3970SCatalin MarinasENDPROC(__irq_invalid)
981da177e4SLinus Torvalds
991da177e4SLinus Torvalds__und_invalid:
100ccea7a19SRussell King	inv_entry BAD_UNDEFINSTR
1011da177e4SLinus Torvalds
102ccea7a19SRussell King	@
103ccea7a19SRussell King	@ XXX fall through to common_invalid
104ccea7a19SRussell King	@
105ccea7a19SRussell King
106ccea7a19SRussell King@
107ccea7a19SRussell King@ common_invalid - generic code for failed exception (re-entrant version of handlers)
108ccea7a19SRussell King@
109ccea7a19SRussell Kingcommon_invalid:
110ccea7a19SRussell King	zero_fp
111ccea7a19SRussell King
112ccea7a19SRussell King	ldmia	r0, {r4 - r6}
113ccea7a19SRussell King	add	r0, sp, #S_PC		@ here for interlock avoidance
114ccea7a19SRussell King	mov	r7, #-1			@  ""   ""    ""        ""
115ccea7a19SRussell King	str	r4, [sp]		@ save preserved r0
116ccea7a19SRussell King	stmia	r0, {r5 - r7}		@ lr_<exception>,
117ccea7a19SRussell King					@ cpsr_<exception>, "old_r0"
118ccea7a19SRussell King
1191da177e4SLinus Torvalds	mov	r0, sp
1201da177e4SLinus Torvalds	b	bad_mode
12193ed3970SCatalin MarinasENDPROC(__und_invalid)
1221da177e4SLinus Torvalds
1231da177e4SLinus Torvalds/*
1241da177e4SLinus Torvalds * SVC mode handlers
1251da177e4SLinus Torvalds */
1262dede2d8SNicolas Pitre
1272dede2d8SNicolas Pitre#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
1282dede2d8SNicolas Pitre#define SPFIX(code...) code
1292dede2d8SNicolas Pitre#else
1302dede2d8SNicolas Pitre#define SPFIX(code...)
1312dede2d8SNicolas Pitre#endif
1322dede2d8SNicolas Pitre
133d30a0c8bSNicolas Pitre	.macro	svc_entry, stack_hole=0
134c4c5716eSCatalin Marinas UNWIND(.fnstart		)
135c4c5716eSCatalin Marinas UNWIND(.save {r0 - pc}		)
136b86040a5SCatalin Marinas	sub	sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
137b86040a5SCatalin Marinas#ifdef CONFIG_THUMB2_KERNEL
138b86040a5SCatalin Marinas SPFIX(	str	r0, [sp]	)	@ temporarily saved
139b86040a5SCatalin Marinas SPFIX(	mov	r0, sp		)
140b86040a5SCatalin Marinas SPFIX(	tst	r0, #4		)	@ test original stack alignment
141b86040a5SCatalin Marinas SPFIX(	ldr	r0, [sp]	)	@ restored
142b86040a5SCatalin Marinas#else
1432dede2d8SNicolas Pitre SPFIX(	tst	sp, #4		)
144b86040a5SCatalin Marinas#endif
145b86040a5SCatalin Marinas SPFIX(	subeq	sp, sp, #4	)
146b86040a5SCatalin Marinas	stmia	sp, {r1 - r12}
147ccea7a19SRussell King
148ccea7a19SRussell King	ldmia	r0, {r1 - r3}
149b86040a5SCatalin Marinas	add	r5, sp, #S_SP - 4	@ here for interlock avoidance
150ccea7a19SRussell King	mov	r4, #-1			@  ""  ""      ""       ""
151b86040a5SCatalin Marinas	add	r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
152b86040a5SCatalin Marinas SPFIX(	addeq	r0, r0, #4	)
153b86040a5SCatalin Marinas	str	r1, [sp, #-4]!		@ save the "real" r0 copied
154ccea7a19SRussell King					@ from the exception stack
155ccea7a19SRussell King
1561da177e4SLinus Torvalds	mov	r1, lr
1571da177e4SLinus Torvalds
1581da177e4SLinus Torvalds	@
1591da177e4SLinus Torvalds	@ We are now ready to fill in the remaining blanks on the stack:
1601da177e4SLinus Torvalds	@
1611da177e4SLinus Torvalds	@  r0 - sp_svc
1621da177e4SLinus Torvalds	@  r1 - lr_svc
1631da177e4SLinus Torvalds	@  r2 - lr_<exception>, already fixed up for correct return/restart
1641da177e4SLinus Torvalds	@  r3 - spsr_<exception>
1651da177e4SLinus Torvalds	@  r4 - orig_r0 (see pt_regs definition in ptrace.h)
1661da177e4SLinus Torvalds	@
1671da177e4SLinus Torvalds	stmia	r5, {r0 - r4}
1681da177e4SLinus Torvalds	.endm
1691da177e4SLinus Torvalds
1701da177e4SLinus Torvalds	.align	5
1711da177e4SLinus Torvalds__dabt_svc:
172ccea7a19SRussell King	svc_entry
1731da177e4SLinus Torvalds
1741da177e4SLinus Torvalds	@
1751da177e4SLinus Torvalds	@ get ready to re-enable interrupts if appropriate
1761da177e4SLinus Torvalds	@
1771da177e4SLinus Torvalds	mrs	r9, cpsr
1781da177e4SLinus Torvalds	tst	r3, #PSR_I_BIT
1791da177e4SLinus Torvalds	biceq	r9, r9, #PSR_I_BIT
1801da177e4SLinus Torvalds
1811da177e4SLinus Torvalds	@
1821da177e4SLinus Torvalds	@ Call the processor-specific abort handler:
1831da177e4SLinus Torvalds	@
1841da177e4SLinus Torvalds	@  r2 - aborted context pc
1851da177e4SLinus Torvalds	@  r3 - aborted context cpsr
1861da177e4SLinus Torvalds	@
1871da177e4SLinus Torvalds	@ The abort handler must return the aborted address in r0, and
1881da177e4SLinus Torvalds	@ the fault status register in r1.  r9 must be preserved.
1891da177e4SLinus Torvalds	@
19048d7927bSPaul Brook#ifdef MULTI_DABORT
1911da177e4SLinus Torvalds	ldr	r4, .LCprocfns
1921da177e4SLinus Torvalds	mov	lr, pc
19348d7927bSPaul Brook	ldr	pc, [r4, #PROCESSOR_DABT_FUNC]
1941da177e4SLinus Torvalds#else
19548d7927bSPaul Brook	bl	CPU_DABORT_HANDLER
1961da177e4SLinus Torvalds#endif
1971da177e4SLinus Torvalds
1981da177e4SLinus Torvalds	@
1991da177e4SLinus Torvalds	@ set desired IRQ state, then call main handler
2001da177e4SLinus Torvalds	@
201*7e202696SWill Deacon	debug_entry r1
2021da177e4SLinus Torvalds	msr	cpsr_c, r9
2031da177e4SLinus Torvalds	mov	r2, sp
2041da177e4SLinus Torvalds	bl	do_DataAbort
2051da177e4SLinus Torvalds
2061da177e4SLinus Torvalds	@
2071da177e4SLinus Torvalds	@ IRQs off again before pulling preserved data off the stack
2081da177e4SLinus Torvalds	@
209ac78884eSRussell King	disable_irq_notrace
2101da177e4SLinus Torvalds
2111da177e4SLinus Torvalds	@
2121da177e4SLinus Torvalds	@ restore SPSR and restart the instruction
2131da177e4SLinus Torvalds	@
214b86040a5SCatalin Marinas	ldr	r2, [sp, #S_PSR]
215b86040a5SCatalin Marinas	svc_exit r2				@ return from exception
216c4c5716eSCatalin Marinas UNWIND(.fnend		)
21793ed3970SCatalin MarinasENDPROC(__dabt_svc)
2181da177e4SLinus Torvalds
2191da177e4SLinus Torvalds	.align	5
2201da177e4SLinus Torvalds__irq_svc:
221ccea7a19SRussell King	svc_entry
222ccea7a19SRussell King
223ac78884eSRussell King#ifdef CONFIG_TRACE_IRQFLAGS
224ac78884eSRussell King	bl	trace_hardirqs_off
225ac78884eSRussell King#endif
2261da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT
227706fdd9fSRussell King	get_thread_info tsk
228706fdd9fSRussell King	ldr	r8, [tsk, #TI_PREEMPT]		@ get preempt count
229706fdd9fSRussell King	add	r7, r8, #1			@ increment it
230706fdd9fSRussell King	str	r7, [tsk, #TI_PREEMPT]
2311da177e4SLinus Torvalds#endif
232ccea7a19SRussell King
233187a51adSRussell King	irq_handler
2341da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT
23528fab1a2SRussell King	str	r8, [tsk, #TI_PREEMPT]		@ restore preempt count
236706fdd9fSRussell King	ldr	r0, [tsk, #TI_FLAGS]		@ get flags
23728fab1a2SRussell King	teq	r8, #0				@ if preempt count != 0
23828fab1a2SRussell King	movne	r0, #0				@ force flags to 0
2391da177e4SLinus Torvalds	tst	r0, #_TIF_NEED_RESCHED
2401da177e4SLinus Torvalds	blne	svc_preempt
2411da177e4SLinus Torvalds#endif
242b86040a5SCatalin Marinas	ldr	r4, [sp, #S_PSR]		@ irqs are already disabled
2437ad1bcb2SRussell King#ifdef CONFIG_TRACE_IRQFLAGS
244b86040a5SCatalin Marinas	tst	r4, #PSR_I_BIT
2457ad1bcb2SRussell King	bleq	trace_hardirqs_on
2467ad1bcb2SRussell King#endif
247b86040a5SCatalin Marinas	svc_exit r4				@ return from exception
248c4c5716eSCatalin Marinas UNWIND(.fnend		)
24993ed3970SCatalin MarinasENDPROC(__irq_svc)
2501da177e4SLinus Torvalds
2511da177e4SLinus Torvalds	.ltorg
2521da177e4SLinus Torvalds
2531da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT
2541da177e4SLinus Torvaldssvc_preempt:
25528fab1a2SRussell King	mov	r8, lr
2561da177e4SLinus Torvalds1:	bl	preempt_schedule_irq		@ irq en/disable is done inside
257706fdd9fSRussell King	ldr	r0, [tsk, #TI_FLAGS]		@ get new tasks TI_FLAGS
2581da177e4SLinus Torvalds	tst	r0, #_TIF_NEED_RESCHED
25928fab1a2SRussell King	moveq	pc, r8				@ go again
2601da177e4SLinus Torvalds	b	1b
2611da177e4SLinus Torvalds#endif
2621da177e4SLinus Torvalds
2631da177e4SLinus Torvalds	.align	5
2641da177e4SLinus Torvalds__und_svc:
265d30a0c8bSNicolas Pitre#ifdef CONFIG_KPROBES
266d30a0c8bSNicolas Pitre	@ If a kprobe is about to simulate a "stmdb sp..." instruction,
267d30a0c8bSNicolas Pitre	@ it obviously needs free stack space which then will belong to
268d30a0c8bSNicolas Pitre	@ the saved context.
269d30a0c8bSNicolas Pitre	svc_entry 64
270d30a0c8bSNicolas Pitre#else
271ccea7a19SRussell King	svc_entry
272d30a0c8bSNicolas Pitre#endif
2731da177e4SLinus Torvalds
2741da177e4SLinus Torvalds	@
2751da177e4SLinus Torvalds	@ call emulation code, which returns using r9 if it has emulated
2761da177e4SLinus Torvalds	@ the instruction, or the more conventional lr if we are to treat
2771da177e4SLinus Torvalds	@ this as a real undefined instruction
2781da177e4SLinus Torvalds	@
2791da177e4SLinus Torvalds	@  r0 - instruction
2801da177e4SLinus Torvalds	@
28183e686eaSCatalin Marinas#ifndef	CONFIG_THUMB2_KERNEL
2821da177e4SLinus Torvalds	ldr	r0, [r2, #-4]
28383e686eaSCatalin Marinas#else
28483e686eaSCatalin Marinas	ldrh	r0, [r2, #-2]			@ Thumb instruction at LR - 2
28583e686eaSCatalin Marinas	and	r9, r0, #0xf800
28683e686eaSCatalin Marinas	cmp	r9, #0xe800			@ 32-bit instruction if xx >= 0
28783e686eaSCatalin Marinas	ldrhhs	r9, [r2]			@ bottom 16 bits
28883e686eaSCatalin Marinas	orrhs	r0, r9, r0, lsl #16
28983e686eaSCatalin Marinas#endif
290b86040a5SCatalin Marinas	adr	r9, BSYM(1f)
2911da177e4SLinus Torvalds	bl	call_fpe
2921da177e4SLinus Torvalds
2931da177e4SLinus Torvalds	mov	r0, sp				@ struct pt_regs *regs
2941da177e4SLinus Torvalds	bl	do_undefinstr
2951da177e4SLinus Torvalds
2961da177e4SLinus Torvalds	@
2971da177e4SLinus Torvalds	@ IRQs off again before pulling preserved data off the stack
2981da177e4SLinus Torvalds	@
299ac78884eSRussell King1:	disable_irq_notrace
3001da177e4SLinus Torvalds
3011da177e4SLinus Torvalds	@
3021da177e4SLinus Torvalds	@ restore SPSR and restart the instruction
3031da177e4SLinus Torvalds	@
304b86040a5SCatalin Marinas	ldr	r2, [sp, #S_PSR]		@ Get SVC cpsr
305b86040a5SCatalin Marinas	svc_exit r2				@ return from exception
306c4c5716eSCatalin Marinas UNWIND(.fnend		)
30793ed3970SCatalin MarinasENDPROC(__und_svc)
3081da177e4SLinus Torvalds
3091da177e4SLinus Torvalds	.align	5
3101da177e4SLinus Torvalds__pabt_svc:
311ccea7a19SRussell King	svc_entry
3121da177e4SLinus Torvalds
3131da177e4SLinus Torvalds	@
3141da177e4SLinus Torvalds	@ re-enable interrupts if appropriate
3151da177e4SLinus Torvalds	@
3161da177e4SLinus Torvalds	mrs	r9, cpsr
3171da177e4SLinus Torvalds	tst	r3, #PSR_I_BIT
3181da177e4SLinus Torvalds	biceq	r9, r9, #PSR_I_BIT
3191da177e4SLinus Torvalds
32048d7927bSPaul Brook	mov	r0, r2			@ pass address of aborted instruction.
3214fb28474SKirill A. Shutemov#ifdef MULTI_PABORT
32248d7927bSPaul Brook	ldr	r4, .LCprocfns
32348d7927bSPaul Brook	mov	lr, pc
32448d7927bSPaul Brook	ldr	pc, [r4, #PROCESSOR_PABT_FUNC]
32548d7927bSPaul Brook#else
3264fb28474SKirill A. Shutemov	bl	CPU_PABORT_HANDLER
32748d7927bSPaul Brook#endif
328*7e202696SWill Deacon	debug_entry r1
32948d7927bSPaul Brook	msr	cpsr_c, r9			@ Maybe enable interrupts
3304fb28474SKirill A. Shutemov	mov	r2, sp				@ regs
3311da177e4SLinus Torvalds	bl	do_PrefetchAbort		@ call abort handler
3321da177e4SLinus Torvalds
3331da177e4SLinus Torvalds	@
3341da177e4SLinus Torvalds	@ IRQs off again before pulling preserved data off the stack
3351da177e4SLinus Torvalds	@
336ac78884eSRussell King	disable_irq_notrace
3371da177e4SLinus Torvalds
3381da177e4SLinus Torvalds	@
3391da177e4SLinus Torvalds	@ restore SPSR and restart the instruction
3401da177e4SLinus Torvalds	@
341b86040a5SCatalin Marinas	ldr	r2, [sp, #S_PSR]
342b86040a5SCatalin Marinas	svc_exit r2				@ return from exception
343c4c5716eSCatalin Marinas UNWIND(.fnend		)
34493ed3970SCatalin MarinasENDPROC(__pabt_svc)
3451da177e4SLinus Torvalds
3461da177e4SLinus Torvalds	.align	5
34749f680eaSRussell King.LCcralign:
34849f680eaSRussell King	.word	cr_alignment
34948d7927bSPaul Brook#ifdef MULTI_DABORT
3501da177e4SLinus Torvalds.LCprocfns:
3511da177e4SLinus Torvalds	.word	processor
3521da177e4SLinus Torvalds#endif
3531da177e4SLinus Torvalds.LCfp:
3541da177e4SLinus Torvalds	.word	fp_enter
3551da177e4SLinus Torvalds
3561da177e4SLinus Torvalds/*
3571da177e4SLinus Torvalds * User mode handlers
3582dede2d8SNicolas Pitre *
3592dede2d8SNicolas Pitre * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
3601da177e4SLinus Torvalds */
3612dede2d8SNicolas Pitre
3622dede2d8SNicolas Pitre#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
3632dede2d8SNicolas Pitre#error "sizeof(struct pt_regs) must be a multiple of 8"
3642dede2d8SNicolas Pitre#endif
3652dede2d8SNicolas Pitre
366ccea7a19SRussell King	.macro	usr_entry
367c4c5716eSCatalin Marinas UNWIND(.fnstart	)
368c4c5716eSCatalin Marinas UNWIND(.cantunwind	)	@ don't unwind the user space
369ccea7a19SRussell King	sub	sp, sp, #S_FRAME_SIZE
370b86040a5SCatalin Marinas ARM(	stmib	sp, {r1 - r12}	)
371b86040a5SCatalin Marinas THUMB(	stmia	sp, {r0 - r12}	)
372ccea7a19SRussell King
373ccea7a19SRussell King	ldmia	r0, {r1 - r3}
374ccea7a19SRussell King	add	r0, sp, #S_PC		@ here for interlock avoidance
375ccea7a19SRussell King	mov	r4, #-1			@  ""  ""     ""        ""
376ccea7a19SRussell King
377ccea7a19SRussell King	str	r1, [sp]		@ save the "real" r0 copied
378ccea7a19SRussell King					@ from the exception stack
3791da177e4SLinus Torvalds
3801da177e4SLinus Torvalds	@
3811da177e4SLinus Torvalds	@ We are now ready to fill in the remaining blanks on the stack:
3821da177e4SLinus Torvalds	@
3831da177e4SLinus Torvalds	@  r2 - lr_<exception>, already fixed up for correct return/restart
3841da177e4SLinus Torvalds	@  r3 - spsr_<exception>
3851da177e4SLinus Torvalds	@  r4 - orig_r0 (see pt_regs definition in ptrace.h)
3861da177e4SLinus Torvalds	@
3871da177e4SLinus Torvalds	@ Also, separately save sp_usr and lr_usr
3881da177e4SLinus Torvalds	@
389ccea7a19SRussell King	stmia	r0, {r2 - r4}
390b86040a5SCatalin Marinas ARM(	stmdb	r0, {sp, lr}^			)
391b86040a5SCatalin Marinas THUMB(	store_user_sp_lr r0, r1, S_SP - S_PC	)
3921da177e4SLinus Torvalds
3931da177e4SLinus Torvalds	@
3941da177e4SLinus Torvalds	@ Enable the alignment trap while in kernel mode
3951da177e4SLinus Torvalds	@
39649f680eaSRussell King	alignment_trap r0
3971da177e4SLinus Torvalds
3981da177e4SLinus Torvalds	@
3991da177e4SLinus Torvalds	@ Clear FP to mark the first stack frame
4001da177e4SLinus Torvalds	@
4011da177e4SLinus Torvalds	zero_fp
4021da177e4SLinus Torvalds	.endm
4031da177e4SLinus Torvalds
404b49c0f24SNicolas Pitre	.macro	kuser_cmpxchg_check
405b49c0f24SNicolas Pitre#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
406b49c0f24SNicolas Pitre#ifndef CONFIG_MMU
407b49c0f24SNicolas Pitre#warning "NPTL on non MMU needs fixing"
408b49c0f24SNicolas Pitre#else
409b49c0f24SNicolas Pitre	@ Make sure our user space atomic helper is restarted
410b49c0f24SNicolas Pitre	@ if it was interrupted in a critical region.  Here we
411b49c0f24SNicolas Pitre	@ perform a quick test inline since it should be false
412b49c0f24SNicolas Pitre	@ 99.9999% of the time.  The rest is done out of line.
413b49c0f24SNicolas Pitre	cmp	r2, #TASK_SIZE
414b49c0f24SNicolas Pitre	blhs	kuser_cmpxchg_fixup
415b49c0f24SNicolas Pitre#endif
416b49c0f24SNicolas Pitre#endif
417b49c0f24SNicolas Pitre	.endm
418b49c0f24SNicolas Pitre
4191da177e4SLinus Torvalds	.align	5
4201da177e4SLinus Torvalds__dabt_usr:
421ccea7a19SRussell King	usr_entry
422b49c0f24SNicolas Pitre	kuser_cmpxchg_check
4231da177e4SLinus Torvalds
4241da177e4SLinus Torvalds	@
4251da177e4SLinus Torvalds	@ Call the processor-specific abort handler:
4261da177e4SLinus Torvalds	@
4271da177e4SLinus Torvalds	@  r2 - aborted context pc
4281da177e4SLinus Torvalds	@  r3 - aborted context cpsr
4291da177e4SLinus Torvalds	@
4301da177e4SLinus Torvalds	@ The abort handler must return the aborted address in r0, and
4311da177e4SLinus Torvalds	@ the fault status register in r1.
4321da177e4SLinus Torvalds	@
43348d7927bSPaul Brook#ifdef MULTI_DABORT
4341da177e4SLinus Torvalds	ldr	r4, .LCprocfns
4351da177e4SLinus Torvalds	mov	lr, pc
43648d7927bSPaul Brook	ldr	pc, [r4, #PROCESSOR_DABT_FUNC]
4371da177e4SLinus Torvalds#else
43848d7927bSPaul Brook	bl	CPU_DABORT_HANDLER
4391da177e4SLinus Torvalds#endif
4401da177e4SLinus Torvalds
4411da177e4SLinus Torvalds	@
4421da177e4SLinus Torvalds	@ IRQs on, then call the main handler
4431da177e4SLinus Torvalds	@
444*7e202696SWill Deacon	debug_entry r1
4451ec42c0cSRussell King	enable_irq
4461da177e4SLinus Torvalds	mov	r2, sp
447b86040a5SCatalin Marinas	adr	lr, BSYM(ret_from_exception)
4481da177e4SLinus Torvalds	b	do_DataAbort
449c4c5716eSCatalin Marinas UNWIND(.fnend		)
45093ed3970SCatalin MarinasENDPROC(__dabt_usr)
4511da177e4SLinus Torvalds
4521da177e4SLinus Torvalds	.align	5
4531da177e4SLinus Torvalds__irq_usr:
454ccea7a19SRussell King	usr_entry
455b49c0f24SNicolas Pitre	kuser_cmpxchg_check
4561da177e4SLinus Torvalds
4571da177e4SLinus Torvalds	get_thread_info tsk
4581da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT
459706fdd9fSRussell King	ldr	r8, [tsk, #TI_PREEMPT]		@ get preempt count
460706fdd9fSRussell King	add	r7, r8, #1			@ increment it
461706fdd9fSRussell King	str	r7, [tsk, #TI_PREEMPT]
4621da177e4SLinus Torvalds#endif
463ccea7a19SRussell King
464187a51adSRussell King	irq_handler
4651da177e4SLinus Torvalds#ifdef CONFIG_PREEMPT
466706fdd9fSRussell King	ldr	r0, [tsk, #TI_PREEMPT]
467706fdd9fSRussell King	str	r8, [tsk, #TI_PREEMPT]
4681da177e4SLinus Torvalds	teq	r0, r7
469b86040a5SCatalin Marinas ARM(	strne	r0, [r0, -r0]	)
470b86040a5SCatalin Marinas THUMB(	movne	r0, #0		)
471b86040a5SCatalin Marinas THUMB(	strne	r0, [r0]	)
4721da177e4SLinus Torvalds#endif
473ccea7a19SRussell King
4741da177e4SLinus Torvalds	mov	why, #0
4751da177e4SLinus Torvalds	b	ret_to_user
476c4c5716eSCatalin Marinas UNWIND(.fnend		)
47793ed3970SCatalin MarinasENDPROC(__irq_usr)
4781da177e4SLinus Torvalds
4791da177e4SLinus Torvalds	.ltorg
4801da177e4SLinus Torvalds
4811da177e4SLinus Torvalds	.align	5
4821da177e4SLinus Torvalds__und_usr:
483ccea7a19SRussell King	usr_entry
4841da177e4SLinus Torvalds
4851da177e4SLinus Torvalds	@
4861da177e4SLinus Torvalds	@ fall through to the emulation code, which returns using r9 if
4871da177e4SLinus Torvalds	@ it has emulated the instruction, or the more conventional lr
4881da177e4SLinus Torvalds	@ if we are to treat this as a real undefined instruction
4891da177e4SLinus Torvalds	@
4901da177e4SLinus Torvalds	@  r0 - instruction
4911da177e4SLinus Torvalds	@
492b86040a5SCatalin Marinas	adr	r9, BSYM(ret_from_exception)
493b86040a5SCatalin Marinas	adr	lr, BSYM(__und_usr_unknown)
494cb170a45SPaul Brook	tst	r3, #PSR_T_BIT			@ Thumb mode?
495b86040a5SCatalin Marinas	itet	eq				@ explicit IT needed for the 1f label
496cb170a45SPaul Brook	subeq	r4, r2, #4			@ ARM instr at LR - 4
497cb170a45SPaul Brook	subne	r4, r2, #2			@ Thumb instr at LR - 2
498cb170a45SPaul Brook1:	ldreqt	r0, [r4]
49926584853SCatalin Marinas#ifdef CONFIG_CPU_ENDIAN_BE8
50026584853SCatalin Marinas	reveq	r0, r0				@ little endian instruction
50126584853SCatalin Marinas#endif
502cb170a45SPaul Brook	beq	call_fpe
503cb170a45SPaul Brook	@ Thumb instruction
504cb170a45SPaul Brook#if __LINUX_ARM_ARCH__ >= 7
505b86040a5SCatalin Marinas2:
506b86040a5SCatalin Marinas ARM(	ldrht	r5, [r4], #2	)
507b86040a5SCatalin Marinas THUMB(	ldrht	r5, [r4]	)
508b86040a5SCatalin Marinas THUMB(	add	r4, r4, #2	)
509cb170a45SPaul Brook	and	r0, r5, #0xf800			@ mask bits 111x x... .... ....
510cb170a45SPaul Brook	cmp	r0, #0xe800			@ 32bit instruction if xx != 0
511cb170a45SPaul Brook	blo	__und_usr_unknown
512cb170a45SPaul Brook3:	ldrht	r0, [r4]
513cb170a45SPaul Brook	add	r2, r2, #2			@ r2 is PC + 2, make it PC + 4
514cb170a45SPaul Brook	orr	r0, r0, r5, lsl #16
515cb170a45SPaul Brook#else
516cb170a45SPaul Brook	b	__und_usr_unknown
517cb170a45SPaul Brook#endif
518c4c5716eSCatalin Marinas UNWIND(.fnend		)
51993ed3970SCatalin MarinasENDPROC(__und_usr)
520cb170a45SPaul Brook
5211da177e4SLinus Torvalds	@
5221da177e4SLinus Torvalds	@ fallthrough to call_fpe
5231da177e4SLinus Torvalds	@
5241da177e4SLinus Torvalds
5251da177e4SLinus Torvalds/*
5261da177e4SLinus Torvalds * The out of line fixup for the ldrt above.
5271da177e4SLinus Torvalds */
5284260415fSRussell King	.pushsection .fixup, "ax"
529cb170a45SPaul Brook4:	mov	pc, r9
5304260415fSRussell King	.popsection
5314260415fSRussell King	.pushsection __ex_table,"a"
532cb170a45SPaul Brook	.long	1b, 4b
533cb170a45SPaul Brook#if __LINUX_ARM_ARCH__ >= 7
534cb170a45SPaul Brook	.long	2b, 4b
535cb170a45SPaul Brook	.long	3b, 4b
536cb170a45SPaul Brook#endif
5374260415fSRussell King	.popsection
5381da177e4SLinus Torvalds
5391da177e4SLinus Torvalds/*
5401da177e4SLinus Torvalds * Check whether the instruction is a co-processor instruction.
5411da177e4SLinus Torvalds * If yes, we need to call the relevant co-processor handler.
5421da177e4SLinus Torvalds *
5431da177e4SLinus Torvalds * Note that we don't do a full check here for the co-processor
5441da177e4SLinus Torvalds * instructions; all instructions with bit 27 set are well
5451da177e4SLinus Torvalds * defined.  The only instructions that should fault are the
5461da177e4SLinus Torvalds * co-processor instructions.  However, we have to watch out
5471da177e4SLinus Torvalds * for the ARM6/ARM7 SWI bug.
5481da177e4SLinus Torvalds *
549b5872db4SCatalin Marinas * NEON is a special case that has to be handled here. Not all
550b5872db4SCatalin Marinas * NEON instructions are co-processor instructions, so we have
551b5872db4SCatalin Marinas * to make a special case of checking for them. Plus, there's
552b5872db4SCatalin Marinas * five groups of them, so we have a table of mask/opcode pairs
553b5872db4SCatalin Marinas * to check against, and if any match then we branch off into the
554b5872db4SCatalin Marinas * NEON handler code.
555b5872db4SCatalin Marinas *
5561da177e4SLinus Torvalds * Emulators may wish to make use of the following registers:
5571da177e4SLinus Torvalds *  r0  = instruction opcode.
5581da177e4SLinus Torvalds *  r2  = PC+4
559db6ccbb6SRussell King *  r9  = normal "successful" return address
5601da177e4SLinus Torvalds *  r10 = this threads thread_info structure.
561db6ccbb6SRussell King *  lr  = unrecognised instruction return address
5621da177e4SLinus Torvalds */
563cb170a45SPaul Brook	@
564cb170a45SPaul Brook	@ Fall-through from Thumb-2 __und_usr
565cb170a45SPaul Brook	@
566cb170a45SPaul Brook#ifdef CONFIG_NEON
567cb170a45SPaul Brook	adr	r6, .LCneon_thumb_opcodes
568cb170a45SPaul Brook	b	2f
569cb170a45SPaul Brook#endif
5701da177e4SLinus Torvaldscall_fpe:
571b5872db4SCatalin Marinas#ifdef CONFIG_NEON
572cb170a45SPaul Brook	adr	r6, .LCneon_arm_opcodes
573b5872db4SCatalin Marinas2:
574b5872db4SCatalin Marinas	ldr	r7, [r6], #4			@ mask value
575b5872db4SCatalin Marinas	cmp	r7, #0				@ end mask?
576b5872db4SCatalin Marinas	beq	1f
577b5872db4SCatalin Marinas	and	r8, r0, r7
578b5872db4SCatalin Marinas	ldr	r7, [r6], #4			@ opcode bits matching in mask
579b5872db4SCatalin Marinas	cmp	r8, r7				@ NEON instruction?
580b5872db4SCatalin Marinas	bne	2b
581b5872db4SCatalin Marinas	get_thread_info r10
582b5872db4SCatalin Marinas	mov	r7, #1
583b5872db4SCatalin Marinas	strb	r7, [r10, #TI_USED_CP + 10]	@ mark CP#10 as used
584b5872db4SCatalin Marinas	strb	r7, [r10, #TI_USED_CP + 11]	@ mark CP#11 as used
585b5872db4SCatalin Marinas	b	do_vfp				@ let VFP handler handle this
586b5872db4SCatalin Marinas1:
587b5872db4SCatalin Marinas#endif
5881da177e4SLinus Torvalds	tst	r0, #0x08000000			@ only CDP/CPRT/LDC/STC have bit 27
589cb170a45SPaul Brook	tstne	r0, #0x04000000			@ bit 26 set on both ARM and Thumb-2
5901da177e4SLinus Torvalds#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
5911da177e4SLinus Torvalds	and	r8, r0, #0x0f000000		@ mask out op-code bits
5921da177e4SLinus Torvalds	teqne	r8, #0x0f000000			@ SWI (ARM6/7 bug)?
5931da177e4SLinus Torvalds#endif
5941da177e4SLinus Torvalds	moveq	pc, lr
5951da177e4SLinus Torvalds	get_thread_info r10			@ get current thread
5961da177e4SLinus Torvalds	and	r8, r0, #0x00000f00		@ mask out CP number
597b86040a5SCatalin Marinas THUMB(	lsr	r8, r8, #8		)
5981da177e4SLinus Torvalds	mov	r7, #1
5991da177e4SLinus Torvalds	add	r6, r10, #TI_USED_CP
600b86040a5SCatalin Marinas ARM(	strb	r7, [r6, r8, lsr #8]	)	@ set appropriate used_cp[]
601b86040a5SCatalin Marinas THUMB(	strb	r7, [r6, r8]		)	@ set appropriate used_cp[]
6021da177e4SLinus Torvalds#ifdef CONFIG_IWMMXT
6031da177e4SLinus Torvalds	@ Test if we need to give access to iWMMXt coprocessors
6041da177e4SLinus Torvalds	ldr	r5, [r10, #TI_FLAGS]
6051da177e4SLinus Torvalds	rsbs	r7, r8, #(1 << 8)		@ CP 0 or 1 only
6061da177e4SLinus Torvalds	movcss	r7, r5, lsr #(TIF_USING_IWMMXT + 1)
6071da177e4SLinus Torvalds	bcs	iwmmxt_task_enable
6081da177e4SLinus Torvalds#endif
609b86040a5SCatalin Marinas ARM(	add	pc, pc, r8, lsr #6	)
610b86040a5SCatalin Marinas THUMB(	lsl	r8, r8, #2		)
611b86040a5SCatalin Marinas THUMB(	add	pc, r8			)
612b86040a5SCatalin Marinas	nop
6131da177e4SLinus Torvalds
614a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#0
615b86040a5SCatalin Marinas	W(b)	do_fpe				@ CP#1 (FPE)
616b86040a5SCatalin Marinas	W(b)	do_fpe				@ CP#2 (FPE)
617a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#3
618c17fad11SLennert Buytenhek#ifdef CONFIG_CRUNCH
619c17fad11SLennert Buytenhek	b	crunch_task_enable		@ CP#4 (MaverickCrunch)
620c17fad11SLennert Buytenhek	b	crunch_task_enable		@ CP#5 (MaverickCrunch)
621c17fad11SLennert Buytenhek	b	crunch_task_enable		@ CP#6 (MaverickCrunch)
622c17fad11SLennert Buytenhek#else
623a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#4
624a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#5
625a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#6
626c17fad11SLennert Buytenhek#endif
627a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#7
628a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#8
629a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#9
6301da177e4SLinus Torvalds#ifdef CONFIG_VFP
631b86040a5SCatalin Marinas	W(b)	do_vfp				@ CP#10 (VFP)
632b86040a5SCatalin Marinas	W(b)	do_vfp				@ CP#11 (VFP)
6331da177e4SLinus Torvalds#else
634a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#10 (VFP)
635a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#11 (VFP)
6361da177e4SLinus Torvalds#endif
637a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#12
638a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#13
639a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#14 (Debug)
640a771fe6eSCatalin Marinas	movw_pc	lr				@ CP#15 (Control)
6411da177e4SLinus Torvalds
642b5872db4SCatalin Marinas#ifdef CONFIG_NEON
643b5872db4SCatalin Marinas	.align	6
644b5872db4SCatalin Marinas
645cb170a45SPaul Brook.LCneon_arm_opcodes:
646b5872db4SCatalin Marinas	.word	0xfe000000			@ mask
647b5872db4SCatalin Marinas	.word	0xf2000000			@ opcode
648b5872db4SCatalin Marinas
649b5872db4SCatalin Marinas	.word	0xff100000			@ mask
650b5872db4SCatalin Marinas	.word	0xf4000000			@ opcode
651b5872db4SCatalin Marinas
652b5872db4SCatalin Marinas	.word	0x00000000			@ mask
653b5872db4SCatalin Marinas	.word	0x00000000			@ opcode
654cb170a45SPaul Brook
655cb170a45SPaul Brook.LCneon_thumb_opcodes:
656cb170a45SPaul Brook	.word	0xef000000			@ mask
657cb170a45SPaul Brook	.word	0xef000000			@ opcode
658cb170a45SPaul Brook
659cb170a45SPaul Brook	.word	0xff100000			@ mask
660cb170a45SPaul Brook	.word	0xf9000000			@ opcode
661cb170a45SPaul Brook
662cb170a45SPaul Brook	.word	0x00000000			@ mask
663cb170a45SPaul Brook	.word	0x00000000			@ opcode
664b5872db4SCatalin Marinas#endif
665b5872db4SCatalin Marinas
6661da177e4SLinus Torvaldsdo_fpe:
6675d25ac03SRussell King	enable_irq
6681da177e4SLinus Torvalds	ldr	r4, .LCfp
6691da177e4SLinus Torvalds	add	r10, r10, #TI_FPSTATE		@ r10 = workspace
6701da177e4SLinus Torvalds	ldr	pc, [r4]			@ Call FP module USR entry point
6711da177e4SLinus Torvalds
6721da177e4SLinus Torvalds/*
6731da177e4SLinus Torvalds * The FP module is called with these registers set:
6741da177e4SLinus Torvalds *  r0  = instruction
6751da177e4SLinus Torvalds *  r2  = PC+4
6761da177e4SLinus Torvalds *  r9  = normal "successful" return address
6771da177e4SLinus Torvalds *  r10 = FP workspace
6781da177e4SLinus Torvalds *  lr  = unrecognised FP instruction return address
6791da177e4SLinus Torvalds */
6801da177e4SLinus Torvalds
681124efc27SSantosh Shilimkar	.pushsection .data
6821da177e4SLinus TorvaldsENTRY(fp_enter)
683db6ccbb6SRussell King	.word	no_fp
684124efc27SSantosh Shilimkar	.popsection
6851da177e4SLinus Torvalds
68683e686eaSCatalin MarinasENTRY(no_fp)
68783e686eaSCatalin Marinas	mov	pc, lr
68883e686eaSCatalin MarinasENDPROC(no_fp)
689db6ccbb6SRussell King
690db6ccbb6SRussell King__und_usr_unknown:
691ecbab71cSRussell King	enable_irq
6921da177e4SLinus Torvalds	mov	r0, sp
693b86040a5SCatalin Marinas	adr	lr, BSYM(ret_from_exception)
6941da177e4SLinus Torvalds	b	do_undefinstr
69593ed3970SCatalin MarinasENDPROC(__und_usr_unknown)
6961da177e4SLinus Torvalds
6971da177e4SLinus Torvalds	.align	5
6981da177e4SLinus Torvalds__pabt_usr:
699ccea7a19SRussell King	usr_entry
7001da177e4SLinus Torvalds
70148d7927bSPaul Brook	mov	r0, r2			@ pass address of aborted instruction.
7024fb28474SKirill A. Shutemov#ifdef MULTI_PABORT
70348d7927bSPaul Brook	ldr	r4, .LCprocfns
70448d7927bSPaul Brook	mov	lr, pc
70548d7927bSPaul Brook	ldr	pc, [r4, #PROCESSOR_PABT_FUNC]
70648d7927bSPaul Brook#else
7074fb28474SKirill A. Shutemov	bl	CPU_PABORT_HANDLER
70848d7927bSPaul Brook#endif
709*7e202696SWill Deacon	debug_entry r1
7101ec42c0cSRussell King	enable_irq				@ Enable interrupts
7114fb28474SKirill A. Shutemov	mov	r2, sp				@ regs
7121da177e4SLinus Torvalds	bl	do_PrefetchAbort		@ call abort handler
713c4c5716eSCatalin Marinas UNWIND(.fnend		)
7141da177e4SLinus Torvalds	/* fall through */
7151da177e4SLinus Torvalds/*
7161da177e4SLinus Torvalds * This is the return code to user mode for abort handlers
7171da177e4SLinus Torvalds */
7181da177e4SLinus TorvaldsENTRY(ret_from_exception)
719c4c5716eSCatalin Marinas UNWIND(.fnstart	)
720c4c5716eSCatalin Marinas UNWIND(.cantunwind	)
7211da177e4SLinus Torvalds	get_thread_info tsk
7221da177e4SLinus Torvalds	mov	why, #0
7231da177e4SLinus Torvalds	b	ret_to_user
724c4c5716eSCatalin Marinas UNWIND(.fnend		)
72593ed3970SCatalin MarinasENDPROC(__pabt_usr)
72693ed3970SCatalin MarinasENDPROC(ret_from_exception)
7271da177e4SLinus Torvalds
7281da177e4SLinus Torvalds/*
7291da177e4SLinus Torvalds * Register switch for ARMv3 and ARMv4 processors
7301da177e4SLinus Torvalds * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
7311da177e4SLinus Torvalds * previous and next are guaranteed not to be the same.
7321da177e4SLinus Torvalds */
7331da177e4SLinus TorvaldsENTRY(__switch_to)
734c4c5716eSCatalin Marinas UNWIND(.fnstart	)
735c4c5716eSCatalin Marinas UNWIND(.cantunwind	)
7361da177e4SLinus Torvalds	add	ip, r1, #TI_CPU_SAVE
7371da177e4SLinus Torvalds	ldr	r3, [r2, #TI_TP_VALUE]
738b86040a5SCatalin Marinas ARM(	stmia	ip!, {r4 - sl, fp, sp, lr} )	@ Store most regs on stack
739b86040a5SCatalin Marinas THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
740b86040a5SCatalin Marinas THUMB(	str	sp, [ip], #4		   )
741b86040a5SCatalin Marinas THUMB(	str	lr, [ip], #4		   )
742d6551e88SRussell King#ifdef CONFIG_MMU
743d6551e88SRussell King	ldr	r6, [r2, #TI_CPU_DOMAIN]
744afeb90caSHyok S. Choi#endif
745f159f4edSTony Lindgren	set_tls	r3, r4, r5
746df0698beSNicolas Pitre#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
747df0698beSNicolas Pitre	ldr	r7, [r2, #TI_TASK]
748df0698beSNicolas Pitre	ldr	r8, =__stack_chk_guard
749df0698beSNicolas Pitre	ldr	r7, [r7, #TSK_STACK_CANARY]
750df0698beSNicolas Pitre#endif
751afeb90caSHyok S. Choi#ifdef CONFIG_MMU
7521da177e4SLinus Torvalds	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
753afeb90caSHyok S. Choi#endif
754d6551e88SRussell King	mov	r5, r0
755d6551e88SRussell King	add	r4, r2, #TI_CPU_SAVE
756d6551e88SRussell King	ldr	r0, =thread_notify_head
757d6551e88SRussell King	mov	r1, #THREAD_NOTIFY_SWITCH
758d6551e88SRussell King	bl	atomic_notifier_call_chain
759df0698beSNicolas Pitre#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
760df0698beSNicolas Pitre	str	r7, [r8]
761df0698beSNicolas Pitre#endif
762b86040a5SCatalin Marinas THUMB(	mov	ip, r4			   )
763d6551e88SRussell King	mov	r0, r5
764b86040a5SCatalin Marinas ARM(	ldmia	r4, {r4 - sl, fp, sp, pc}  )	@ Load all regs saved previously
765b86040a5SCatalin Marinas THUMB(	ldmia	ip!, {r4 - sl, fp}	   )	@ Load all regs saved previously
766b86040a5SCatalin Marinas THUMB(	ldr	sp, [ip], #4		   )
767b86040a5SCatalin Marinas THUMB(	ldr	pc, [ip]		   )
768c4c5716eSCatalin Marinas UNWIND(.fnend		)
76993ed3970SCatalin MarinasENDPROC(__switch_to)
7701da177e4SLinus Torvalds
7711da177e4SLinus Torvalds	__INIT
7722d2669b6SNicolas Pitre
7732d2669b6SNicolas Pitre/*
7742d2669b6SNicolas Pitre * User helpers.
7752d2669b6SNicolas Pitre *
7762d2669b6SNicolas Pitre * These are segment of kernel provided user code reachable from user space
7772d2669b6SNicolas Pitre * at a fixed address in kernel memory.  This is used to provide user space
7782d2669b6SNicolas Pitre * with some operations which require kernel help because of unimplemented
7792d2669b6SNicolas Pitre * native feature and/or instructions in many ARM CPUs. The idea is for
7802d2669b6SNicolas Pitre * this code to be executed directly in user mode for best efficiency but
7812d2669b6SNicolas Pitre * which is too intimate with the kernel counter part to be left to user
7822d2669b6SNicolas Pitre * libraries.  In fact this code might even differ from one CPU to another
7832d2669b6SNicolas Pitre * depending on the available  instruction set and restrictions like on
7842d2669b6SNicolas Pitre * SMP systems.  In other words, the kernel reserves the right to change
7852d2669b6SNicolas Pitre * this code as needed without warning. Only the entry points and their
7862d2669b6SNicolas Pitre * results are guaranteed to be stable.
7872d2669b6SNicolas Pitre *
7882d2669b6SNicolas Pitre * Each segment is 32-byte aligned and will be moved to the top of the high
7892d2669b6SNicolas Pitre * vector page.  New segments (if ever needed) must be added in front of
7902d2669b6SNicolas Pitre * existing ones.  This mechanism should be used only for things that are
7912d2669b6SNicolas Pitre * really small and justified, and not be abused freely.
7922d2669b6SNicolas Pitre *
7932d2669b6SNicolas Pitre * User space is expected to implement those things inline when optimizing
7942d2669b6SNicolas Pitre * for a processor that has the necessary native support, but only if such
7952d2669b6SNicolas Pitre * resulting binaries are already to be incompatible with earlier ARM
7962d2669b6SNicolas Pitre * processors due to the use of unsupported instructions other than what
7972d2669b6SNicolas Pitre * is provided here.  In other words don't make binaries unable to run on
7982d2669b6SNicolas Pitre * earlier processors just for the sake of not using these kernel helpers
7992d2669b6SNicolas Pitre * if your compiled code is not going to use the new instructions for other
8002d2669b6SNicolas Pitre * purpose.
8012d2669b6SNicolas Pitre */
802b86040a5SCatalin Marinas THUMB(	.arm	)
8032d2669b6SNicolas Pitre
804ba9b5d76SNicolas Pitre	.macro	usr_ret, reg
805ba9b5d76SNicolas Pitre#ifdef CONFIG_ARM_THUMB
806ba9b5d76SNicolas Pitre	bx	\reg
807ba9b5d76SNicolas Pitre#else
808ba9b5d76SNicolas Pitre	mov	pc, \reg
809ba9b5d76SNicolas Pitre#endif
810ba9b5d76SNicolas Pitre	.endm
811ba9b5d76SNicolas Pitre
8122d2669b6SNicolas Pitre	.align	5
8132d2669b6SNicolas Pitre	.globl	__kuser_helper_start
8142d2669b6SNicolas Pitre__kuser_helper_start:
8152d2669b6SNicolas Pitre
8162d2669b6SNicolas Pitre/*
8172d2669b6SNicolas Pitre * Reference prototype:
8182d2669b6SNicolas Pitre *
8197c612bfdSNicolas Pitre *	void __kernel_memory_barrier(void)
8207c612bfdSNicolas Pitre *
8217c612bfdSNicolas Pitre * Input:
8227c612bfdSNicolas Pitre *
8237c612bfdSNicolas Pitre *	lr = return address
8247c612bfdSNicolas Pitre *
8257c612bfdSNicolas Pitre * Output:
8267c612bfdSNicolas Pitre *
8277c612bfdSNicolas Pitre *	none
8287c612bfdSNicolas Pitre *
8297c612bfdSNicolas Pitre * Clobbered:
8307c612bfdSNicolas Pitre *
831b49c0f24SNicolas Pitre *	none
8327c612bfdSNicolas Pitre *
8337c612bfdSNicolas Pitre * Definition and user space usage example:
8347c612bfdSNicolas Pitre *
8357c612bfdSNicolas Pitre *	typedef void (__kernel_dmb_t)(void);
8367c612bfdSNicolas Pitre *	#define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
8377c612bfdSNicolas Pitre *
8387c612bfdSNicolas Pitre * Apply any needed memory barrier to preserve consistency with data modified
8397c612bfdSNicolas Pitre * manually and __kuser_cmpxchg usage.
8407c612bfdSNicolas Pitre *
8417c612bfdSNicolas Pitre * This could be used as follows:
8427c612bfdSNicolas Pitre *
8437c612bfdSNicolas Pitre * #define __kernel_dmb() \
8447c612bfdSNicolas Pitre *         asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
8456896eec0SPaul Brook *	        : : : "r0", "lr","cc" )
8467c612bfdSNicolas Pitre */
8477c612bfdSNicolas Pitre
8487c612bfdSNicolas Pitre__kuser_memory_barrier:				@ 0xffff0fa0
849bac4e960SRussell King	smp_dmb
850ba9b5d76SNicolas Pitre	usr_ret	lr
8517c612bfdSNicolas Pitre
8527c612bfdSNicolas Pitre	.align	5
8537c612bfdSNicolas Pitre
8547c612bfdSNicolas Pitre/*
8557c612bfdSNicolas Pitre * Reference prototype:
8567c612bfdSNicolas Pitre *
8572d2669b6SNicolas Pitre *	int __kernel_cmpxchg(int oldval, int newval, int *ptr)
8582d2669b6SNicolas Pitre *
8592d2669b6SNicolas Pitre * Input:
8602d2669b6SNicolas Pitre *
8612d2669b6SNicolas Pitre *	r0 = oldval
8622d2669b6SNicolas Pitre *	r1 = newval
8632d2669b6SNicolas Pitre *	r2 = ptr
8642d2669b6SNicolas Pitre *	lr = return address
8652d2669b6SNicolas Pitre *
8662d2669b6SNicolas Pitre * Output:
8672d2669b6SNicolas Pitre *
8682d2669b6SNicolas Pitre *	r0 = returned value (zero or non-zero)
8692d2669b6SNicolas Pitre *	C flag = set if r0 == 0, clear if r0 != 0
8702d2669b6SNicolas Pitre *
8712d2669b6SNicolas Pitre * Clobbered:
8722d2669b6SNicolas Pitre *
8732d2669b6SNicolas Pitre *	r3, ip, flags
8742d2669b6SNicolas Pitre *
8752d2669b6SNicolas Pitre * Definition and user space usage example:
8762d2669b6SNicolas Pitre *
8772d2669b6SNicolas Pitre *	typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
8782d2669b6SNicolas Pitre *	#define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
8792d2669b6SNicolas Pitre *
8802d2669b6SNicolas Pitre * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
8812d2669b6SNicolas Pitre * Return zero if *ptr was changed or non-zero if no exchange happened.
8822d2669b6SNicolas Pitre * The C flag is also set if *ptr was changed to allow for assembly
8832d2669b6SNicolas Pitre * optimization in the calling code.
8842d2669b6SNicolas Pitre *
8855964eae8SNicolas Pitre * Notes:
8865964eae8SNicolas Pitre *
8875964eae8SNicolas Pitre *    - This routine already includes memory barriers as needed.
8885964eae8SNicolas Pitre *
8892d2669b6SNicolas Pitre * For example, a user space atomic_add implementation could look like this:
8902d2669b6SNicolas Pitre *
8912d2669b6SNicolas Pitre * #define atomic_add(ptr, val) \
8922d2669b6SNicolas Pitre *	({ register unsigned int *__ptr asm("r2") = (ptr); \
8932d2669b6SNicolas Pitre *	   register unsigned int __result asm("r1"); \
8942d2669b6SNicolas Pitre *	   asm volatile ( \
8952d2669b6SNicolas Pitre *	       "1: @ atomic_add\n\t" \
8962d2669b6SNicolas Pitre *	       "ldr	r0, [r2]\n\t" \
8972d2669b6SNicolas Pitre *	       "mov	r3, #0xffff0fff\n\t" \
8982d2669b6SNicolas Pitre *	       "add	lr, pc, #4\n\t" \
8992d2669b6SNicolas Pitre *	       "add	r1, r0, %2\n\t" \
9002d2669b6SNicolas Pitre *	       "add	pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
9012d2669b6SNicolas Pitre *	       "bcc	1b" \
9022d2669b6SNicolas Pitre *	       : "=&r" (__result) \
9032d2669b6SNicolas Pitre *	       : "r" (__ptr), "rIL" (val) \
9042d2669b6SNicolas Pitre *	       : "r0","r3","ip","lr","cc","memory" ); \
9052d2669b6SNicolas Pitre *	   __result; })
9062d2669b6SNicolas Pitre */
9072d2669b6SNicolas Pitre
9082d2669b6SNicolas Pitre__kuser_cmpxchg:				@ 0xffff0fc0
9092d2669b6SNicolas Pitre
910dcef1f63SNicolas Pitre#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
9112d2669b6SNicolas Pitre
912dcef1f63SNicolas Pitre	/*
913dcef1f63SNicolas Pitre	 * Poor you.  No fast solution possible...
914dcef1f63SNicolas Pitre	 * The kernel itself must perform the operation.
915dcef1f63SNicolas Pitre	 * A special ghost syscall is used for that (see traps.c).
916dcef1f63SNicolas Pitre	 */
9175e097445SNicolas Pitre	stmfd	sp!, {r7, lr}
918cc20d429SRussell King	ldr	r7, =1f			@ it's 20 bits
919cc20d429SRussell King	swi	__ARM_NR_cmpxchg
9205e097445SNicolas Pitre	ldmfd	sp!, {r7, pc}
921cc20d429SRussell King1:	.word	__ARM_NR_cmpxchg
922dcef1f63SNicolas Pitre
923dcef1f63SNicolas Pitre#elif __LINUX_ARM_ARCH__ < 6
9242d2669b6SNicolas Pitre
92549bca4c2SNicolas Pitre#ifdef CONFIG_MMU
926b49c0f24SNicolas Pitre
927b49c0f24SNicolas Pitre	/*
928b49c0f24SNicolas Pitre	 * The only thing that can break atomicity in this cmpxchg
929b49c0f24SNicolas Pitre	 * implementation is either an IRQ or a data abort exception
930b49c0f24SNicolas Pitre	 * causing another process/thread to be scheduled in the middle
931b49c0f24SNicolas Pitre	 * of the critical sequence.  To prevent this, code is added to
932b49c0f24SNicolas Pitre	 * the IRQ and data abort exception handlers to set the pc back
933b49c0f24SNicolas Pitre	 * to the beginning of the critical section if it is found to be
934b49c0f24SNicolas Pitre	 * within that critical section (see kuser_cmpxchg_fixup).
935b49c0f24SNicolas Pitre	 */
936b49c0f24SNicolas Pitre1:	ldr	r3, [r2]			@ load current val
937b49c0f24SNicolas Pitre	subs	r3, r3, r0			@ compare with oldval
938b49c0f24SNicolas Pitre2:	streq	r1, [r2]			@ store newval if eq
939b49c0f24SNicolas Pitre	rsbs	r0, r3, #0			@ set return val and C flag
940b49c0f24SNicolas Pitre	usr_ret	lr
941b49c0f24SNicolas Pitre
942b49c0f24SNicolas Pitre	.text
943b49c0f24SNicolas Pitrekuser_cmpxchg_fixup:
944b49c0f24SNicolas Pitre	@ Called from kuser_cmpxchg_check macro.
945b49c0f24SNicolas Pitre	@ r2 = address of interrupted insn (must be preserved).
946b49c0f24SNicolas Pitre	@ sp = saved regs. r7 and r8 are clobbered.
947b49c0f24SNicolas Pitre	@ 1b = first critical insn, 2b = last critical insn.
948b49c0f24SNicolas Pitre	@ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
949b49c0f24SNicolas Pitre	mov	r7, #0xffff0fff
950b49c0f24SNicolas Pitre	sub	r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
951b49c0f24SNicolas Pitre	subs	r8, r2, r7
952b49c0f24SNicolas Pitre	rsbcss	r8, r8, #(2b - 1b)
953b49c0f24SNicolas Pitre	strcs	r7, [sp, #S_PC]
954b49c0f24SNicolas Pitre	mov	pc, lr
955b49c0f24SNicolas Pitre	.previous
956b49c0f24SNicolas Pitre
95749bca4c2SNicolas Pitre#else
95849bca4c2SNicolas Pitre#warning "NPTL on non MMU needs fixing"
95949bca4c2SNicolas Pitre	mov	r0, #-1
96049bca4c2SNicolas Pitre	adds	r0, r0, #0
961ba9b5d76SNicolas Pitre	usr_ret	lr
962b49c0f24SNicolas Pitre#endif
9632d2669b6SNicolas Pitre
9642d2669b6SNicolas Pitre#else
9652d2669b6SNicolas Pitre
9667511bce4SRussell King	smp_dmb
967b49c0f24SNicolas Pitre1:	ldrex	r3, [r2]
9682d2669b6SNicolas Pitre	subs	r3, r3, r0
9692d2669b6SNicolas Pitre	strexeq	r3, r1, [r2]
970b49c0f24SNicolas Pitre	teqeq	r3, #1
971b49c0f24SNicolas Pitre	beq	1b
9722d2669b6SNicolas Pitre	rsbs	r0, r3, #0
973b49c0f24SNicolas Pitre	/* beware -- each __kuser slot must be 8 instructions max */
974f00ec48fSRussell King	ALT_SMP(b	__kuser_memory_barrier)
975f00ec48fSRussell King	ALT_UP(usr_ret	lr)
9762d2669b6SNicolas Pitre
9772d2669b6SNicolas Pitre#endif
9782d2669b6SNicolas Pitre
9792d2669b6SNicolas Pitre	.align	5
9802d2669b6SNicolas Pitre
9812d2669b6SNicolas Pitre/*
9822d2669b6SNicolas Pitre * Reference prototype:
9832d2669b6SNicolas Pitre *
9842d2669b6SNicolas Pitre *	int __kernel_get_tls(void)
9852d2669b6SNicolas Pitre *
9862d2669b6SNicolas Pitre * Input:
9872d2669b6SNicolas Pitre *
9882d2669b6SNicolas Pitre *	lr = return address
9892d2669b6SNicolas Pitre *
9902d2669b6SNicolas Pitre * Output:
9912d2669b6SNicolas Pitre *
9922d2669b6SNicolas Pitre *	r0 = TLS value
9932d2669b6SNicolas Pitre *
9942d2669b6SNicolas Pitre * Clobbered:
9952d2669b6SNicolas Pitre *
996b49c0f24SNicolas Pitre *	none
9972d2669b6SNicolas Pitre *
9982d2669b6SNicolas Pitre * Definition and user space usage example:
9992d2669b6SNicolas Pitre *
10002d2669b6SNicolas Pitre *	typedef int (__kernel_get_tls_t)(void);
10012d2669b6SNicolas Pitre *	#define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
10022d2669b6SNicolas Pitre *
10032d2669b6SNicolas Pitre * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
10042d2669b6SNicolas Pitre *
10052d2669b6SNicolas Pitre * This could be used as follows:
10062d2669b6SNicolas Pitre *
10072d2669b6SNicolas Pitre * #define __kernel_get_tls() \
10082d2669b6SNicolas Pitre *	({ register unsigned int __val asm("r0"); \
10092d2669b6SNicolas Pitre *         asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
10102d2669b6SNicolas Pitre *	        : "=r" (__val) : : "lr","cc" ); \
10112d2669b6SNicolas Pitre *	   __val; })
10122d2669b6SNicolas Pitre */
10132d2669b6SNicolas Pitre
10142d2669b6SNicolas Pitre__kuser_get_tls:				@ 0xffff0fe0
1015f159f4edSTony Lindgren	ldr	r0, [pc, #(16 - 8)]	@ read TLS, set in kuser_get_tls_init
1016ba9b5d76SNicolas Pitre	usr_ret	lr
1017f159f4edSTony Lindgren	mrc	p15, 0, r0, c13, c0, 3	@ 0xffff0fe8 hardware TLS code
1018f159f4edSTony Lindgren	.rep	4
1019f159f4edSTony Lindgren	.word	0			@ 0xffff0ff0 software TLS value, then
1020f159f4edSTony Lindgren	.endr				@ pad up to __kuser_helper_version
10212d2669b6SNicolas Pitre
10222d2669b6SNicolas Pitre/*
10232d2669b6SNicolas Pitre * Reference declaration:
10242d2669b6SNicolas Pitre *
10252d2669b6SNicolas Pitre *	extern unsigned int __kernel_helper_version;
10262d2669b6SNicolas Pitre *
10272d2669b6SNicolas Pitre * Definition and user space usage example:
10282d2669b6SNicolas Pitre *
10292d2669b6SNicolas Pitre *	#define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
10302d2669b6SNicolas Pitre *
10312d2669b6SNicolas Pitre * User space may read this to determine the curent number of helpers
10322d2669b6SNicolas Pitre * available.
10332d2669b6SNicolas Pitre */
10342d2669b6SNicolas Pitre
10352d2669b6SNicolas Pitre__kuser_helper_version:				@ 0xffff0ffc
10362d2669b6SNicolas Pitre	.word	((__kuser_helper_end - __kuser_helper_start) >> 5)
10372d2669b6SNicolas Pitre
10382d2669b6SNicolas Pitre	.globl	__kuser_helper_end
10392d2669b6SNicolas Pitre__kuser_helper_end:
10402d2669b6SNicolas Pitre
1041b86040a5SCatalin Marinas THUMB(	.thumb	)
10422d2669b6SNicolas Pitre
10431da177e4SLinus Torvalds/*
10441da177e4SLinus Torvalds * Vector stubs.
10451da177e4SLinus Torvalds *
10467933523dSRussell King * This code is copied to 0xffff0200 so we can use branches in the
10477933523dSRussell King * vectors, rather than ldr's.  Note that this code must not
10487933523dSRussell King * exceed 0x300 bytes.
10491da177e4SLinus Torvalds *
10501da177e4SLinus Torvalds * Common stub entry macro:
10511da177e4SLinus Torvalds *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1052ccea7a19SRussell King *
1053ccea7a19SRussell King * SP points to a minimal amount of processor-private memory, the address
1054ccea7a19SRussell King * of which is copied into r0 for the mode specific abort handler.
10551da177e4SLinus Torvalds */
1056b7ec4795SNicolas Pitre	.macro	vector_stub, name, mode, correction=0
10571da177e4SLinus Torvalds	.align	5
10581da177e4SLinus Torvalds
10591da177e4SLinus Torvaldsvector_\name:
10601da177e4SLinus Torvalds	.if \correction
10611da177e4SLinus Torvalds	sub	lr, lr, #\correction
10621da177e4SLinus Torvalds	.endif
10631da177e4SLinus Torvalds
1064ccea7a19SRussell King	@
1065ccea7a19SRussell King	@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1066ccea7a19SRussell King	@ (parent CPSR)
1067ccea7a19SRussell King	@
1068ccea7a19SRussell King	stmia	sp, {r0, lr}		@ save r0, lr
1069ccea7a19SRussell King	mrs	lr, spsr
1070ccea7a19SRussell King	str	lr, [sp, #8]		@ save spsr
1071ccea7a19SRussell King
1072ccea7a19SRussell King	@
1073ccea7a19SRussell King	@ Prepare for SVC32 mode.  IRQs remain disabled.
1074ccea7a19SRussell King	@
1075ccea7a19SRussell King	mrs	r0, cpsr
1076b86040a5SCatalin Marinas	eor	r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1077ccea7a19SRussell King	msr	spsr_cxsf, r0
1078ccea7a19SRussell King
1079ccea7a19SRussell King	@
1080ccea7a19SRussell King	@ the branch table must immediately follow this code
1081ccea7a19SRussell King	@
1082ccea7a19SRussell King	and	lr, lr, #0x0f
1083b86040a5SCatalin Marinas THUMB(	adr	r0, 1f			)
1084b86040a5SCatalin Marinas THUMB(	ldr	lr, [r0, lr, lsl #2]	)
1085b7ec4795SNicolas Pitre	mov	r0, sp
1086b86040a5SCatalin Marinas ARM(	ldr	lr, [pc, lr, lsl #2]	)
1087ccea7a19SRussell King	movs	pc, lr			@ branch to handler in SVC mode
108893ed3970SCatalin MarinasENDPROC(vector_\name)
108988987ef9SCatalin Marinas
109088987ef9SCatalin Marinas	.align	2
109188987ef9SCatalin Marinas	@ handler addresses follow this label
109288987ef9SCatalin Marinas1:
10931da177e4SLinus Torvalds	.endm
10941da177e4SLinus Torvalds
10957933523dSRussell King	.globl	__stubs_start
10961da177e4SLinus Torvalds__stubs_start:
10971da177e4SLinus Torvalds/*
10981da177e4SLinus Torvalds * Interrupt dispatcher
10991da177e4SLinus Torvalds */
1100b7ec4795SNicolas Pitre	vector_stub	irq, IRQ_MODE, 4
11011da177e4SLinus Torvalds
11021da177e4SLinus Torvalds	.long	__irq_usr			@  0  (USR_26 / USR_32)
11031da177e4SLinus Torvalds	.long	__irq_invalid			@  1  (FIQ_26 / FIQ_32)
11041da177e4SLinus Torvalds	.long	__irq_invalid			@  2  (IRQ_26 / IRQ_32)
11051da177e4SLinus Torvalds	.long	__irq_svc			@  3  (SVC_26 / SVC_32)
11061da177e4SLinus Torvalds	.long	__irq_invalid			@  4
11071da177e4SLinus Torvalds	.long	__irq_invalid			@  5
11081da177e4SLinus Torvalds	.long	__irq_invalid			@  6
11091da177e4SLinus Torvalds	.long	__irq_invalid			@  7
11101da177e4SLinus Torvalds	.long	__irq_invalid			@  8
11111da177e4SLinus Torvalds	.long	__irq_invalid			@  9
11121da177e4SLinus Torvalds	.long	__irq_invalid			@  a
11131da177e4SLinus Torvalds	.long	__irq_invalid			@  b
11141da177e4SLinus Torvalds	.long	__irq_invalid			@  c
11151da177e4SLinus Torvalds	.long	__irq_invalid			@  d
11161da177e4SLinus Torvalds	.long	__irq_invalid			@  e
11171da177e4SLinus Torvalds	.long	__irq_invalid			@  f
11181da177e4SLinus Torvalds
11191da177e4SLinus Torvalds/*
11201da177e4SLinus Torvalds * Data abort dispatcher
11211da177e4SLinus Torvalds * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
11221da177e4SLinus Torvalds */
1123b7ec4795SNicolas Pitre	vector_stub	dabt, ABT_MODE, 8
11241da177e4SLinus Torvalds
11251da177e4SLinus Torvalds	.long	__dabt_usr			@  0  (USR_26 / USR_32)
11261da177e4SLinus Torvalds	.long	__dabt_invalid			@  1  (FIQ_26 / FIQ_32)
11271da177e4SLinus Torvalds	.long	__dabt_invalid			@  2  (IRQ_26 / IRQ_32)
11281da177e4SLinus Torvalds	.long	__dabt_svc			@  3  (SVC_26 / SVC_32)
11291da177e4SLinus Torvalds	.long	__dabt_invalid			@  4
11301da177e4SLinus Torvalds	.long	__dabt_invalid			@  5
11311da177e4SLinus Torvalds	.long	__dabt_invalid			@  6
11321da177e4SLinus Torvalds	.long	__dabt_invalid			@  7
11331da177e4SLinus Torvalds	.long	__dabt_invalid			@  8
11341da177e4SLinus Torvalds	.long	__dabt_invalid			@  9
11351da177e4SLinus Torvalds	.long	__dabt_invalid			@  a
11361da177e4SLinus Torvalds	.long	__dabt_invalid			@  b
11371da177e4SLinus Torvalds	.long	__dabt_invalid			@  c
11381da177e4SLinus Torvalds	.long	__dabt_invalid			@  d
11391da177e4SLinus Torvalds	.long	__dabt_invalid			@  e
11401da177e4SLinus Torvalds	.long	__dabt_invalid			@  f
11411da177e4SLinus Torvalds
11421da177e4SLinus Torvalds/*
11431da177e4SLinus Torvalds * Prefetch abort dispatcher
11441da177e4SLinus Torvalds * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
11451da177e4SLinus Torvalds */
1146b7ec4795SNicolas Pitre	vector_stub	pabt, ABT_MODE, 4
11471da177e4SLinus Torvalds
11481da177e4SLinus Torvalds	.long	__pabt_usr			@  0 (USR_26 / USR_32)
11491da177e4SLinus Torvalds	.long	__pabt_invalid			@  1 (FIQ_26 / FIQ_32)
11501da177e4SLinus Torvalds	.long	__pabt_invalid			@  2 (IRQ_26 / IRQ_32)
11511da177e4SLinus Torvalds	.long	__pabt_svc			@  3 (SVC_26 / SVC_32)
11521da177e4SLinus Torvalds	.long	__pabt_invalid			@  4
11531da177e4SLinus Torvalds	.long	__pabt_invalid			@  5
11541da177e4SLinus Torvalds	.long	__pabt_invalid			@  6
11551da177e4SLinus Torvalds	.long	__pabt_invalid			@  7
11561da177e4SLinus Torvalds	.long	__pabt_invalid			@  8
11571da177e4SLinus Torvalds	.long	__pabt_invalid			@  9
11581da177e4SLinus Torvalds	.long	__pabt_invalid			@  a
11591da177e4SLinus Torvalds	.long	__pabt_invalid			@  b
11601da177e4SLinus Torvalds	.long	__pabt_invalid			@  c
11611da177e4SLinus Torvalds	.long	__pabt_invalid			@  d
11621da177e4SLinus Torvalds	.long	__pabt_invalid			@  e
11631da177e4SLinus Torvalds	.long	__pabt_invalid			@  f
11641da177e4SLinus Torvalds
11651da177e4SLinus Torvalds/*
11661da177e4SLinus Torvalds * Undef instr entry dispatcher
11671da177e4SLinus Torvalds * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
11681da177e4SLinus Torvalds */
1169b7ec4795SNicolas Pitre	vector_stub	und, UND_MODE
11701da177e4SLinus Torvalds
11711da177e4SLinus Torvalds	.long	__und_usr			@  0 (USR_26 / USR_32)
11721da177e4SLinus Torvalds	.long	__und_invalid			@  1 (FIQ_26 / FIQ_32)
11731da177e4SLinus Torvalds	.long	__und_invalid			@  2 (IRQ_26 / IRQ_32)
11741da177e4SLinus Torvalds	.long	__und_svc			@  3 (SVC_26 / SVC_32)
11751da177e4SLinus Torvalds	.long	__und_invalid			@  4
11761da177e4SLinus Torvalds	.long	__und_invalid			@  5
11771da177e4SLinus Torvalds	.long	__und_invalid			@  6
11781da177e4SLinus Torvalds	.long	__und_invalid			@  7
11791da177e4SLinus Torvalds	.long	__und_invalid			@  8
11801da177e4SLinus Torvalds	.long	__und_invalid			@  9
11811da177e4SLinus Torvalds	.long	__und_invalid			@  a
11821da177e4SLinus Torvalds	.long	__und_invalid			@  b
11831da177e4SLinus Torvalds	.long	__und_invalid			@  c
11841da177e4SLinus Torvalds	.long	__und_invalid			@  d
11851da177e4SLinus Torvalds	.long	__und_invalid			@  e
11861da177e4SLinus Torvalds	.long	__und_invalid			@  f
11871da177e4SLinus Torvalds
11881da177e4SLinus Torvalds	.align	5
11891da177e4SLinus Torvalds
11901da177e4SLinus Torvalds/*=============================================================================
11911da177e4SLinus Torvalds * Undefined FIQs
11921da177e4SLinus Torvalds *-----------------------------------------------------------------------------
11931da177e4SLinus Torvalds * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
11941da177e4SLinus Torvalds * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
11951da177e4SLinus Torvalds * Basically to switch modes, we *HAVE* to clobber one register...  brain
11961da177e4SLinus Torvalds * damage alert!  I don't think that we can execute any code in here in any
11971da177e4SLinus Torvalds * other mode than FIQ...  Ok you can switch to another mode, but you can't
11981da177e4SLinus Torvalds * get out of that mode without clobbering one register.
11991da177e4SLinus Torvalds */
12001da177e4SLinus Torvaldsvector_fiq:
12011da177e4SLinus Torvalds	disable_fiq
12021da177e4SLinus Torvalds	subs	pc, lr, #4
12031da177e4SLinus Torvalds
12041da177e4SLinus Torvalds/*=============================================================================
12051da177e4SLinus Torvalds * Address exception handler
12061da177e4SLinus Torvalds *-----------------------------------------------------------------------------
12071da177e4SLinus Torvalds * These aren't too critical.
12081da177e4SLinus Torvalds * (they're not supposed to happen, and won't happen in 32-bit data mode).
12091da177e4SLinus Torvalds */
12101da177e4SLinus Torvalds
12111da177e4SLinus Torvaldsvector_addrexcptn:
12121da177e4SLinus Torvalds	b	vector_addrexcptn
12131da177e4SLinus Torvalds
12141da177e4SLinus Torvalds/*
12151da177e4SLinus Torvalds * We group all the following data together to optimise
12161da177e4SLinus Torvalds * for CPUs with separate I & D caches.
12171da177e4SLinus Torvalds */
12181da177e4SLinus Torvalds	.align	5
12191da177e4SLinus Torvalds
12201da177e4SLinus Torvalds.LCvswi:
12211da177e4SLinus Torvalds	.word	vector_swi
12221da177e4SLinus Torvalds
12237933523dSRussell King	.globl	__stubs_end
12241da177e4SLinus Torvalds__stubs_end:
12251da177e4SLinus Torvalds
12267933523dSRussell King	.equ	stubs_offset, __vectors_start + 0x200 - __stubs_start
12271da177e4SLinus Torvalds
12287933523dSRussell King	.globl	__vectors_start
12297933523dSRussell King__vectors_start:
1230b86040a5SCatalin Marinas ARM(	swi	SYS_ERROR0	)
1231b86040a5SCatalin Marinas THUMB(	svc	#0		)
1232b86040a5SCatalin Marinas THUMB(	nop			)
1233b86040a5SCatalin Marinas	W(b)	vector_und + stubs_offset
1234b86040a5SCatalin Marinas	W(ldr)	pc, .LCvswi + stubs_offset
1235b86040a5SCatalin Marinas	W(b)	vector_pabt + stubs_offset
1236b86040a5SCatalin Marinas	W(b)	vector_dabt + stubs_offset
1237b86040a5SCatalin Marinas	W(b)	vector_addrexcptn + stubs_offset
1238b86040a5SCatalin Marinas	W(b)	vector_irq + stubs_offset
1239b86040a5SCatalin Marinas	W(b)	vector_fiq + stubs_offset
12401da177e4SLinus Torvalds
12417933523dSRussell King	.globl	__vectors_end
12427933523dSRussell King__vectors_end:
12431da177e4SLinus Torvalds
12441da177e4SLinus Torvalds	.data
12451da177e4SLinus Torvalds
12461da177e4SLinus Torvalds	.globl	cr_alignment
12471da177e4SLinus Torvalds	.globl	cr_no_alignment
12481da177e4SLinus Torvaldscr_alignment:
12491da177e4SLinus Torvalds	.space	4
12501da177e4SLinus Torvaldscr_no_alignment:
12511da177e4SLinus Torvalds	.space	4
1252