xref: /openbmc/linux/arch/arm/kernel/devtree.c (revision e44ef891e9e68b6ce7d3fd3bac73b7d5433050ae)
19eb8f674SGrant Likely /*
29eb8f674SGrant Likely  *  linux/arch/arm/kernel/devtree.c
39eb8f674SGrant Likely  *
49eb8f674SGrant Likely  *  Copyright (C) 2009 Canonical Ltd. <jeremy.kerr@canonical.com>
59eb8f674SGrant Likely  *
69eb8f674SGrant Likely  * This program is free software; you can redistribute it and/or modify
79eb8f674SGrant Likely  * it under the terms of the GNU General Public License version 2 as
89eb8f674SGrant Likely  * published by the Free Software Foundation.
99eb8f674SGrant Likely  */
109eb8f674SGrant Likely 
119eb8f674SGrant Likely #include <linux/init.h>
12ecea4ab6SPaul Gortmaker #include <linux/export.h>
139eb8f674SGrant Likely #include <linux/errno.h>
149eb8f674SGrant Likely #include <linux/types.h>
159eb8f674SGrant Likely #include <linux/bootmem.h>
169eb8f674SGrant Likely #include <linux/memblock.h>
179eb8f674SGrant Likely #include <linux/of.h>
189eb8f674SGrant Likely #include <linux/of_fdt.h>
199eb8f674SGrant Likely #include <linux/of_irq.h>
209eb8f674SGrant Likely #include <linux/of_platform.h>
219eb8f674SGrant Likely 
22a0ae0240SLorenzo Pieralisi #include <asm/cputype.h>
239eb8f674SGrant Likely #include <asm/setup.h>
249eb8f674SGrant Likely #include <asm/page.h>
25a0ae0240SLorenzo Pieralisi #include <asm/smp_plat.h>
2693c02ab4SGrant Likely #include <asm/mach/arch.h>
2793c02ab4SGrant Likely #include <asm/mach-types.h>
289eb8f674SGrant Likely 
299eb8f674SGrant Likely void __init early_init_dt_add_memory_arch(u64 base, u64 size)
309eb8f674SGrant Likely {
319eb8f674SGrant Likely 	arm_add_memory(base, size);
329eb8f674SGrant Likely }
339eb8f674SGrant Likely 
349eb8f674SGrant Likely void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
359eb8f674SGrant Likely {
369eb8f674SGrant Likely 	return alloc_bootmem_align(size, align);
379eb8f674SGrant Likely }
389eb8f674SGrant Likely 
3993c02ab4SGrant Likely void __init arm_dt_memblock_reserve(void)
4093c02ab4SGrant Likely {
4193c02ab4SGrant Likely 	u64 *reserve_map, base, size;
4293c02ab4SGrant Likely 
4393c02ab4SGrant Likely 	if (!initial_boot_params)
4493c02ab4SGrant Likely 		return;
4593c02ab4SGrant Likely 
4693c02ab4SGrant Likely 	/* Reserve the dtb region */
4793c02ab4SGrant Likely 	memblock_reserve(virt_to_phys(initial_boot_params),
4893c02ab4SGrant Likely 			 be32_to_cpu(initial_boot_params->totalsize));
4993c02ab4SGrant Likely 
5093c02ab4SGrant Likely 	/*
5193c02ab4SGrant Likely 	 * Process the reserve map.  This will probably overlap the initrd
5293c02ab4SGrant Likely 	 * and dtb locations which are already reserved, but overlaping
5393c02ab4SGrant Likely 	 * doesn't hurt anything
5493c02ab4SGrant Likely 	 */
5593c02ab4SGrant Likely 	reserve_map = ((void*)initial_boot_params) +
5693c02ab4SGrant Likely 			be32_to_cpu(initial_boot_params->off_mem_rsvmap);
5793c02ab4SGrant Likely 	while (1) {
5893c02ab4SGrant Likely 		base = be64_to_cpup(reserve_map++);
5993c02ab4SGrant Likely 		size = be64_to_cpup(reserve_map++);
6093c02ab4SGrant Likely 		if (!size)
6193c02ab4SGrant Likely 			break;
6293c02ab4SGrant Likely 		memblock_reserve(base, size);
6393c02ab4SGrant Likely 	}
6493c02ab4SGrant Likely }
6593c02ab4SGrant Likely 
66a0ae0240SLorenzo Pieralisi /*
67a0ae0240SLorenzo Pieralisi  * arm_dt_init_cpu_maps - Function retrieves cpu nodes from the device tree
68a0ae0240SLorenzo Pieralisi  * and builds the cpu logical map array containing MPIDR values related to
69a0ae0240SLorenzo Pieralisi  * logical cpus
70a0ae0240SLorenzo Pieralisi  *
71a0ae0240SLorenzo Pieralisi  * Updates the cpu possible mask with the number of parsed cpu nodes
72a0ae0240SLorenzo Pieralisi  */
73a0ae0240SLorenzo Pieralisi void __init arm_dt_init_cpu_maps(void)
74a0ae0240SLorenzo Pieralisi {
75a0ae0240SLorenzo Pieralisi 	/*
76a0ae0240SLorenzo Pieralisi 	 * Temp logical map is initialized with UINT_MAX values that are
77a0ae0240SLorenzo Pieralisi 	 * considered invalid logical map entries since the logical map must
78a0ae0240SLorenzo Pieralisi 	 * contain a list of MPIDR[23:0] values where MPIDR[31:24] must
79a0ae0240SLorenzo Pieralisi 	 * read as 0.
80a0ae0240SLorenzo Pieralisi 	 */
81a0ae0240SLorenzo Pieralisi 	struct device_node *cpu, *cpus;
82a0ae0240SLorenzo Pieralisi 	u32 i, j, cpuidx = 1;
83a0ae0240SLorenzo Pieralisi 	u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
84a0ae0240SLorenzo Pieralisi 
8518d7f152SLorenzo Pieralisi 	u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
86a0ae0240SLorenzo Pieralisi 	bool bootcpu_valid = false;
87a0ae0240SLorenzo Pieralisi 	cpus = of_find_node_by_path("/cpus");
88a0ae0240SLorenzo Pieralisi 
89a0ae0240SLorenzo Pieralisi 	if (!cpus)
90a0ae0240SLorenzo Pieralisi 		return;
91a0ae0240SLorenzo Pieralisi 
92a0ae0240SLorenzo Pieralisi 	for_each_child_of_node(cpus, cpu) {
93a0ae0240SLorenzo Pieralisi 		u32 hwid;
94a0ae0240SLorenzo Pieralisi 
951ba9bf0aSLorenzo Pieralisi 		if (of_node_cmp(cpu->type, "cpu"))
961ba9bf0aSLorenzo Pieralisi 			continue;
971ba9bf0aSLorenzo Pieralisi 
98a0ae0240SLorenzo Pieralisi 		pr_debug(" * %s...\n", cpu->full_name);
99a0ae0240SLorenzo Pieralisi 		/*
100a0ae0240SLorenzo Pieralisi 		 * A device tree containing CPU nodes with missing "reg"
101a0ae0240SLorenzo Pieralisi 		 * properties is considered invalid to build the
102a0ae0240SLorenzo Pieralisi 		 * cpu_logical_map.
103a0ae0240SLorenzo Pieralisi 		 */
104a0ae0240SLorenzo Pieralisi 		if (of_property_read_u32(cpu, "reg", &hwid)) {
105a0ae0240SLorenzo Pieralisi 			pr_debug(" * %s missing reg property\n",
106a0ae0240SLorenzo Pieralisi 				     cpu->full_name);
107a0ae0240SLorenzo Pieralisi 			return;
108a0ae0240SLorenzo Pieralisi 		}
109a0ae0240SLorenzo Pieralisi 
110a0ae0240SLorenzo Pieralisi 		/*
111a0ae0240SLorenzo Pieralisi 		 * 8 MSBs must be set to 0 in the DT since the reg property
112a0ae0240SLorenzo Pieralisi 		 * defines the MPIDR[23:0].
113a0ae0240SLorenzo Pieralisi 		 */
114a0ae0240SLorenzo Pieralisi 		if (hwid & ~MPIDR_HWID_BITMASK)
115a0ae0240SLorenzo Pieralisi 			return;
116a0ae0240SLorenzo Pieralisi 
117a0ae0240SLorenzo Pieralisi 		/*
118a0ae0240SLorenzo Pieralisi 		 * Duplicate MPIDRs are a recipe for disaster.
119a0ae0240SLorenzo Pieralisi 		 * Scan all initialized entries and check for
120a0ae0240SLorenzo Pieralisi 		 * duplicates. If any is found just bail out.
121a0ae0240SLorenzo Pieralisi 		 * temp values were initialized to UINT_MAX
122a0ae0240SLorenzo Pieralisi 		 * to avoid matching valid MPIDR[23:0] values.
123a0ae0240SLorenzo Pieralisi 		 */
124a0ae0240SLorenzo Pieralisi 		for (j = 0; j < cpuidx; j++)
125a0ae0240SLorenzo Pieralisi 			if (WARN(tmp_map[j] == hwid, "Duplicate /cpu reg "
126a0ae0240SLorenzo Pieralisi 						     "properties in the DT\n"))
127a0ae0240SLorenzo Pieralisi 				return;
128a0ae0240SLorenzo Pieralisi 
129a0ae0240SLorenzo Pieralisi 		/*
130a0ae0240SLorenzo Pieralisi 		 * Build a stashed array of MPIDR values. Numbering scheme
131a0ae0240SLorenzo Pieralisi 		 * requires that if detected the boot CPU must be assigned
132a0ae0240SLorenzo Pieralisi 		 * logical id 0. Other CPUs get sequential indexes starting
133a0ae0240SLorenzo Pieralisi 		 * from 1. If a CPU node with a reg property matching the
134a0ae0240SLorenzo Pieralisi 		 * boot CPU MPIDR is detected, this is recorded so that the
135a0ae0240SLorenzo Pieralisi 		 * logical map built from DT is validated and can be used
136a0ae0240SLorenzo Pieralisi 		 * to override the map created in smp_setup_processor_id().
137a0ae0240SLorenzo Pieralisi 		 */
138a0ae0240SLorenzo Pieralisi 		if (hwid == mpidr) {
139a0ae0240SLorenzo Pieralisi 			i = 0;
140a0ae0240SLorenzo Pieralisi 			bootcpu_valid = true;
141a0ae0240SLorenzo Pieralisi 		} else {
142a0ae0240SLorenzo Pieralisi 			i = cpuidx++;
143a0ae0240SLorenzo Pieralisi 		}
144a0ae0240SLorenzo Pieralisi 
145ce7b1756SLorenzo Pieralisi 		if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
146ce7b1756SLorenzo Pieralisi 					       "max cores %u, capping them\n",
147ce7b1756SLorenzo Pieralisi 					       cpuidx, nr_cpu_ids)) {
148ce7b1756SLorenzo Pieralisi 			cpuidx = nr_cpu_ids;
149a0ae0240SLorenzo Pieralisi 			break;
150a0ae0240SLorenzo Pieralisi 		}
151a0ae0240SLorenzo Pieralisi 
152ce7b1756SLorenzo Pieralisi 		tmp_map[i] = hwid;
153ce7b1756SLorenzo Pieralisi 	}
154ce7b1756SLorenzo Pieralisi 
1558d5bc1a6SOlof Johansson 	if (!bootcpu_valid) {
1568d5bc1a6SOlof Johansson 		pr_warn("DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map\n");
157a0ae0240SLorenzo Pieralisi 		return;
1588d5bc1a6SOlof Johansson 	}
159a0ae0240SLorenzo Pieralisi 
160a0ae0240SLorenzo Pieralisi 	/*
161a0ae0240SLorenzo Pieralisi 	 * Since the boot CPU node contains proper data, and all nodes have
162a0ae0240SLorenzo Pieralisi 	 * a reg property, the DT CPU list can be considered valid and the
163a0ae0240SLorenzo Pieralisi 	 * logical map created in smp_setup_processor_id() can be overridden
164a0ae0240SLorenzo Pieralisi 	 */
165a0ae0240SLorenzo Pieralisi 	for (i = 0; i < cpuidx; i++) {
166a0ae0240SLorenzo Pieralisi 		set_cpu_possible(i, true);
167a0ae0240SLorenzo Pieralisi 		cpu_logical_map(i) = tmp_map[i];
168a0ae0240SLorenzo Pieralisi 		pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
169a0ae0240SLorenzo Pieralisi 	}
170a0ae0240SLorenzo Pieralisi }
171a0ae0240SLorenzo Pieralisi 
172973e02c1SSudeep KarkadaNagesha bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
173973e02c1SSudeep KarkadaNagesha {
174*e44ef891SSudeep Holla 	return phys_id == cpu_logical_map(cpu);
175973e02c1SSudeep KarkadaNagesha }
176973e02c1SSudeep KarkadaNagesha 
1776d67a9f6SRob Herring static const void * __init arch_get_next_mach(const char *const **match)
1786d67a9f6SRob Herring {
1796d67a9f6SRob Herring 	static const struct machine_desc *mdesc = __arch_info_begin;
1806d67a9f6SRob Herring 	const struct machine_desc *m = mdesc;
1816d67a9f6SRob Herring 
1826d67a9f6SRob Herring 	if (m >= __arch_info_end)
1836d67a9f6SRob Herring 		return NULL;
1846d67a9f6SRob Herring 
1856d67a9f6SRob Herring 	mdesc++;
1866d67a9f6SRob Herring 	*match = m->dt_compat;
1876d67a9f6SRob Herring 	return m;
1886d67a9f6SRob Herring }
1896d67a9f6SRob Herring 
19093c02ab4SGrant Likely /**
19193c02ab4SGrant Likely  * setup_machine_fdt - Machine setup when an dtb was passed to the kernel
19293c02ab4SGrant Likely  * @dt_phys: physical address of dt blob
19393c02ab4SGrant Likely  *
19493c02ab4SGrant Likely  * If a dtb was passed to the kernel in r2, then use it to choose the
19593c02ab4SGrant Likely  * correct machine_desc and to setup the system.
19693c02ab4SGrant Likely  */
197ff69a4c8SRussell King const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
19893c02ab4SGrant Likely {
199ff69a4c8SRussell King 	const struct machine_desc *mdesc, *mdesc_best = NULL;
20093c02ab4SGrant Likely 
201883a106bSArnd Bergmann #ifdef CONFIG_ARCH_MULTIPLATFORM
202883a106bSArnd Bergmann 	DT_MACHINE_START(GENERIC_DT, "Generic DT based system")
203883a106bSArnd Bergmann 	MACHINE_END
204883a106bSArnd Bergmann 
205ff69a4c8SRussell King 	mdesc_best = &__mach_desc_GENERIC_DT;
206883a106bSArnd Bergmann #endif
207883a106bSArnd Bergmann 
20856dc1f47SRob Herring 	if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys)))
209f506cd48SNicolas Pitre 		return NULL;
210f506cd48SNicolas Pitre 
2116d67a9f6SRob Herring 	mdesc = of_flat_dt_match_machine(mdesc_best, arch_get_next_mach);
21293c02ab4SGrant Likely 
2136d67a9f6SRob Herring 	if (!mdesc) {
21493c02ab4SGrant Likely 		const char *prop;
21593c02ab4SGrant Likely 		long size;
2166d67a9f6SRob Herring 		unsigned long dt_root;
21793c02ab4SGrant Likely 
21893c02ab4SGrant Likely 		early_print("\nError: unrecognized/unsupported "
21993c02ab4SGrant Likely 			    "device tree compatible list:\n[ ");
22093c02ab4SGrant Likely 
2216d67a9f6SRob Herring 		dt_root = of_get_flat_dt_root();
22293c02ab4SGrant Likely 		prop = of_get_flat_dt_prop(dt_root, "compatible", &size);
22393c02ab4SGrant Likely 		while (size > 0) {
22493c02ab4SGrant Likely 			early_print("'%s' ", prop);
22593c02ab4SGrant Likely 			size -= strlen(prop) + 1;
22693c02ab4SGrant Likely 			prop += strlen(prop) + 1;
22793c02ab4SGrant Likely 		}
22893c02ab4SGrant Likely 		early_print("]\n\n");
22993c02ab4SGrant Likely 
23093c02ab4SGrant Likely 		dump_machine_table(); /* does not return */
23193c02ab4SGrant Likely 	}
23293c02ab4SGrant Likely 
23393c02ab4SGrant Likely 	/* Change machine number to match the mdesc we're using */
2346d67a9f6SRob Herring 	__machine_arch_type = mdesc->nr;
23593c02ab4SGrant Likely 
2366d67a9f6SRob Herring 	return mdesc;
23793c02ab4SGrant Likely }
238