1*f8c95fe6SShawn Guo /* 2*f8c95fe6SShawn Guo * Copyright (C) 2012 Freescale Semiconductor, Inc. 3*f8c95fe6SShawn Guo * 4*f8c95fe6SShawn Guo * This program is free software; you can redistribute it and/or modify 5*f8c95fe6SShawn Guo * it under the terms of the GNU General Public License version 2 as 6*f8c95fe6SShawn Guo * published by the Free Software Foundation. 7*f8c95fe6SShawn Guo */ 8*f8c95fe6SShawn Guo 9*f8c95fe6SShawn Guo #ifndef __DEBUG_IMX_UART_H 10*f8c95fe6SShawn Guo #define __DEBUG_IMX_UART_H 11*f8c95fe6SShawn Guo 12*f8c95fe6SShawn Guo #define IMX1_UART1_BASE_ADDR 0x00206000 13*f8c95fe6SShawn Guo #define IMX1_UART2_BASE_ADDR 0x00207000 14*f8c95fe6SShawn Guo #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR 15*f8c95fe6SShawn Guo #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) 16*f8c95fe6SShawn Guo 17*f8c95fe6SShawn Guo #define IMX21_UART1_BASE_ADDR 0x1000a000 18*f8c95fe6SShawn Guo #define IMX21_UART2_BASE_ADDR 0x1000b000 19*f8c95fe6SShawn Guo #define IMX21_UART3_BASE_ADDR 0x1000c000 20*f8c95fe6SShawn Guo #define IMX21_UART4_BASE_ADDR 0x1000d000 21*f8c95fe6SShawn Guo #define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR 22*f8c95fe6SShawn Guo #define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n) 23*f8c95fe6SShawn Guo 24*f8c95fe6SShawn Guo #define IMX25_UART1_BASE_ADDR 0x43f90000 25*f8c95fe6SShawn Guo #define IMX25_UART2_BASE_ADDR 0x43f94000 26*f8c95fe6SShawn Guo #define IMX25_UART3_BASE_ADDR 0x5000c000 27*f8c95fe6SShawn Guo #define IMX25_UART4_BASE_ADDR 0x50008000 28*f8c95fe6SShawn Guo #define IMX25_UART5_BASE_ADDR 0x5002c000 29*f8c95fe6SShawn Guo #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR 30*f8c95fe6SShawn Guo #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) 31*f8c95fe6SShawn Guo 32*f8c95fe6SShawn Guo #define IMX31_UART1_BASE_ADDR 0x43f90000 33*f8c95fe6SShawn Guo #define IMX31_UART2_BASE_ADDR 0x43f94000 34*f8c95fe6SShawn Guo #define IMX31_UART3_BASE_ADDR 0x5000c000 35*f8c95fe6SShawn Guo #define IMX31_UART4_BASE_ADDR 0x43fb0000 36*f8c95fe6SShawn Guo #define IMX31_UART5_BASE_ADDR 0x43fb4000 37*f8c95fe6SShawn Guo #define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR 38*f8c95fe6SShawn Guo #define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n) 39*f8c95fe6SShawn Guo 40*f8c95fe6SShawn Guo #define IMX35_UART1_BASE_ADDR 0x43f90000 41*f8c95fe6SShawn Guo #define IMX35_UART2_BASE_ADDR 0x43f94000 42*f8c95fe6SShawn Guo #define IMX35_UART3_BASE_ADDR 0x5000c000 43*f8c95fe6SShawn Guo #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR 44*f8c95fe6SShawn Guo #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) 45*f8c95fe6SShawn Guo 46*f8c95fe6SShawn Guo #define IMX51_UART1_BASE_ADDR 0x73fbc000 47*f8c95fe6SShawn Guo #define IMX51_UART2_BASE_ADDR 0x73fc0000 48*f8c95fe6SShawn Guo #define IMX51_UART3_BASE_ADDR 0x7000c000 49*f8c95fe6SShawn Guo #define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR 50*f8c95fe6SShawn Guo #define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n) 51*f8c95fe6SShawn Guo 52*f8c95fe6SShawn Guo #define IMX53_UART1_BASE_ADDR 0x53fbc000 53*f8c95fe6SShawn Guo #define IMX53_UART2_BASE_ADDR 0x53fc0000 54*f8c95fe6SShawn Guo #define IMX53_UART3_BASE_ADDR 0x5000c000 55*f8c95fe6SShawn Guo #define IMX53_UART4_BASE_ADDR 0x53ff0000 56*f8c95fe6SShawn Guo #define IMX53_UART5_BASE_ADDR 0x63f90000 57*f8c95fe6SShawn Guo #define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR 58*f8c95fe6SShawn Guo #define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n) 59*f8c95fe6SShawn Guo 60*f8c95fe6SShawn Guo #define IMX6Q_UART1_BASE_ADDR 0x02020000 61*f8c95fe6SShawn Guo #define IMX6Q_UART2_BASE_ADDR 0x021e8000 62*f8c95fe6SShawn Guo #define IMX6Q_UART3_BASE_ADDR 0x021ec000 63*f8c95fe6SShawn Guo #define IMX6Q_UART4_BASE_ADDR 0x021f0000 64*f8c95fe6SShawn Guo #define IMX6Q_UART5_BASE_ADDR 0x021f4000 65*f8c95fe6SShawn Guo #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR 66*f8c95fe6SShawn Guo #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) 67*f8c95fe6SShawn Guo 68*f8c95fe6SShawn Guo #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 69*f8c95fe6SShawn Guo 70*f8c95fe6SShawn Guo #ifdef CONFIG_DEBUG_IMX1_UART 71*f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) 72*f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX21_IMX27_UART) 73*f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX21) 74*f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX25_UART) 75*f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) 76*f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX31_UART) 77*f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) 78*f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX35_UART) 79*f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) 80*f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX51_UART) 81*f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) 82*f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX53_UART) 83*f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) 84*f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX6Q_UART) 85*f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 86*f8c95fe6SShawn Guo #endif 87*f8c95fe6SShawn Guo 88*f8c95fe6SShawn Guo #endif /* __DEBUG_IMX_UART_H */ 89