1f8c95fe6SShawn Guo /* 2f8c95fe6SShawn Guo * Copyright (C) 2012 Freescale Semiconductor, Inc. 3f8c95fe6SShawn Guo * 4f8c95fe6SShawn Guo * This program is free software; you can redistribute it and/or modify 5f8c95fe6SShawn Guo * it under the terms of the GNU General Public License version 2 as 6f8c95fe6SShawn Guo * published by the Free Software Foundation. 7f8c95fe6SShawn Guo */ 8f8c95fe6SShawn Guo 9f8c95fe6SShawn Guo #ifndef __DEBUG_IMX_UART_H 10f8c95fe6SShawn Guo #define __DEBUG_IMX_UART_H 11f8c95fe6SShawn Guo 12f8c95fe6SShawn Guo #define IMX1_UART1_BASE_ADDR 0x00206000 13f8c95fe6SShawn Guo #define IMX1_UART2_BASE_ADDR 0x00207000 14f8c95fe6SShawn Guo #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR 15f8c95fe6SShawn Guo #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) 16f8c95fe6SShawn Guo 17f8c95fe6SShawn Guo #define IMX21_UART1_BASE_ADDR 0x1000a000 18f8c95fe6SShawn Guo #define IMX21_UART2_BASE_ADDR 0x1000b000 19f8c95fe6SShawn Guo #define IMX21_UART3_BASE_ADDR 0x1000c000 20f8c95fe6SShawn Guo #define IMX21_UART4_BASE_ADDR 0x1000d000 21f8c95fe6SShawn Guo #define IMX21_UART_BASE_ADDR(n) IMX21_UART##n##_BASE_ADDR 22f8c95fe6SShawn Guo #define IMX21_UART_BASE(n) IMX21_UART_BASE_ADDR(n) 23f8c95fe6SShawn Guo 24f8c95fe6SShawn Guo #define IMX25_UART1_BASE_ADDR 0x43f90000 25f8c95fe6SShawn Guo #define IMX25_UART2_BASE_ADDR 0x43f94000 26f8c95fe6SShawn Guo #define IMX25_UART3_BASE_ADDR 0x5000c000 27f8c95fe6SShawn Guo #define IMX25_UART4_BASE_ADDR 0x50008000 28f8c95fe6SShawn Guo #define IMX25_UART5_BASE_ADDR 0x5002c000 29f8c95fe6SShawn Guo #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR 30f8c95fe6SShawn Guo #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) 31f8c95fe6SShawn Guo 32f8c95fe6SShawn Guo #define IMX31_UART1_BASE_ADDR 0x43f90000 33f8c95fe6SShawn Guo #define IMX31_UART2_BASE_ADDR 0x43f94000 34f8c95fe6SShawn Guo #define IMX31_UART3_BASE_ADDR 0x5000c000 35f8c95fe6SShawn Guo #define IMX31_UART4_BASE_ADDR 0x43fb0000 36f8c95fe6SShawn Guo #define IMX31_UART5_BASE_ADDR 0x43fb4000 37f8c95fe6SShawn Guo #define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR 38f8c95fe6SShawn Guo #define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n) 39f8c95fe6SShawn Guo 40f8c95fe6SShawn Guo #define IMX35_UART1_BASE_ADDR 0x43f90000 41f8c95fe6SShawn Guo #define IMX35_UART2_BASE_ADDR 0x43f94000 42f8c95fe6SShawn Guo #define IMX35_UART3_BASE_ADDR 0x5000c000 43f8c95fe6SShawn Guo #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR 44f8c95fe6SShawn Guo #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) 45f8c95fe6SShawn Guo 46ad364a70SGreg Ungerer #define IMX50_UART1_BASE_ADDR 0x53fbc000 47ad364a70SGreg Ungerer #define IMX50_UART2_BASE_ADDR 0x53fc0000 48ad364a70SGreg Ungerer #define IMX50_UART3_BASE_ADDR 0x5000c000 49ad364a70SGreg Ungerer #define IMX50_UART4_BASE_ADDR 0x53ff0000 50ad364a70SGreg Ungerer #define IMX50_UART5_BASE_ADDR 0x63f90000 51ad364a70SGreg Ungerer #define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR 52ad364a70SGreg Ungerer #define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n) 53ad364a70SGreg Ungerer 54f8c95fe6SShawn Guo #define IMX51_UART1_BASE_ADDR 0x73fbc000 55f8c95fe6SShawn Guo #define IMX51_UART2_BASE_ADDR 0x73fc0000 56f8c95fe6SShawn Guo #define IMX51_UART3_BASE_ADDR 0x7000c000 57f8c95fe6SShawn Guo #define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR 58f8c95fe6SShawn Guo #define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n) 59f8c95fe6SShawn Guo 60f8c95fe6SShawn Guo #define IMX53_UART1_BASE_ADDR 0x53fbc000 61f8c95fe6SShawn Guo #define IMX53_UART2_BASE_ADDR 0x53fc0000 62f8c95fe6SShawn Guo #define IMX53_UART3_BASE_ADDR 0x5000c000 63f8c95fe6SShawn Guo #define IMX53_UART4_BASE_ADDR 0x53ff0000 64f8c95fe6SShawn Guo #define IMX53_UART5_BASE_ADDR 0x63f90000 65f8c95fe6SShawn Guo #define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR 66f8c95fe6SShawn Guo #define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n) 67f8c95fe6SShawn Guo 68f8c95fe6SShawn Guo #define IMX6Q_UART1_BASE_ADDR 0x02020000 69f8c95fe6SShawn Guo #define IMX6Q_UART2_BASE_ADDR 0x021e8000 70f8c95fe6SShawn Guo #define IMX6Q_UART3_BASE_ADDR 0x021ec000 71f8c95fe6SShawn Guo #define IMX6Q_UART4_BASE_ADDR 0x021f0000 72f8c95fe6SShawn Guo #define IMX6Q_UART5_BASE_ADDR 0x021f4000 73f8c95fe6SShawn Guo #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR 74f8c95fe6SShawn Guo #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) 75f8c95fe6SShawn Guo 7634e8a16bSShawn Guo #define IMX6SL_UART1_BASE_ADDR 0x02020000 7734e8a16bSShawn Guo #define IMX6SL_UART2_BASE_ADDR 0x02024000 7834e8a16bSShawn Guo #define IMX6SL_UART3_BASE_ADDR 0x02034000 7934e8a16bSShawn Guo #define IMX6SL_UART4_BASE_ADDR 0x02038000 8034e8a16bSShawn Guo #define IMX6SL_UART5_BASE_ADDR 0x02018000 8134e8a16bSShawn Guo #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR 8234e8a16bSShawn Guo #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) 8334e8a16bSShawn Guo 84*74368e81SShawn Guo #define IMX6SX_UART1_BASE_ADDR 0x02020000 85*74368e81SShawn Guo #define IMX6SX_UART2_BASE_ADDR 0x021e8000 86*74368e81SShawn Guo #define IMX6SX_UART3_BASE_ADDR 0x021ec000 87*74368e81SShawn Guo #define IMX6SX_UART4_BASE_ADDR 0x021f0000 88*74368e81SShawn Guo #define IMX6SX_UART5_BASE_ADDR 0x021f4000 89*74368e81SShawn Guo #define IMX6SX_UART6_BASE_ADDR 0x022a0000 90*74368e81SShawn Guo #define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR 91*74368e81SShawn Guo #define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n) 92*74368e81SShawn Guo 93f8c95fe6SShawn Guo #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 94f8c95fe6SShawn Guo 95f8c95fe6SShawn Guo #ifdef CONFIG_DEBUG_IMX1_UART 96f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) 97f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX21_IMX27_UART) 98f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX21) 99f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX25_UART) 100f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) 101f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX31_UART) 102f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) 103f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX35_UART) 104f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) 105ad364a70SGreg Ungerer #elif defined(CONFIG_DEBUG_IMX50_UART) 106ad364a70SGreg Ungerer #define UART_PADDR IMX_DEBUG_UART_BASE(IMX50) 107f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX51_UART) 108f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) 109f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX53_UART) 110f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) 111f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX6Q_UART) 112f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 11334e8a16bSShawn Guo #elif defined(CONFIG_DEBUG_IMX6SL_UART) 11434e8a16bSShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) 115*74368e81SShawn Guo #elif defined(CONFIG_DEBUG_IMX6SX_UART) 116*74368e81SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) 117f8c95fe6SShawn Guo #endif 118f8c95fe6SShawn Guo 119f8c95fe6SShawn Guo #endif /* __DEBUG_IMX_UART_H */ 120