1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2f8c95fe6SShawn Guo /* 352d7aec2SAnson Huang * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. 4f8c95fe6SShawn Guo */ 5f8c95fe6SShawn Guo 6f8c95fe6SShawn Guo #ifndef __DEBUG_IMX_UART_H 7f8c95fe6SShawn Guo #define __DEBUG_IMX_UART_H 8f8c95fe6SShawn Guo 9f8c95fe6SShawn Guo #define IMX1_UART1_BASE_ADDR 0x00206000 10f8c95fe6SShawn Guo #define IMX1_UART2_BASE_ADDR 0x00207000 11f8c95fe6SShawn Guo #define IMX1_UART_BASE_ADDR(n) IMX1_UART##n##_BASE_ADDR 12f8c95fe6SShawn Guo #define IMX1_UART_BASE(n) IMX1_UART_BASE_ADDR(n) 13f8c95fe6SShawn Guo 14f8c95fe6SShawn Guo #define IMX25_UART1_BASE_ADDR 0x43f90000 15f8c95fe6SShawn Guo #define IMX25_UART2_BASE_ADDR 0x43f94000 16f8c95fe6SShawn Guo #define IMX25_UART3_BASE_ADDR 0x5000c000 17f8c95fe6SShawn Guo #define IMX25_UART4_BASE_ADDR 0x50008000 18f8c95fe6SShawn Guo #define IMX25_UART5_BASE_ADDR 0x5002c000 19f8c95fe6SShawn Guo #define IMX25_UART_BASE_ADDR(n) IMX25_UART##n##_BASE_ADDR 20f8c95fe6SShawn Guo #define IMX25_UART_BASE(n) IMX25_UART_BASE_ADDR(n) 21f8c95fe6SShawn Guo 22*b0100bceSLukas Bulwahn #define IMX27_UART1_BASE_ADDR 0x1000a000 23*b0100bceSLukas Bulwahn #define IMX27_UART2_BASE_ADDR 0x1000b000 24*b0100bceSLukas Bulwahn #define IMX27_UART3_BASE_ADDR 0x1000c000 25*b0100bceSLukas Bulwahn #define IMX27_UART4_BASE_ADDR 0x1000d000 26*b0100bceSLukas Bulwahn #define IMX27_UART_BASE_ADDR(n) IMX27_UART##n##_BASE_ADDR 27*b0100bceSLukas Bulwahn #define IMX27_UART_BASE(n) IMX27_UART_BASE_ADDR(n) 28*b0100bceSLukas Bulwahn 29f8c95fe6SShawn Guo #define IMX31_UART1_BASE_ADDR 0x43f90000 30f8c95fe6SShawn Guo #define IMX31_UART2_BASE_ADDR 0x43f94000 31f8c95fe6SShawn Guo #define IMX31_UART3_BASE_ADDR 0x5000c000 32f8c95fe6SShawn Guo #define IMX31_UART4_BASE_ADDR 0x43fb0000 33f8c95fe6SShawn Guo #define IMX31_UART5_BASE_ADDR 0x43fb4000 34f8c95fe6SShawn Guo #define IMX31_UART_BASE_ADDR(n) IMX31_UART##n##_BASE_ADDR 35f8c95fe6SShawn Guo #define IMX31_UART_BASE(n) IMX31_UART_BASE_ADDR(n) 36f8c95fe6SShawn Guo 37f8c95fe6SShawn Guo #define IMX35_UART1_BASE_ADDR 0x43f90000 38f8c95fe6SShawn Guo #define IMX35_UART2_BASE_ADDR 0x43f94000 39f8c95fe6SShawn Guo #define IMX35_UART3_BASE_ADDR 0x5000c000 40f8c95fe6SShawn Guo #define IMX35_UART_BASE_ADDR(n) IMX35_UART##n##_BASE_ADDR 41f8c95fe6SShawn Guo #define IMX35_UART_BASE(n) IMX35_UART_BASE_ADDR(n) 42f8c95fe6SShawn Guo 43ad364a70SGreg Ungerer #define IMX50_UART1_BASE_ADDR 0x53fbc000 44ad364a70SGreg Ungerer #define IMX50_UART2_BASE_ADDR 0x53fc0000 45ad364a70SGreg Ungerer #define IMX50_UART3_BASE_ADDR 0x5000c000 46ad364a70SGreg Ungerer #define IMX50_UART4_BASE_ADDR 0x53ff0000 47ad364a70SGreg Ungerer #define IMX50_UART5_BASE_ADDR 0x63f90000 48ad364a70SGreg Ungerer #define IMX50_UART_BASE_ADDR(n) IMX50_UART##n##_BASE_ADDR 49ad364a70SGreg Ungerer #define IMX50_UART_BASE(n) IMX50_UART_BASE_ADDR(n) 50ad364a70SGreg Ungerer 51f8c95fe6SShawn Guo #define IMX51_UART1_BASE_ADDR 0x73fbc000 52f8c95fe6SShawn Guo #define IMX51_UART2_BASE_ADDR 0x73fc0000 53f8c95fe6SShawn Guo #define IMX51_UART3_BASE_ADDR 0x7000c000 54f8c95fe6SShawn Guo #define IMX51_UART_BASE_ADDR(n) IMX51_UART##n##_BASE_ADDR 55f8c95fe6SShawn Guo #define IMX51_UART_BASE(n) IMX51_UART_BASE_ADDR(n) 56f8c95fe6SShawn Guo 57f8c95fe6SShawn Guo #define IMX53_UART1_BASE_ADDR 0x53fbc000 58f8c95fe6SShawn Guo #define IMX53_UART2_BASE_ADDR 0x53fc0000 59f8c95fe6SShawn Guo #define IMX53_UART3_BASE_ADDR 0x5000c000 60f8c95fe6SShawn Guo #define IMX53_UART4_BASE_ADDR 0x53ff0000 61f8c95fe6SShawn Guo #define IMX53_UART5_BASE_ADDR 0x63f90000 62f8c95fe6SShawn Guo #define IMX53_UART_BASE_ADDR(n) IMX53_UART##n##_BASE_ADDR 63f8c95fe6SShawn Guo #define IMX53_UART_BASE(n) IMX53_UART_BASE_ADDR(n) 64f8c95fe6SShawn Guo 65f8c95fe6SShawn Guo #define IMX6Q_UART1_BASE_ADDR 0x02020000 66f8c95fe6SShawn Guo #define IMX6Q_UART2_BASE_ADDR 0x021e8000 67f8c95fe6SShawn Guo #define IMX6Q_UART3_BASE_ADDR 0x021ec000 68f8c95fe6SShawn Guo #define IMX6Q_UART4_BASE_ADDR 0x021f0000 69f8c95fe6SShawn Guo #define IMX6Q_UART5_BASE_ADDR 0x021f4000 70f8c95fe6SShawn Guo #define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR 71f8c95fe6SShawn Guo #define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) 72f8c95fe6SShawn Guo 7334e8a16bSShawn Guo #define IMX6SL_UART1_BASE_ADDR 0x02020000 7434e8a16bSShawn Guo #define IMX6SL_UART2_BASE_ADDR 0x02024000 7534e8a16bSShawn Guo #define IMX6SL_UART3_BASE_ADDR 0x02034000 7634e8a16bSShawn Guo #define IMX6SL_UART4_BASE_ADDR 0x02038000 7734e8a16bSShawn Guo #define IMX6SL_UART5_BASE_ADDR 0x02018000 7834e8a16bSShawn Guo #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR 7934e8a16bSShawn Guo #define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) 8034e8a16bSShawn Guo 8174368e81SShawn Guo #define IMX6SX_UART1_BASE_ADDR 0x02020000 8274368e81SShawn Guo #define IMX6SX_UART2_BASE_ADDR 0x021e8000 8374368e81SShawn Guo #define IMX6SX_UART3_BASE_ADDR 0x021ec000 8474368e81SShawn Guo #define IMX6SX_UART4_BASE_ADDR 0x021f0000 8574368e81SShawn Guo #define IMX6SX_UART5_BASE_ADDR 0x021f4000 8674368e81SShawn Guo #define IMX6SX_UART6_BASE_ADDR 0x022a0000 8774368e81SShawn Guo #define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR 8874368e81SShawn Guo #define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n) 8974368e81SShawn Guo 9020c305f6SAnson Huang #define IMX6UL_UART1_BASE_ADDR 0x02020000 9120c305f6SAnson Huang #define IMX6UL_UART2_BASE_ADDR 0x021e8000 9220c305f6SAnson Huang #define IMX6UL_UART3_BASE_ADDR 0x021ec000 9320c305f6SAnson Huang #define IMX6UL_UART4_BASE_ADDR 0x021f0000 9420c305f6SAnson Huang #define IMX6UL_UART5_BASE_ADDR 0x021f4000 9520c305f6SAnson Huang #define IMX6UL_UART6_BASE_ADDR 0x021fc000 9620c305f6SAnson Huang #define IMX6UL_UART7_BASE_ADDR 0x02018000 9720c305f6SAnson Huang #define IMX6UL_UART8_BASE_ADDR 0x02024000 9820c305f6SAnson Huang #define IMX6UL_UART_BASE_ADDR(n) IMX6UL_UART##n##_BASE_ADDR 9920c305f6SAnson Huang #define IMX6UL_UART_BASE(n) IMX6UL_UART_BASE_ADDR(n) 10020c305f6SAnson Huang 10152d7aec2SAnson Huang #define IMX7D_UART1_BASE_ADDR 0x30860000 10252d7aec2SAnson Huang #define IMX7D_UART2_BASE_ADDR 0x30890000 10352d7aec2SAnson Huang #define IMX7D_UART3_BASE_ADDR 0x30880000 10452d7aec2SAnson Huang #define IMX7D_UART4_BASE_ADDR 0x30a60000 10552d7aec2SAnson Huang #define IMX7D_UART5_BASE_ADDR 0x30a70000 10652d7aec2SAnson Huang #define IMX7D_UART6_BASE_ADDR 0x30a80000 10752d7aec2SAnson Huang #define IMX7D_UART7_BASE_ADDR 0x30a90000 10852d7aec2SAnson Huang #define IMX7D_UART_BASE_ADDR(n) IMX7D_UART##n##_BASE_ADDR 10952d7aec2SAnson Huang #define IMX7D_UART_BASE(n) IMX7D_UART_BASE_ADDR(n) 11052d7aec2SAnson Huang 111f8c95fe6SShawn Guo #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 112f8c95fe6SShawn Guo 113f8c95fe6SShawn Guo #ifdef CONFIG_DEBUG_IMX1_UART 114f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX1) 115f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX25_UART) 116f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX25) 117*b0100bceSLukas Bulwahn #elif defined(CONFIG_DEBUG_IMX27_UART) 118*b0100bceSLukas Bulwahn #define UART_PADDR IMX_DEBUG_UART_BASE(IMX27) 119f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX31_UART) 120f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX31) 121f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX35_UART) 122f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX35) 123ad364a70SGreg Ungerer #elif defined(CONFIG_DEBUG_IMX50_UART) 124ad364a70SGreg Ungerer #define UART_PADDR IMX_DEBUG_UART_BASE(IMX50) 125f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX51_UART) 126f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX51) 127f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX53_UART) 128f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) 129f8c95fe6SShawn Guo #elif defined(CONFIG_DEBUG_IMX6Q_UART) 130f8c95fe6SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 13134e8a16bSShawn Guo #elif defined(CONFIG_DEBUG_IMX6SL_UART) 13234e8a16bSShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) 13374368e81SShawn Guo #elif defined(CONFIG_DEBUG_IMX6SX_UART) 13474368e81SShawn Guo #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) 13520c305f6SAnson Huang #elif defined(CONFIG_DEBUG_IMX6UL_UART) 13620c305f6SAnson Huang #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6UL) 13752d7aec2SAnson Huang #elif defined(CONFIG_DEBUG_IMX7D_UART) 13852d7aec2SAnson Huang #define UART_PADDR IMX_DEBUG_UART_BASE(IMX7D) 13952d7aec2SAnson Huang 140f8c95fe6SShawn Guo #endif 141f8c95fe6SShawn Guo 142f8c95fe6SShawn Guo #endif /* __DEBUG_IMX_UART_H */ 143