1 /* 2 * arch/arm/include/asm/pgtable.h 3 * 4 * Copyright (C) 1995-2002 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _ASMARM_PGTABLE_H 11 #define _ASMARM_PGTABLE_H 12 13 #include <asm-generic/4level-fixup.h> 14 #include <asm/proc-fns.h> 15 16 #ifndef CONFIG_MMU 17 18 #include "pgtable-nommu.h" 19 20 #else 21 22 #include <asm/memory.h> 23 #include <mach/vmalloc.h> 24 #include <asm/pgtable-hwdef.h> 25 26 /* 27 * Just any arbitrary offset to the start of the vmalloc VM area: the 28 * current 8MB value just means that there will be a 8MB "hole" after the 29 * physical memory until the kernel virtual memory starts. That means that 30 * any out-of-bounds memory accesses will hopefully be caught. 31 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 32 * area for the same reason. ;) 33 * 34 * Note that platforms may override VMALLOC_START, but they must provide 35 * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space, 36 * which may not overlap IO space. 37 */ 38 #ifndef VMALLOC_START 39 #define VMALLOC_OFFSET (8*1024*1024) 40 #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) 41 #endif 42 43 /* 44 * Hardware-wise, we have a two level page table structure, where the first 45 * level has 4096 entries, and the second level has 256 entries. Each entry 46 * is one 32-bit word. Most of the bits in the second level entry are used 47 * by hardware, and there aren't any "accessed" and "dirty" bits. 48 * 49 * Linux on the other hand has a three level page table structure, which can 50 * be wrapped to fit a two level page table structure easily - using the PGD 51 * and PTE only. However, Linux also expects one "PTE" table per page, and 52 * at least a "dirty" bit. 53 * 54 * Therefore, we tweak the implementation slightly - we tell Linux that we 55 * have 2048 entries in the first level, each of which is 8 bytes (iow, two 56 * hardware pointers to the second level.) The second level contains two 57 * hardware PTE tables arranged contiguously, followed by Linux versions 58 * which contain the state information Linux needs. We, therefore, end up 59 * with 512 entries in the "PTE" level. 60 * 61 * This leads to the page tables having the following layout: 62 * 63 * pgd pte 64 * | | 65 * +--------+ +0 66 * | |-----> +------------+ +0 67 * +- - - - + +4 | h/w pt 0 | 68 * | |-----> +------------+ +1024 69 * +--------+ +8 | h/w pt 1 | 70 * | | +------------+ +2048 71 * +- - - - + | Linux pt 0 | 72 * | | +------------+ +3072 73 * +--------+ | Linux pt 1 | 74 * | | +------------+ +4096 75 * 76 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and 77 * PTE_xxx for definitions of bits appearing in the "h/w pt". 78 * 79 * PMD_xxx definitions refer to bits in the first level page table. 80 * 81 * The "dirty" bit is emulated by only granting hardware write permission 82 * iff the page is marked "writable" and "dirty" in the Linux PTE. This 83 * means that a write to a clean page will cause a permission fault, and 84 * the Linux MM layer will mark the page dirty via handle_pte_fault(). 85 * For the hardware to notice the permission change, the TLB entry must 86 * be flushed, and ptep_set_access_flags() does that for us. 87 * 88 * The "accessed" or "young" bit is emulated by a similar method; we only 89 * allow accesses to the page if the "young" bit is set. Accesses to the 90 * page will cause a fault, and handle_pte_fault() will set the young bit 91 * for us as long as the page is marked present in the corresponding Linux 92 * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is 93 * up to date. 94 * 95 * However, when the "young" bit is cleared, we deny access to the page 96 * by clearing the hardware PTE. Currently Linux does not flush the TLB 97 * for us in this case, which means the TLB will retain the transation 98 * until either the TLB entry is evicted under pressure, or a context 99 * switch which changes the user space mapping occurs. 100 */ 101 #define PTRS_PER_PTE 512 102 #define PTRS_PER_PMD 1 103 #define PTRS_PER_PGD 2048 104 105 /* 106 * PMD_SHIFT determines the size of the area a second-level page table can map 107 * PGDIR_SHIFT determines what a third-level page table entry can map 108 */ 109 #define PMD_SHIFT 21 110 #define PGDIR_SHIFT 21 111 112 #define LIBRARY_TEXT_START 0x0c000000 113 114 #ifndef __ASSEMBLY__ 115 extern void __pte_error(const char *file, int line, unsigned long val); 116 extern void __pmd_error(const char *file, int line, unsigned long val); 117 extern void __pgd_error(const char *file, int line, unsigned long val); 118 119 #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) 120 #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) 121 #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) 122 #endif /* !__ASSEMBLY__ */ 123 124 #define PMD_SIZE (1UL << PMD_SHIFT) 125 #define PMD_MASK (~(PMD_SIZE-1)) 126 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 127 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 128 129 /* 130 * This is the lowest virtual address we can permit any user space 131 * mapping to be mapped at. This is particularly important for 132 * non-high vector CPUs. 133 */ 134 #define FIRST_USER_ADDRESS PAGE_SIZE 135 136 #define FIRST_USER_PGD_NR 1 137 #define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR) 138 139 /* 140 * section address mask and size definitions. 141 */ 142 #define SECTION_SHIFT 20 143 #define SECTION_SIZE (1UL << SECTION_SHIFT) 144 #define SECTION_MASK (~(SECTION_SIZE-1)) 145 146 /* 147 * ARMv6 supersection address mask and size definitions. 148 */ 149 #define SUPERSECTION_SHIFT 24 150 #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) 151 #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) 152 153 /* 154 * "Linux" PTE definitions. 155 * 156 * We keep two sets of PTEs - the hardware and the linux version. 157 * This allows greater flexibility in the way we map the Linux bits 158 * onto the hardware tables, and allows us to have YOUNG and DIRTY 159 * bits. 160 * 161 * The PTE table pointer refers to the hardware entries; the "Linux" 162 * entries are stored 1024 bytes below. 163 */ 164 #define L_PTE_PRESENT (1 << 0) 165 #define L_PTE_FILE (1 << 1) /* only when !PRESENT */ 166 #define L_PTE_YOUNG (1 << 1) 167 #define L_PTE_BUFFERABLE (1 << 2) /* obsolete, matches PTE */ 168 #define L_PTE_CACHEABLE (1 << 3) /* obsolete, matches PTE */ 169 #define L_PTE_DIRTY (1 << 6) 170 #define L_PTE_WRITE (1 << 7) 171 #define L_PTE_USER (1 << 8) 172 #define L_PTE_EXEC (1 << 9) 173 #define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */ 174 175 /* 176 * These are the memory types, defined to be compatible with 177 * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB 178 */ 179 #define L_PTE_MT_UNCACHED (0x00 << 2) /* 0000 */ 180 #define L_PTE_MT_BUFFERABLE (0x01 << 2) /* 0001 */ 181 #define L_PTE_MT_WRITETHROUGH (0x02 << 2) /* 0010 */ 182 #define L_PTE_MT_WRITEBACK (0x03 << 2) /* 0011 */ 183 #define L_PTE_MT_MINICACHE (0x06 << 2) /* 0110 (sa1100, xscale) */ 184 #define L_PTE_MT_WRITEALLOC (0x07 << 2) /* 0111 */ 185 #define L_PTE_MT_DEV_SHARED (0x04 << 2) /* 0100 */ 186 #define L_PTE_MT_DEV_NONSHARED (0x0c << 2) /* 1100 */ 187 #define L_PTE_MT_DEV_WC (0x09 << 2) /* 1001 */ 188 #define L_PTE_MT_DEV_CACHED (0x0b << 2) /* 1011 */ 189 #define L_PTE_MT_MASK (0x0f << 2) 190 191 #ifndef __ASSEMBLY__ 192 193 /* 194 * The pgprot_* and protection_map entries will be fixed up in runtime 195 * to include the cachable and bufferable bits based on memory policy, 196 * as well as any architecture dependent bits like global/ASID and SMP 197 * shared mapping bits. 198 */ 199 #define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG 200 #define _L_PTE_READ L_PTE_USER | L_PTE_EXEC 201 202 extern pgprot_t pgprot_user; 203 extern pgprot_t pgprot_kernel; 204 205 #define PAGE_NONE pgprot_user 206 #define PAGE_COPY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ) 207 #define PAGE_SHARED __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ | \ 208 L_PTE_WRITE) 209 #define PAGE_READONLY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ) 210 #define PAGE_KERNEL pgprot_kernel 211 212 #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT) 213 #define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ) 214 #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE) 215 #define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ) 216 217 #endif /* __ASSEMBLY__ */ 218 219 /* 220 * The table below defines the page protection levels that we insert into our 221 * Linux page table version. These get translated into the best that the 222 * architecture can perform. Note that on most ARM hardware: 223 * 1) We cannot do execute protection 224 * 2) If we could do execute protection, then read is implied 225 * 3) write implies read permissions 226 */ 227 #define __P000 __PAGE_NONE 228 #define __P001 __PAGE_READONLY 229 #define __P010 __PAGE_COPY 230 #define __P011 __PAGE_COPY 231 #define __P100 __PAGE_READONLY 232 #define __P101 __PAGE_READONLY 233 #define __P110 __PAGE_COPY 234 #define __P111 __PAGE_COPY 235 236 #define __S000 __PAGE_NONE 237 #define __S001 __PAGE_READONLY 238 #define __S010 __PAGE_SHARED 239 #define __S011 __PAGE_SHARED 240 #define __S100 __PAGE_READONLY 241 #define __S101 __PAGE_READONLY 242 #define __S110 __PAGE_SHARED 243 #define __S111 __PAGE_SHARED 244 245 #ifndef __ASSEMBLY__ 246 /* 247 * ZERO_PAGE is a global shared page that is always zero: used 248 * for zero-mapped memory areas etc.. 249 */ 250 extern struct page *empty_zero_page; 251 #define ZERO_PAGE(vaddr) (empty_zero_page) 252 253 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 254 #define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))) 255 256 #define pte_none(pte) (!pte_val(pte)) 257 #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) 258 #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) 259 #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) 260 #define pte_offset_map(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) 261 #define pte_offset_map_nested(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) 262 #define pte_unmap(pte) do { } while (0) 263 #define pte_unmap_nested(pte) do { } while (0) 264 265 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) 266 267 #define set_pte_at(mm,addr,ptep,pteval) do { \ 268 set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \ 269 } while (0) 270 271 /* 272 * The following only work if pte_present() is true. 273 * Undefined behaviour if not.. 274 */ 275 #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT) 276 #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE) 277 #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) 278 #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) 279 #define pte_special(pte) (0) 280 281 /* 282 * The following only works if pte_present() is not true. 283 */ 284 #define pte_file(pte) (pte_val(pte) & L_PTE_FILE) 285 #define pte_to_pgoff(x) (pte_val(x) >> 2) 286 #define pgoff_to_pte(x) __pte(((x) << 2) | L_PTE_FILE) 287 288 #define PTE_FILE_MAX_BITS 30 289 290 #define PTE_BIT_FUNC(fn,op) \ 291 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } 292 293 PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE); 294 PTE_BIT_FUNC(mkwrite, |= L_PTE_WRITE); 295 PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY); 296 PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY); 297 PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG); 298 PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG); 299 300 static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 301 302 /* 303 * Mark the prot value as uncacheable and unbufferable. 304 */ 305 #define pgprot_noncached(prot) \ 306 __pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_UNCACHED) 307 #define pgprot_writecombine(prot) \ 308 __pgprot((pgprot_val(prot) & ~L_PTE_MT_MASK) | L_PTE_MT_BUFFERABLE) 309 310 #define pmd_none(pmd) (!pmd_val(pmd)) 311 #define pmd_present(pmd) (pmd_val(pmd)) 312 #define pmd_bad(pmd) (pmd_val(pmd) & 2) 313 314 #define copy_pmd(pmdpd,pmdps) \ 315 do { \ 316 pmdpd[0] = pmdps[0]; \ 317 pmdpd[1] = pmdps[1]; \ 318 flush_pmd_entry(pmdpd); \ 319 } while (0) 320 321 #define pmd_clear(pmdp) \ 322 do { \ 323 pmdp[0] = __pmd(0); \ 324 pmdp[1] = __pmd(0); \ 325 clean_pmd_entry(pmdp); \ 326 } while (0) 327 328 static inline pte_t *pmd_page_vaddr(pmd_t pmd) 329 { 330 unsigned long ptr; 331 332 ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1); 333 ptr += PTRS_PER_PTE * sizeof(void *); 334 335 return __va(ptr); 336 } 337 338 #define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd))) 339 340 /* 341 * Permanent address of a page. We never have highmem, so this is trivial. 342 */ 343 #define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT)) 344 345 /* 346 * Conversion functions: convert a page and protection to a page entry, 347 * and a page entry and page directory to the page they refer to. 348 */ 349 #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) 350 351 /* 352 * The "pgd_xxx()" functions here are trivial for a folded two-level 353 * setup: the pgd is never bad, and a pmd always exists (as it's folded 354 * into the pgd entry) 355 */ 356 #define pgd_none(pgd) (0) 357 #define pgd_bad(pgd) (0) 358 #define pgd_present(pgd) (1) 359 #define pgd_clear(pgdp) do { } while (0) 360 #define set_pgd(pgd,pgdp) do { } while (0) 361 362 /* to find an entry in a page-table-directory */ 363 #define pgd_index(addr) ((addr) >> PGDIR_SHIFT) 364 365 #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr)) 366 367 /* to find an entry in a kernel page-table-directory */ 368 #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 369 370 /* Find an entry in the second-level page table.. */ 371 #define pmd_offset(dir, addr) ((pmd_t *)(dir)) 372 373 /* Find an entry in the third-level page table.. */ 374 #define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 375 376 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 377 { 378 const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER; 379 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 380 return pte; 381 } 382 383 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 384 385 /* Encode and decode a swap entry. 386 * 387 * We support up to 32GB of swap on 4k machines 388 */ 389 #define __swp_type(x) (((x).val >> 2) & 0x7f) 390 #define __swp_offset(x) ((x).val >> 9) 391 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) }) 392 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 393 #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) 394 395 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ 396 /* FIXME: this is not correct */ 397 #define kern_addr_valid(addr) (1) 398 399 #include <asm-generic/pgtable.h> 400 401 /* 402 * We provide our own arch_get_unmapped_area to cope with VIPT caches. 403 */ 404 #define HAVE_ARCH_UNMAPPED_AREA 405 406 /* 407 * remap a physical page `pfn' of size `size' with page protection `prot' 408 * into virtual address `from' 409 */ 410 #define io_remap_pfn_range(vma,from,pfn,size,prot) \ 411 remap_pfn_range(vma, from, pfn, size, prot) 412 413 #define pgtable_cache_init() do { } while (0) 414 415 #endif /* !__ASSEMBLY__ */ 416 417 #endif /* CONFIG_MMU */ 418 419 #endif /* _ASMARM_PGTABLE_H */ 420