xref: /openbmc/linux/arch/arm/include/asm/perf_event.h (revision e50c54189f7c6211a99539156e3978474f0b1a0b)
17ada189fSJamie Iles /*
27ada189fSJamie Iles  *  linux/arch/arm/include/asm/perf_event.h
37ada189fSJamie Iles  *
47ada189fSJamie Iles  *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
57ada189fSJamie Iles  *
67ada189fSJamie Iles  * This program is free software; you can redistribute it and/or modify
77ada189fSJamie Iles  * it under the terms of the GNU General Public License version 2 as
87ada189fSJamie Iles  * published by the Free Software Foundation.
97ada189fSJamie Iles  *
107ada189fSJamie Iles  */
117ada189fSJamie Iles 
127ada189fSJamie Iles #ifndef __ARM_PERF_EVENT_H__
137ada189fSJamie Iles #define __ARM_PERF_EVENT_H__
147ada189fSJamie Iles 
156dbc0029SWill Deacon /*
166dbc0029SWill Deacon  * The ARMv7 CPU PMU supports up to 32 event counters.
176dbc0029SWill Deacon  */
186dbc0029SWill Deacon #define ARMPMU_MAX_HWEVENTS		32
196dbc0029SWill Deacon 
206dbc0029SWill Deacon #define HW_OP_UNSUPPORTED		0xFFFF
216dbc0029SWill Deacon #define C(_x)				PERF_COUNT_HW_CACHE_##_x
226dbc0029SWill Deacon #define CACHE_OP_UNSUPPORTED		0xFFFF
23181193f3SWill Deacon 
24*e50c5418SMarc Zyngier struct pt_regs;
25*e50c5418SMarc Zyngier extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
26*e50c5418SMarc Zyngier extern unsigned long perf_misc_flags(struct pt_regs *regs);
27*e50c5418SMarc Zyngier #define perf_misc_flags(regs)	perf_misc_flags(regs)
28*e50c5418SMarc Zyngier 
297ada189fSJamie Iles #endif /* __ARM_PERF_EVENT_H__ */
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