1*7ada189fSJamie Iles /* 2*7ada189fSJamie Iles * linux/arch/arm/include/asm/perf_event.h 3*7ada189fSJamie Iles * 4*7ada189fSJamie Iles * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles 5*7ada189fSJamie Iles * 6*7ada189fSJamie Iles * This program is free software; you can redistribute it and/or modify 7*7ada189fSJamie Iles * it under the terms of the GNU General Public License version 2 as 8*7ada189fSJamie Iles * published by the Free Software Foundation. 9*7ada189fSJamie Iles * 10*7ada189fSJamie Iles */ 11*7ada189fSJamie Iles 12*7ada189fSJamie Iles #ifndef __ARM_PERF_EVENT_H__ 13*7ada189fSJamie Iles #define __ARM_PERF_EVENT_H__ 14*7ada189fSJamie Iles 15*7ada189fSJamie Iles /* 16*7ada189fSJamie Iles * NOP: on *most* (read: all supported) ARM platforms, the performance 17*7ada189fSJamie Iles * counter interrupts are regular interrupts and not an NMI. This 18*7ada189fSJamie Iles * means that when we receive the interrupt we can call 19*7ada189fSJamie Iles * perf_event_do_pending() that handles all of the work with 20*7ada189fSJamie Iles * interrupts enabled. 21*7ada189fSJamie Iles */ 22*7ada189fSJamie Iles static inline void 23*7ada189fSJamie Iles set_perf_event_pending(void) 24*7ada189fSJamie Iles { 25*7ada189fSJamie Iles } 26*7ada189fSJamie Iles 27*7ada189fSJamie Iles /* ARM performance counters start from 1 (in the cp15 accesses) so use the 28*7ada189fSJamie Iles * same indexes here for consistency. */ 29*7ada189fSJamie Iles #define PERF_EVENT_INDEX_OFFSET 1 30*7ada189fSJamie Iles 31*7ada189fSJamie Iles #endif /* __ARM_PERF_EVENT_H__ */ 32