xref: /openbmc/linux/arch/arm/include/asm/mcpm.h (revision de885d147ad2c4a66777e3557440247efde1cc8d)
1e8db288eSNicolas Pitre /*
2e8db288eSNicolas Pitre  * arch/arm/include/asm/mcpm.h
3e8db288eSNicolas Pitre  *
4e8db288eSNicolas Pitre  * Created by:  Nicolas Pitre, April 2012
5e8db288eSNicolas Pitre  * Copyright:   (C) 2012-2013  Linaro Limited
6e8db288eSNicolas Pitre  *
7e8db288eSNicolas Pitre  * This program is free software; you can redistribute it and/or modify
8e8db288eSNicolas Pitre  * it under the terms of the GNU General Public License version 2 as
9e8db288eSNicolas Pitre  * published by the Free Software Foundation.
10e8db288eSNicolas Pitre  */
11e8db288eSNicolas Pitre 
12e8db288eSNicolas Pitre #ifndef MCPM_H
13e8db288eSNicolas Pitre #define MCPM_H
14e8db288eSNicolas Pitre 
15e8db288eSNicolas Pitre /*
16e8db288eSNicolas Pitre  * Maximum number of possible clusters / CPUs per cluster.
17e8db288eSNicolas Pitre  *
18e8db288eSNicolas Pitre  * This should be sufficient for quite a while, while keeping the
19e8db288eSNicolas Pitre  * (assembly) code simpler.  When this starts to grow then we'll have
20e8db288eSNicolas Pitre  * to consider dynamic allocation.
21e8db288eSNicolas Pitre  */
22e8db288eSNicolas Pitre #define MAX_CPUS_PER_CLUSTER	4
23e8db288eSNicolas Pitre #define MAX_NR_CLUSTERS		2
24e8db288eSNicolas Pitre 
25e8db288eSNicolas Pitre #ifndef __ASSEMBLY__
26e8db288eSNicolas Pitre 
277fe31d28SDave Martin #include <linux/types.h>
287fe31d28SDave Martin #include <asm/cacheflush.h>
297fe31d28SDave Martin 
30e8db288eSNicolas Pitre /*
31e8db288eSNicolas Pitre  * Platform specific code should use this symbol to set up secondary
32e8db288eSNicolas Pitre  * entry location for processors to use when released from reset.
33e8db288eSNicolas Pitre  */
34e8db288eSNicolas Pitre extern void mcpm_entry_point(void);
35e8db288eSNicolas Pitre 
36e8db288eSNicolas Pitre /*
37e8db288eSNicolas Pitre  * This is used to indicate where the given CPU from given cluster should
38e8db288eSNicolas Pitre  * branch once it is ready to re-enter the kernel using ptr, or NULL if it
39e8db288eSNicolas Pitre  * should be gated.  A gated CPU is held in a WFE loop until its vector
40e8db288eSNicolas Pitre  * becomes non NULL.
41e8db288eSNicolas Pitre  */
42e8db288eSNicolas Pitre void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr);
43e8db288eSNicolas Pitre 
447c2b8605SNicolas Pitre /*
45*de885d14SNicolas Pitre  * This sets an early poke i.e a value to be poked into some address
46*de885d14SNicolas Pitre  * from very early assembly code before the CPU is ungated.  The
47*de885d14SNicolas Pitre  * address must be physical, and if 0 then nothing will happen.
48*de885d14SNicolas Pitre  */
49*de885d14SNicolas Pitre void mcpm_set_early_poke(unsigned cpu, unsigned cluster,
50*de885d14SNicolas Pitre 			 unsigned long poke_phys_addr, unsigned long poke_val);
51*de885d14SNicolas Pitre 
52*de885d14SNicolas Pitre /*
537c2b8605SNicolas Pitre  * CPU/cluster power operations API for higher subsystems to use.
547c2b8605SNicolas Pitre  */
557c2b8605SNicolas Pitre 
567c2b8605SNicolas Pitre /**
577c2b8605SNicolas Pitre  * mcpm_cpu_power_up - make given CPU in given cluster runable
587c2b8605SNicolas Pitre  *
597c2b8605SNicolas Pitre  * @cpu: CPU number within given cluster
607c2b8605SNicolas Pitre  * @cluster: cluster number for the CPU
617c2b8605SNicolas Pitre  *
627c2b8605SNicolas Pitre  * The identified CPU is brought out of reset.  If the cluster was powered
637c2b8605SNicolas Pitre  * down then it is brought up as well, taking care not to let the other CPUs
647c2b8605SNicolas Pitre  * in the cluster run, and ensuring appropriate cluster setup.
657c2b8605SNicolas Pitre  *
667c2b8605SNicolas Pitre  * Caller must ensure the appropriate entry vector is initialized with
677c2b8605SNicolas Pitre  * mcpm_set_entry_vector() prior to calling this.
687c2b8605SNicolas Pitre  *
697c2b8605SNicolas Pitre  * This must be called in a sleepable context.  However, the implementation
707c2b8605SNicolas Pitre  * is strongly encouraged to return early and let the operation happen
717c2b8605SNicolas Pitre  * asynchronously, especially when significant delays are expected.
727c2b8605SNicolas Pitre  *
737c2b8605SNicolas Pitre  * If the operation cannot be performed then an error code is returned.
747c2b8605SNicolas Pitre  */
757c2b8605SNicolas Pitre int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster);
767c2b8605SNicolas Pitre 
777c2b8605SNicolas Pitre /**
787c2b8605SNicolas Pitre  * mcpm_cpu_power_down - power the calling CPU down
797c2b8605SNicolas Pitre  *
807c2b8605SNicolas Pitre  * The calling CPU is powered down.
817c2b8605SNicolas Pitre  *
827c2b8605SNicolas Pitre  * If this CPU is found to be the "last man standing" in the cluster
837c2b8605SNicolas Pitre  * then the cluster is prepared for power-down too.
847c2b8605SNicolas Pitre  *
857c2b8605SNicolas Pitre  * This must be called with interrupts disabled.
867c2b8605SNicolas Pitre  *
877c2b8605SNicolas Pitre  * This does not return.  Re-entry in the kernel is expected via
887c2b8605SNicolas Pitre  * mcpm_entry_point.
897c2b8605SNicolas Pitre  */
907c2b8605SNicolas Pitre void mcpm_cpu_power_down(void);
917c2b8605SNicolas Pitre 
927c2b8605SNicolas Pitre /**
937c2b8605SNicolas Pitre  * mcpm_cpu_suspend - bring the calling CPU in a suspended state
947c2b8605SNicolas Pitre  *
957c2b8605SNicolas Pitre  * @expected_residency: duration in microseconds the CPU is expected
967c2b8605SNicolas Pitre  *			to remain suspended, or 0 if unknown/infinity.
977c2b8605SNicolas Pitre  *
987c2b8605SNicolas Pitre  * The calling CPU is suspended.  The expected residency argument is used
997c2b8605SNicolas Pitre  * as a hint by the platform specific backend to implement the appropriate
1007c2b8605SNicolas Pitre  * sleep state level according to the knowledge it has on wake-up latency
1017c2b8605SNicolas Pitre  * for the given hardware.
1027c2b8605SNicolas Pitre  *
1037c2b8605SNicolas Pitre  * If this CPU is found to be the "last man standing" in the cluster
1047c2b8605SNicolas Pitre  * then the cluster may be prepared for power-down too, if the expected
1057c2b8605SNicolas Pitre  * residency makes it worthwhile.
1067c2b8605SNicolas Pitre  *
1077c2b8605SNicolas Pitre  * This must be called with interrupts disabled.
1087c2b8605SNicolas Pitre  *
1097c2b8605SNicolas Pitre  * This does not return.  Re-entry in the kernel is expected via
1107c2b8605SNicolas Pitre  * mcpm_entry_point.
1117c2b8605SNicolas Pitre  */
1127c2b8605SNicolas Pitre void mcpm_cpu_suspend(u64 expected_residency);
1137c2b8605SNicolas Pitre 
1147c2b8605SNicolas Pitre /**
1157c2b8605SNicolas Pitre  * mcpm_cpu_powered_up - housekeeping workafter a CPU has been powered up
1167c2b8605SNicolas Pitre  *
1177c2b8605SNicolas Pitre  * This lets the platform specific backend code perform needed housekeeping
1187c2b8605SNicolas Pitre  * work.  This must be called by the newly activated CPU as soon as it is
1197c2b8605SNicolas Pitre  * fully operational in kernel space, before it enables interrupts.
1207c2b8605SNicolas Pitre  *
1217c2b8605SNicolas Pitre  * If the operation cannot be performed then an error code is returned.
1227c2b8605SNicolas Pitre  */
1237c2b8605SNicolas Pitre int mcpm_cpu_powered_up(void);
1247c2b8605SNicolas Pitre 
1257c2b8605SNicolas Pitre /*
1267c2b8605SNicolas Pitre  * Platform specific methods used in the implementation of the above API.
1277c2b8605SNicolas Pitre  */
1287c2b8605SNicolas Pitre struct mcpm_platform_ops {
1297c2b8605SNicolas Pitre 	int (*power_up)(unsigned int cpu, unsigned int cluster);
1307c2b8605SNicolas Pitre 	void (*power_down)(void);
1317c2b8605SNicolas Pitre 	void (*suspend)(u64);
1327c2b8605SNicolas Pitre 	void (*powered_up)(void);
1337c2b8605SNicolas Pitre };
1347c2b8605SNicolas Pitre 
1357c2b8605SNicolas Pitre /**
1367c2b8605SNicolas Pitre  * mcpm_platform_register - register platform specific power methods
1377c2b8605SNicolas Pitre  *
1387c2b8605SNicolas Pitre  * @ops: mcpm_platform_ops structure to register
1397c2b8605SNicolas Pitre  *
1407c2b8605SNicolas Pitre  * An error is returned if the registration has been done previously.
1417c2b8605SNicolas Pitre  */
1427c2b8605SNicolas Pitre int __init mcpm_platform_register(const struct mcpm_platform_ops *ops);
1437c2b8605SNicolas Pitre 
1447fe31d28SDave Martin /* Synchronisation structures for coordinating safe cluster setup/teardown: */
1457fe31d28SDave Martin 
1467fe31d28SDave Martin /*
1477fe31d28SDave Martin  * When modifying this structure, make sure you update the MCPM_SYNC_ defines
1487fe31d28SDave Martin  * to match.
1497fe31d28SDave Martin  */
1507fe31d28SDave Martin struct mcpm_sync_struct {
1517fe31d28SDave Martin 	/* individual CPU states */
1527fe31d28SDave Martin 	struct {
1537fe31d28SDave Martin 		s8 cpu __aligned(__CACHE_WRITEBACK_GRANULE);
1547fe31d28SDave Martin 	} cpus[MAX_CPUS_PER_CLUSTER];
1557fe31d28SDave Martin 
1567fe31d28SDave Martin 	/* cluster state */
1577fe31d28SDave Martin 	s8 cluster __aligned(__CACHE_WRITEBACK_GRANULE);
1587fe31d28SDave Martin 
1597fe31d28SDave Martin 	/* inbound-side state */
1607fe31d28SDave Martin 	s8 inbound __aligned(__CACHE_WRITEBACK_GRANULE);
1617fe31d28SDave Martin };
1627fe31d28SDave Martin 
1637fe31d28SDave Martin struct sync_struct {
1647fe31d28SDave Martin 	struct mcpm_sync_struct clusters[MAX_NR_CLUSTERS];
1657fe31d28SDave Martin };
1667fe31d28SDave Martin 
1677fe31d28SDave Martin extern unsigned long sync_phys;	/* physical address of *mcpm_sync */
1687fe31d28SDave Martin 
1697fe31d28SDave Martin void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster);
1707fe31d28SDave Martin void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster);
1717fe31d28SDave Martin void __mcpm_outbound_leave_critical(unsigned int cluster, int state);
1727fe31d28SDave Martin bool __mcpm_outbound_enter_critical(unsigned int this_cpu, unsigned int cluster);
1737fe31d28SDave Martin int __mcpm_cluster_state(unsigned int cluster);
1747fe31d28SDave Martin 
1757fe31d28SDave Martin int __init mcpm_sync_init(
1767fe31d28SDave Martin 	void (*power_up_setup)(unsigned int affinity_level));
1777fe31d28SDave Martin 
178a7eb7c6fSNicolas Pitre void __init mcpm_smp_set_ops(void);
179a7eb7c6fSNicolas Pitre 
1807fe31d28SDave Martin #else
1817fe31d28SDave Martin 
1827fe31d28SDave Martin /*
1837fe31d28SDave Martin  * asm-offsets.h causes trouble when included in .c files, and cacheflush.h
1847fe31d28SDave Martin  * cannot be included in asm files.  Let's work around the conflict like this.
1857fe31d28SDave Martin  */
1867fe31d28SDave Martin #include <asm/asm-offsets.h>
1877fe31d28SDave Martin #define __CACHE_WRITEBACK_GRANULE CACHE_WRITEBACK_GRANULE
1887fe31d28SDave Martin 
189e8db288eSNicolas Pitre #endif /* ! __ASSEMBLY__ */
1907fe31d28SDave Martin 
1917fe31d28SDave Martin /* Definitions for mcpm_sync_struct */
1927fe31d28SDave Martin #define CPU_DOWN		0x11
1937fe31d28SDave Martin #define CPU_COMING_UP		0x12
1947fe31d28SDave Martin #define CPU_UP			0x13
1957fe31d28SDave Martin #define CPU_GOING_DOWN		0x14
1967fe31d28SDave Martin 
1977fe31d28SDave Martin #define CLUSTER_DOWN		0x21
1987fe31d28SDave Martin #define CLUSTER_UP		0x22
1997fe31d28SDave Martin #define CLUSTER_GOING_DOWN	0x23
2007fe31d28SDave Martin 
2017fe31d28SDave Martin #define INBOUND_NOT_COMING_UP	0x31
2027fe31d28SDave Martin #define INBOUND_COMING_UP	0x32
2037fe31d28SDave Martin 
2047fe31d28SDave Martin /*
2057fe31d28SDave Martin  * Offsets for the mcpm_sync_struct members, for use in asm.
2067fe31d28SDave Martin  * We don't want to make them global to the kernel via asm-offsets.c.
2077fe31d28SDave Martin  */
2087fe31d28SDave Martin #define MCPM_SYNC_CLUSTER_CPUS	0
2097fe31d28SDave Martin #define MCPM_SYNC_CPU_SIZE	__CACHE_WRITEBACK_GRANULE
2107fe31d28SDave Martin #define MCPM_SYNC_CLUSTER_CLUSTER \
2117fe31d28SDave Martin 	(MCPM_SYNC_CLUSTER_CPUS + MCPM_SYNC_CPU_SIZE * MAX_CPUS_PER_CLUSTER)
2127fe31d28SDave Martin #define MCPM_SYNC_CLUSTER_INBOUND \
2137fe31d28SDave Martin 	(MCPM_SYNC_CLUSTER_CLUSTER + __CACHE_WRITEBACK_GRANULE)
2147fe31d28SDave Martin #define MCPM_SYNC_CLUSTER_SIZE \
2157fe31d28SDave Martin 	(MCPM_SYNC_CLUSTER_INBOUND + __CACHE_WRITEBACK_GRANULE)
2167fe31d28SDave Martin 
217e8db288eSNicolas Pitre #endif
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