xref: /openbmc/linux/arch/arm/include/asm/mcpm.h (revision 7fe31d28e839f9565c8176ec584676a045970802)
1e8db288eSNicolas Pitre /*
2e8db288eSNicolas Pitre  * arch/arm/include/asm/mcpm.h
3e8db288eSNicolas Pitre  *
4e8db288eSNicolas Pitre  * Created by:  Nicolas Pitre, April 2012
5e8db288eSNicolas Pitre  * Copyright:   (C) 2012-2013  Linaro Limited
6e8db288eSNicolas Pitre  *
7e8db288eSNicolas Pitre  * This program is free software; you can redistribute it and/or modify
8e8db288eSNicolas Pitre  * it under the terms of the GNU General Public License version 2 as
9e8db288eSNicolas Pitre  * published by the Free Software Foundation.
10e8db288eSNicolas Pitre  */
11e8db288eSNicolas Pitre 
12e8db288eSNicolas Pitre #ifndef MCPM_H
13e8db288eSNicolas Pitre #define MCPM_H
14e8db288eSNicolas Pitre 
15e8db288eSNicolas Pitre /*
16e8db288eSNicolas Pitre  * Maximum number of possible clusters / CPUs per cluster.
17e8db288eSNicolas Pitre  *
18e8db288eSNicolas Pitre  * This should be sufficient for quite a while, while keeping the
19e8db288eSNicolas Pitre  * (assembly) code simpler.  When this starts to grow then we'll have
20e8db288eSNicolas Pitre  * to consider dynamic allocation.
21e8db288eSNicolas Pitre  */
22e8db288eSNicolas Pitre #define MAX_CPUS_PER_CLUSTER	4
23e8db288eSNicolas Pitre #define MAX_NR_CLUSTERS		2
24e8db288eSNicolas Pitre 
25e8db288eSNicolas Pitre #ifndef __ASSEMBLY__
26e8db288eSNicolas Pitre 
27*7fe31d28SDave Martin #include <linux/types.h>
28*7fe31d28SDave Martin #include <asm/cacheflush.h>
29*7fe31d28SDave Martin 
30e8db288eSNicolas Pitre /*
31e8db288eSNicolas Pitre  * Platform specific code should use this symbol to set up secondary
32e8db288eSNicolas Pitre  * entry location for processors to use when released from reset.
33e8db288eSNicolas Pitre  */
34e8db288eSNicolas Pitre extern void mcpm_entry_point(void);
35e8db288eSNicolas Pitre 
36e8db288eSNicolas Pitre /*
37e8db288eSNicolas Pitre  * This is used to indicate where the given CPU from given cluster should
38e8db288eSNicolas Pitre  * branch once it is ready to re-enter the kernel using ptr, or NULL if it
39e8db288eSNicolas Pitre  * should be gated.  A gated CPU is held in a WFE loop until its vector
40e8db288eSNicolas Pitre  * becomes non NULL.
41e8db288eSNicolas Pitre  */
42e8db288eSNicolas Pitre void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr);
43e8db288eSNicolas Pitre 
447c2b8605SNicolas Pitre /*
457c2b8605SNicolas Pitre  * CPU/cluster power operations API for higher subsystems to use.
467c2b8605SNicolas Pitre  */
477c2b8605SNicolas Pitre 
487c2b8605SNicolas Pitre /**
497c2b8605SNicolas Pitre  * mcpm_cpu_power_up - make given CPU in given cluster runable
507c2b8605SNicolas Pitre  *
517c2b8605SNicolas Pitre  * @cpu: CPU number within given cluster
527c2b8605SNicolas Pitre  * @cluster: cluster number for the CPU
537c2b8605SNicolas Pitre  *
547c2b8605SNicolas Pitre  * The identified CPU is brought out of reset.  If the cluster was powered
557c2b8605SNicolas Pitre  * down then it is brought up as well, taking care not to let the other CPUs
567c2b8605SNicolas Pitre  * in the cluster run, and ensuring appropriate cluster setup.
577c2b8605SNicolas Pitre  *
587c2b8605SNicolas Pitre  * Caller must ensure the appropriate entry vector is initialized with
597c2b8605SNicolas Pitre  * mcpm_set_entry_vector() prior to calling this.
607c2b8605SNicolas Pitre  *
617c2b8605SNicolas Pitre  * This must be called in a sleepable context.  However, the implementation
627c2b8605SNicolas Pitre  * is strongly encouraged to return early and let the operation happen
637c2b8605SNicolas Pitre  * asynchronously, especially when significant delays are expected.
647c2b8605SNicolas Pitre  *
657c2b8605SNicolas Pitre  * If the operation cannot be performed then an error code is returned.
667c2b8605SNicolas Pitre  */
677c2b8605SNicolas Pitre int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster);
687c2b8605SNicolas Pitre 
697c2b8605SNicolas Pitre /**
707c2b8605SNicolas Pitre  * mcpm_cpu_power_down - power the calling CPU down
717c2b8605SNicolas Pitre  *
727c2b8605SNicolas Pitre  * The calling CPU is powered down.
737c2b8605SNicolas Pitre  *
747c2b8605SNicolas Pitre  * If this CPU is found to be the "last man standing" in the cluster
757c2b8605SNicolas Pitre  * then the cluster is prepared for power-down too.
767c2b8605SNicolas Pitre  *
777c2b8605SNicolas Pitre  * This must be called with interrupts disabled.
787c2b8605SNicolas Pitre  *
797c2b8605SNicolas Pitre  * This does not return.  Re-entry in the kernel is expected via
807c2b8605SNicolas Pitre  * mcpm_entry_point.
817c2b8605SNicolas Pitre  */
827c2b8605SNicolas Pitre void mcpm_cpu_power_down(void);
837c2b8605SNicolas Pitre 
847c2b8605SNicolas Pitre /**
857c2b8605SNicolas Pitre  * mcpm_cpu_suspend - bring the calling CPU in a suspended state
867c2b8605SNicolas Pitre  *
877c2b8605SNicolas Pitre  * @expected_residency: duration in microseconds the CPU is expected
887c2b8605SNicolas Pitre  *			to remain suspended, or 0 if unknown/infinity.
897c2b8605SNicolas Pitre  *
907c2b8605SNicolas Pitre  * The calling CPU is suspended.  The expected residency argument is used
917c2b8605SNicolas Pitre  * as a hint by the platform specific backend to implement the appropriate
927c2b8605SNicolas Pitre  * sleep state level according to the knowledge it has on wake-up latency
937c2b8605SNicolas Pitre  * for the given hardware.
947c2b8605SNicolas Pitre  *
957c2b8605SNicolas Pitre  * If this CPU is found to be the "last man standing" in the cluster
967c2b8605SNicolas Pitre  * then the cluster may be prepared for power-down too, if the expected
977c2b8605SNicolas Pitre  * residency makes it worthwhile.
987c2b8605SNicolas Pitre  *
997c2b8605SNicolas Pitre  * This must be called with interrupts disabled.
1007c2b8605SNicolas Pitre  *
1017c2b8605SNicolas Pitre  * This does not return.  Re-entry in the kernel is expected via
1027c2b8605SNicolas Pitre  * mcpm_entry_point.
1037c2b8605SNicolas Pitre  */
1047c2b8605SNicolas Pitre void mcpm_cpu_suspend(u64 expected_residency);
1057c2b8605SNicolas Pitre 
1067c2b8605SNicolas Pitre /**
1077c2b8605SNicolas Pitre  * mcpm_cpu_powered_up - housekeeping workafter a CPU has been powered up
1087c2b8605SNicolas Pitre  *
1097c2b8605SNicolas Pitre  * This lets the platform specific backend code perform needed housekeeping
1107c2b8605SNicolas Pitre  * work.  This must be called by the newly activated CPU as soon as it is
1117c2b8605SNicolas Pitre  * fully operational in kernel space, before it enables interrupts.
1127c2b8605SNicolas Pitre  *
1137c2b8605SNicolas Pitre  * If the operation cannot be performed then an error code is returned.
1147c2b8605SNicolas Pitre  */
1157c2b8605SNicolas Pitre int mcpm_cpu_powered_up(void);
1167c2b8605SNicolas Pitre 
1177c2b8605SNicolas Pitre /*
1187c2b8605SNicolas Pitre  * Platform specific methods used in the implementation of the above API.
1197c2b8605SNicolas Pitre  */
1207c2b8605SNicolas Pitre struct mcpm_platform_ops {
1217c2b8605SNicolas Pitre 	int (*power_up)(unsigned int cpu, unsigned int cluster);
1227c2b8605SNicolas Pitre 	void (*power_down)(void);
1237c2b8605SNicolas Pitre 	void (*suspend)(u64);
1247c2b8605SNicolas Pitre 	void (*powered_up)(void);
1257c2b8605SNicolas Pitre };
1267c2b8605SNicolas Pitre 
1277c2b8605SNicolas Pitre /**
1287c2b8605SNicolas Pitre  * mcpm_platform_register - register platform specific power methods
1297c2b8605SNicolas Pitre  *
1307c2b8605SNicolas Pitre  * @ops: mcpm_platform_ops structure to register
1317c2b8605SNicolas Pitre  *
1327c2b8605SNicolas Pitre  * An error is returned if the registration has been done previously.
1337c2b8605SNicolas Pitre  */
1347c2b8605SNicolas Pitre int __init mcpm_platform_register(const struct mcpm_platform_ops *ops);
1357c2b8605SNicolas Pitre 
136*7fe31d28SDave Martin /* Synchronisation structures for coordinating safe cluster setup/teardown: */
137*7fe31d28SDave Martin 
138*7fe31d28SDave Martin /*
139*7fe31d28SDave Martin  * When modifying this structure, make sure you update the MCPM_SYNC_ defines
140*7fe31d28SDave Martin  * to match.
141*7fe31d28SDave Martin  */
142*7fe31d28SDave Martin struct mcpm_sync_struct {
143*7fe31d28SDave Martin 	/* individual CPU states */
144*7fe31d28SDave Martin 	struct {
145*7fe31d28SDave Martin 		s8 cpu __aligned(__CACHE_WRITEBACK_GRANULE);
146*7fe31d28SDave Martin 	} cpus[MAX_CPUS_PER_CLUSTER];
147*7fe31d28SDave Martin 
148*7fe31d28SDave Martin 	/* cluster state */
149*7fe31d28SDave Martin 	s8 cluster __aligned(__CACHE_WRITEBACK_GRANULE);
150*7fe31d28SDave Martin 
151*7fe31d28SDave Martin 	/* inbound-side state */
152*7fe31d28SDave Martin 	s8 inbound __aligned(__CACHE_WRITEBACK_GRANULE);
153*7fe31d28SDave Martin };
154*7fe31d28SDave Martin 
155*7fe31d28SDave Martin struct sync_struct {
156*7fe31d28SDave Martin 	struct mcpm_sync_struct clusters[MAX_NR_CLUSTERS];
157*7fe31d28SDave Martin };
158*7fe31d28SDave Martin 
159*7fe31d28SDave Martin extern unsigned long sync_phys;	/* physical address of *mcpm_sync */
160*7fe31d28SDave Martin 
161*7fe31d28SDave Martin void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster);
162*7fe31d28SDave Martin void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster);
163*7fe31d28SDave Martin void __mcpm_outbound_leave_critical(unsigned int cluster, int state);
164*7fe31d28SDave Martin bool __mcpm_outbound_enter_critical(unsigned int this_cpu, unsigned int cluster);
165*7fe31d28SDave Martin int __mcpm_cluster_state(unsigned int cluster);
166*7fe31d28SDave Martin 
167*7fe31d28SDave Martin int __init mcpm_sync_init(
168*7fe31d28SDave Martin 	void (*power_up_setup)(unsigned int affinity_level));
169*7fe31d28SDave Martin 
170*7fe31d28SDave Martin #else
171*7fe31d28SDave Martin 
172*7fe31d28SDave Martin /*
173*7fe31d28SDave Martin  * asm-offsets.h causes trouble when included in .c files, and cacheflush.h
174*7fe31d28SDave Martin  * cannot be included in asm files.  Let's work around the conflict like this.
175*7fe31d28SDave Martin  */
176*7fe31d28SDave Martin #include <asm/asm-offsets.h>
177*7fe31d28SDave Martin #define __CACHE_WRITEBACK_GRANULE CACHE_WRITEBACK_GRANULE
178*7fe31d28SDave Martin 
179e8db288eSNicolas Pitre #endif /* ! __ASSEMBLY__ */
180*7fe31d28SDave Martin 
181*7fe31d28SDave Martin /* Definitions for mcpm_sync_struct */
182*7fe31d28SDave Martin #define CPU_DOWN		0x11
183*7fe31d28SDave Martin #define CPU_COMING_UP		0x12
184*7fe31d28SDave Martin #define CPU_UP			0x13
185*7fe31d28SDave Martin #define CPU_GOING_DOWN		0x14
186*7fe31d28SDave Martin 
187*7fe31d28SDave Martin #define CLUSTER_DOWN		0x21
188*7fe31d28SDave Martin #define CLUSTER_UP		0x22
189*7fe31d28SDave Martin #define CLUSTER_GOING_DOWN	0x23
190*7fe31d28SDave Martin 
191*7fe31d28SDave Martin #define INBOUND_NOT_COMING_UP	0x31
192*7fe31d28SDave Martin #define INBOUND_COMING_UP	0x32
193*7fe31d28SDave Martin 
194*7fe31d28SDave Martin /*
195*7fe31d28SDave Martin  * Offsets for the mcpm_sync_struct members, for use in asm.
196*7fe31d28SDave Martin  * We don't want to make them global to the kernel via asm-offsets.c.
197*7fe31d28SDave Martin  */
198*7fe31d28SDave Martin #define MCPM_SYNC_CLUSTER_CPUS	0
199*7fe31d28SDave Martin #define MCPM_SYNC_CPU_SIZE	__CACHE_WRITEBACK_GRANULE
200*7fe31d28SDave Martin #define MCPM_SYNC_CLUSTER_CLUSTER \
201*7fe31d28SDave Martin 	(MCPM_SYNC_CLUSTER_CPUS + MCPM_SYNC_CPU_SIZE * MAX_CPUS_PER_CLUSTER)
202*7fe31d28SDave Martin #define MCPM_SYNC_CLUSTER_INBOUND \
203*7fe31d28SDave Martin 	(MCPM_SYNC_CLUSTER_CLUSTER + __CACHE_WRITEBACK_GRANULE)
204*7fe31d28SDave Martin #define MCPM_SYNC_CLUSTER_SIZE \
205*7fe31d28SDave Martin 	(MCPM_SYNC_CLUSTER_INBOUND + __CACHE_WRITEBACK_GRANULE)
206*7fe31d28SDave Martin 
207e8db288eSNicolas Pitre #endif
208