1*d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2753790e7SRussell King /*
3753790e7SRussell King * arch/arm/include/asm/glue-cache.h
4753790e7SRussell King *
5753790e7SRussell King * Copyright (C) 1999-2002 Russell King
6753790e7SRussell King */
7753790e7SRussell King #ifndef ASM_GLUE_CACHE_H
8753790e7SRussell King #define ASM_GLUE_CACHE_H
9753790e7SRussell King
10753790e7SRussell King #include <asm/glue.h>
11753790e7SRussell King
12753790e7SRussell King /*
13753790e7SRussell King * Cache Model
14753790e7SRussell King * ===========
15753790e7SRussell King */
16753790e7SRussell King #undef _CACHE
17753790e7SRussell King #undef MULTI_CACHE
18753790e7SRussell King
19753790e7SRussell King #if defined(CONFIG_CPU_CACHE_V4)
20753790e7SRussell King # ifdef _CACHE
21753790e7SRussell King # define MULTI_CACHE 1
22753790e7SRussell King # else
23753790e7SRussell King # define _CACHE v4
24753790e7SRussell King # endif
25753790e7SRussell King #endif
26753790e7SRussell King
27753790e7SRussell King #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
28753790e7SRussell King defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
29753790e7SRussell King defined(CONFIG_CPU_ARM1026)
30753790e7SRussell King # define MULTI_CACHE 1
31753790e7SRussell King #endif
32753790e7SRussell King
33753790e7SRussell King #if defined(CONFIG_CPU_FA526)
34753790e7SRussell King # ifdef _CACHE
35753790e7SRussell King # define MULTI_CACHE 1
36753790e7SRussell King # else
37753790e7SRussell King # define _CACHE fa
38753790e7SRussell King # endif
39753790e7SRussell King #endif
40753790e7SRussell King
41753790e7SRussell King #if defined(CONFIG_CPU_ARM926T)
42753790e7SRussell King # ifdef _CACHE
43753790e7SRussell King # define MULTI_CACHE 1
44753790e7SRussell King # else
45753790e7SRussell King # define _CACHE arm926
46753790e7SRussell King # endif
47753790e7SRussell King #endif
48753790e7SRussell King
49753790e7SRussell King #if defined(CONFIG_CPU_ARM940T)
50753790e7SRussell King # ifdef _CACHE
51753790e7SRussell King # define MULTI_CACHE 1
52753790e7SRussell King # else
53753790e7SRussell King # define _CACHE arm940
54753790e7SRussell King # endif
55753790e7SRussell King #endif
56753790e7SRussell King
57753790e7SRussell King #if defined(CONFIG_CPU_ARM946E)
58753790e7SRussell King # ifdef _CACHE
59753790e7SRussell King # define MULTI_CACHE 1
60753790e7SRussell King # else
61753790e7SRussell King # define _CACHE arm946
62753790e7SRussell King # endif
63753790e7SRussell King #endif
64753790e7SRussell King
65753790e7SRussell King #if defined(CONFIG_CPU_CACHE_V4WB)
66753790e7SRussell King # ifdef _CACHE
67753790e7SRussell King # define MULTI_CACHE 1
68753790e7SRussell King # else
69753790e7SRussell King # define _CACHE v4wb
70753790e7SRussell King # endif
71753790e7SRussell King #endif
72753790e7SRussell King
73753790e7SRussell King #if defined(CONFIG_CPU_XSCALE)
74753790e7SRussell King # ifdef _CACHE
75753790e7SRussell King # define MULTI_CACHE 1
76753790e7SRussell King # else
77753790e7SRussell King # define _CACHE xscale
78753790e7SRussell King # endif
79753790e7SRussell King #endif
80753790e7SRussell King
81753790e7SRussell King #if defined(CONFIG_CPU_XSC3)
82753790e7SRussell King # ifdef _CACHE
83753790e7SRussell King # define MULTI_CACHE 1
84753790e7SRussell King # else
85753790e7SRussell King # define _CACHE xsc3
86753790e7SRussell King # endif
87753790e7SRussell King #endif
88753790e7SRussell King
89753790e7SRussell King #if defined(CONFIG_CPU_MOHAWK)
90753790e7SRussell King # ifdef _CACHE
91753790e7SRussell King # define MULTI_CACHE 1
92753790e7SRussell King # else
93753790e7SRussell King # define _CACHE mohawk
94753790e7SRussell King # endif
95753790e7SRussell King #endif
96753790e7SRussell King
97753790e7SRussell King #if defined(CONFIG_CPU_FEROCEON)
98753790e7SRussell King # define MULTI_CACHE 1
99753790e7SRussell King #endif
100753790e7SRussell King
101bd1274dcSRussell King #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
102a67e1ce1SRussell King # ifdef _CACHE
103753790e7SRussell King # define MULTI_CACHE 1
104a67e1ce1SRussell King # else
105a67e1ce1SRussell King # define _CACHE v6
106a67e1ce1SRussell King # endif
107753790e7SRussell King #endif
108753790e7SRussell King
109753790e7SRussell King #if defined(CONFIG_CPU_V7)
110a67e1ce1SRussell King # ifdef _CACHE
111753790e7SRussell King # define MULTI_CACHE 1
112a67e1ce1SRussell King # else
113a67e1ce1SRussell King # define _CACHE v7
114a67e1ce1SRussell King # endif
115753790e7SRussell King #endif
116753790e7SRussell King
117f6f9be1cSFlorian Fainelli #if defined(CONFIG_CACHE_B15_RAC)
118f6f9be1cSFlorian Fainelli # define MULTI_CACHE 1
119f6f9be1cSFlorian Fainelli #endif
120f6f9be1cSFlorian Fainelli
12155bdd694SCatalin Marinas #if defined(CONFIG_CPU_V7M)
12255bdd694SCatalin Marinas # define MULTI_CACHE 1
12355bdd694SCatalin Marinas #endif
12455bdd694SCatalin Marinas
125753790e7SRussell King #if !defined(_CACHE) && !defined(MULTI_CACHE)
12625985edcSLucas De Marchi #error Unknown cache maintenance model
127753790e7SRussell King #endif
128753790e7SRussell King
12955bdd694SCatalin Marinas #ifndef __ASSEMBLER__
nop_flush_icache_all(void)13076ae0382SBehan Webster static inline void nop_flush_icache_all(void) { }
nop_flush_kern_cache_all(void)13176ae0382SBehan Webster static inline void nop_flush_kern_cache_all(void) { }
nop_flush_kern_cache_louis(void)13276ae0382SBehan Webster static inline void nop_flush_kern_cache_louis(void) { }
nop_flush_user_cache_all(void)13376ae0382SBehan Webster static inline void nop_flush_user_cache_all(void) { }
nop_flush_user_cache_range(unsigned long a,unsigned long b,unsigned int c)13476ae0382SBehan Webster static inline void nop_flush_user_cache_range(unsigned long a,
13555bdd694SCatalin Marinas unsigned long b, unsigned int c) { }
13655bdd694SCatalin Marinas
nop_coherent_kern_range(unsigned long a,unsigned long b)13776ae0382SBehan Webster static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
nop_coherent_user_range(unsigned long a,unsigned long b)13876ae0382SBehan Webster static inline int nop_coherent_user_range(unsigned long a,
13955bdd694SCatalin Marinas unsigned long b) { return 0; }
nop_flush_kern_dcache_area(void * a,size_t s)14076ae0382SBehan Webster static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
14155bdd694SCatalin Marinas
nop_dma_flush_range(const void * a,const void * b)14276ae0382SBehan Webster static inline void nop_dma_flush_range(const void *a, const void *b) { }
14355bdd694SCatalin Marinas
nop_dma_map_area(const void * s,size_t l,int f)14476ae0382SBehan Webster static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
nop_dma_unmap_area(const void * s,size_t l,int f)14576ae0382SBehan Webster static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
14655bdd694SCatalin Marinas #endif
14755bdd694SCatalin Marinas
148753790e7SRussell King #ifndef MULTI_CACHE
149753790e7SRussell King #define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
150753790e7SRussell King #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
151031bd879SLorenzo Pieralisi #define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis)
152753790e7SRussell King #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
153753790e7SRussell King #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
154753790e7SRussell King #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
155753790e7SRussell King #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
156753790e7SRussell King #define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
157753790e7SRussell King
158753790e7SRussell King #define dmac_flush_range __glue(_CACHE,_dma_flush_range)
159753790e7SRussell King #endif
160753790e7SRussell King
161753790e7SRussell King #endif
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