1 /* 2 * arch/arm/include/asm/cacheflush.h 3 * 4 * Copyright (C) 1999-2002 Russell King 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 #ifndef _ASMARM_CACHEFLUSH_H 11 #define _ASMARM_CACHEFLUSH_H 12 13 #include <linux/mm.h> 14 15 #include <asm/glue.h> 16 #include <asm/shmparam.h> 17 #include <asm/cachetype.h> 18 19 #define CACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT) 20 21 /* 22 * Cache Model 23 * =========== 24 */ 25 #undef _CACHE 26 #undef MULTI_CACHE 27 28 #if defined(CONFIG_CPU_CACHE_V3) 29 # ifdef _CACHE 30 # define MULTI_CACHE 1 31 # else 32 # define _CACHE v3 33 # endif 34 #endif 35 36 #if defined(CONFIG_CPU_CACHE_V4) 37 # ifdef _CACHE 38 # define MULTI_CACHE 1 39 # else 40 # define _CACHE v4 41 # endif 42 #endif 43 44 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \ 45 defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) 46 # define MULTI_CACHE 1 47 #endif 48 49 #if defined(CONFIG_CPU_ARM926T) 50 # ifdef _CACHE 51 # define MULTI_CACHE 1 52 # else 53 # define _CACHE arm926 54 # endif 55 #endif 56 57 #if defined(CONFIG_CPU_ARM940T) 58 # ifdef _CACHE 59 # define MULTI_CACHE 1 60 # else 61 # define _CACHE arm940 62 # endif 63 #endif 64 65 #if defined(CONFIG_CPU_ARM946E) 66 # ifdef _CACHE 67 # define MULTI_CACHE 1 68 # else 69 # define _CACHE arm946 70 # endif 71 #endif 72 73 #if defined(CONFIG_CPU_CACHE_V4WB) 74 # ifdef _CACHE 75 # define MULTI_CACHE 1 76 # else 77 # define _CACHE v4wb 78 # endif 79 #endif 80 81 #if defined(CONFIG_CPU_XSCALE) 82 # ifdef _CACHE 83 # define MULTI_CACHE 1 84 # else 85 # define _CACHE xscale 86 # endif 87 #endif 88 89 #if defined(CONFIG_CPU_XSC3) 90 # ifdef _CACHE 91 # define MULTI_CACHE 1 92 # else 93 # define _CACHE xsc3 94 # endif 95 #endif 96 97 #if defined(CONFIG_CPU_MOHAWK) 98 # ifdef _CACHE 99 # define MULTI_CACHE 1 100 # else 101 # define _CACHE mohawk 102 # endif 103 #endif 104 105 #if defined(CONFIG_CPU_FEROCEON) 106 # define MULTI_CACHE 1 107 #endif 108 109 #if defined(CONFIG_CPU_V6) 110 //# ifdef _CACHE 111 # define MULTI_CACHE 1 112 //# else 113 //# define _CACHE v6 114 //# endif 115 #endif 116 117 #if defined(CONFIG_CPU_V7) 118 //# ifdef _CACHE 119 # define MULTI_CACHE 1 120 //# else 121 //# define _CACHE v7 122 //# endif 123 #endif 124 125 #if !defined(_CACHE) && !defined(MULTI_CACHE) 126 #error Unknown cache maintainence model 127 #endif 128 129 /* 130 * This flag is used to indicate that the page pointed to by a pte 131 * is dirty and requires cleaning before returning it to the user. 132 */ 133 #define PG_dcache_dirty PG_arch_1 134 135 /* 136 * MM Cache Management 137 * =================== 138 * 139 * The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files 140 * implement these methods. 141 * 142 * Start addresses are inclusive and end addresses are exclusive; 143 * start addresses should be rounded down, end addresses up. 144 * 145 * See Documentation/cachetlb.txt for more information. 146 * Please note that the implementation of these, and the required 147 * effects are cache-type (VIVT/VIPT/PIPT) specific. 148 * 149 * flush_cache_kern_all() 150 * 151 * Unconditionally clean and invalidate the entire cache. 152 * 153 * flush_cache_user_mm(mm) 154 * 155 * Clean and invalidate all user space cache entries 156 * before a change of page tables. 157 * 158 * flush_cache_user_range(start, end, flags) 159 * 160 * Clean and invalidate a range of cache entries in the 161 * specified address space before a change of page tables. 162 * - start - user start address (inclusive, page aligned) 163 * - end - user end address (exclusive, page aligned) 164 * - flags - vma->vm_flags field 165 * 166 * coherent_kern_range(start, end) 167 * 168 * Ensure coherency between the Icache and the Dcache in the 169 * region described by start, end. If you have non-snooping 170 * Harvard caches, you need to implement this function. 171 * - start - virtual start address 172 * - end - virtual end address 173 * 174 * DMA Cache Coherency 175 * =================== 176 * 177 * dma_inv_range(start, end) 178 * 179 * Invalidate (discard) the specified virtual address range. 180 * May not write back any entries. If 'start' or 'end' 181 * are not cache line aligned, those lines must be written 182 * back. 183 * - start - virtual start address 184 * - end - virtual end address 185 * 186 * dma_clean_range(start, end) 187 * 188 * Clean (write back) the specified virtual address range. 189 * - start - virtual start address 190 * - end - virtual end address 191 * 192 * dma_flush_range(start, end) 193 * 194 * Clean and invalidate the specified virtual address range. 195 * - start - virtual start address 196 * - end - virtual end address 197 */ 198 199 struct cpu_cache_fns { 200 void (*flush_kern_all)(void); 201 void (*flush_user_all)(void); 202 void (*flush_user_range)(unsigned long, unsigned long, unsigned int); 203 204 void (*coherent_kern_range)(unsigned long, unsigned long); 205 void (*coherent_user_range)(unsigned long, unsigned long); 206 void (*flush_kern_dcache_page)(void *); 207 208 void (*dma_inv_range)(const void *, const void *); 209 void (*dma_clean_range)(const void *, const void *); 210 void (*dma_flush_range)(const void *, const void *); 211 }; 212 213 struct outer_cache_fns { 214 void (*inv_range)(unsigned long, unsigned long); 215 void (*clean_range)(unsigned long, unsigned long); 216 void (*flush_range)(unsigned long, unsigned long); 217 }; 218 219 /* 220 * Select the calling method 221 */ 222 #ifdef MULTI_CACHE 223 224 extern struct cpu_cache_fns cpu_cache; 225 226 #define __cpuc_flush_kern_all cpu_cache.flush_kern_all 227 #define __cpuc_flush_user_all cpu_cache.flush_user_all 228 #define __cpuc_flush_user_range cpu_cache.flush_user_range 229 #define __cpuc_coherent_kern_range cpu_cache.coherent_kern_range 230 #define __cpuc_coherent_user_range cpu_cache.coherent_user_range 231 #define __cpuc_flush_dcache_page cpu_cache.flush_kern_dcache_page 232 233 /* 234 * These are private to the dma-mapping API. Do not use directly. 235 * Their sole purpose is to ensure that data held in the cache 236 * is visible to DMA, or data written by DMA to system memory is 237 * visible to the CPU. 238 */ 239 #define dmac_inv_range cpu_cache.dma_inv_range 240 #define dmac_clean_range cpu_cache.dma_clean_range 241 #define dmac_flush_range cpu_cache.dma_flush_range 242 243 #else 244 245 #define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) 246 #define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) 247 #define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) 248 #define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range) 249 #define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) 250 #define __cpuc_flush_dcache_page __glue(_CACHE,_flush_kern_dcache_page) 251 252 extern void __cpuc_flush_kern_all(void); 253 extern void __cpuc_flush_user_all(void); 254 extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); 255 extern void __cpuc_coherent_kern_range(unsigned long, unsigned long); 256 extern void __cpuc_coherent_user_range(unsigned long, unsigned long); 257 extern void __cpuc_flush_dcache_page(void *); 258 259 /* 260 * These are private to the dma-mapping API. Do not use directly. 261 * Their sole purpose is to ensure that data held in the cache 262 * is visible to DMA, or data written by DMA to system memory is 263 * visible to the CPU. 264 */ 265 #define dmac_inv_range __glue(_CACHE,_dma_inv_range) 266 #define dmac_clean_range __glue(_CACHE,_dma_clean_range) 267 #define dmac_flush_range __glue(_CACHE,_dma_flush_range) 268 269 extern void dmac_inv_range(const void *, const void *); 270 extern void dmac_clean_range(const void *, const void *); 271 extern void dmac_flush_range(const void *, const void *); 272 273 #endif 274 275 #ifdef CONFIG_OUTER_CACHE 276 277 extern struct outer_cache_fns outer_cache; 278 279 static inline void outer_inv_range(unsigned long start, unsigned long end) 280 { 281 if (outer_cache.inv_range) 282 outer_cache.inv_range(start, end); 283 } 284 static inline void outer_clean_range(unsigned long start, unsigned long end) 285 { 286 if (outer_cache.clean_range) 287 outer_cache.clean_range(start, end); 288 } 289 static inline void outer_flush_range(unsigned long start, unsigned long end) 290 { 291 if (outer_cache.flush_range) 292 outer_cache.flush_range(start, end); 293 } 294 295 #else 296 297 static inline void outer_inv_range(unsigned long start, unsigned long end) 298 { } 299 static inline void outer_clean_range(unsigned long start, unsigned long end) 300 { } 301 static inline void outer_flush_range(unsigned long start, unsigned long end) 302 { } 303 304 #endif 305 306 /* 307 * Copy user data from/to a page which is mapped into a different 308 * processes address space. Really, we want to allow our "user 309 * space" model to handle this. 310 */ 311 #define copy_to_user_page(vma, page, vaddr, dst, src, len) \ 312 do { \ 313 memcpy(dst, src, len); \ 314 flush_ptrace_access(vma, page, vaddr, dst, len, 1);\ 315 } while (0) 316 317 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \ 318 do { \ 319 memcpy(dst, src, len); \ 320 } while (0) 321 322 /* 323 * Convert calls to our calling convention. 324 */ 325 #define flush_cache_all() __cpuc_flush_kern_all() 326 #ifndef CONFIG_CPU_CACHE_VIPT 327 static inline void flush_cache_mm(struct mm_struct *mm) 328 { 329 if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) 330 __cpuc_flush_user_all(); 331 } 332 333 static inline void 334 flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) 335 { 336 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) 337 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end), 338 vma->vm_flags); 339 } 340 341 static inline void 342 flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn) 343 { 344 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { 345 unsigned long addr = user_addr & PAGE_MASK; 346 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags); 347 } 348 } 349 350 static inline void 351 flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 352 unsigned long uaddr, void *kaddr, 353 unsigned long len, int write) 354 { 355 if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { 356 unsigned long addr = (unsigned long)kaddr; 357 __cpuc_coherent_kern_range(addr, addr + len); 358 } 359 } 360 #else 361 extern void flush_cache_mm(struct mm_struct *mm); 362 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); 363 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn); 364 extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 365 unsigned long uaddr, void *kaddr, 366 unsigned long len, int write); 367 #endif 368 369 #define flush_cache_dup_mm(mm) flush_cache_mm(mm) 370 371 /* 372 * flush_cache_user_range is used when we want to ensure that the 373 * Harvard caches are synchronised for the user space address range. 374 * This is used for the ARM private sys_cacheflush system call. 375 */ 376 #define flush_cache_user_range(vma,start,end) \ 377 __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end)) 378 379 /* 380 * Perform necessary cache operations to ensure that data previously 381 * stored within this range of addresses can be executed by the CPU. 382 */ 383 #define flush_icache_range(s,e) __cpuc_coherent_kern_range(s,e) 384 385 /* 386 * Perform necessary cache operations to ensure that the TLB will 387 * see data written in the specified area. 388 */ 389 #define clean_dcache_area(start,size) cpu_dcache_clean_area(start, size) 390 391 /* 392 * flush_dcache_page is used when the kernel has written to the page 393 * cache page at virtual address page->virtual. 394 * 395 * If this page isn't mapped (ie, page_mapping == NULL), or it might 396 * have userspace mappings, then we _must_ always clean + invalidate 397 * the dcache entries associated with the kernel mapping. 398 * 399 * Otherwise we can defer the operation, and clean the cache when we are 400 * about to change to user space. This is the same method as used on SPARC64. 401 * See update_mmu_cache for the user space part. 402 */ 403 extern void flush_dcache_page(struct page *); 404 405 extern void __flush_dcache_page(struct address_space *mapping, struct page *page); 406 407 static inline void __flush_icache_all(void) 408 { 409 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n" 410 : 411 : "r" (0)); 412 } 413 414 #define ARCH_HAS_FLUSH_ANON_PAGE 415 static inline void flush_anon_page(struct vm_area_struct *vma, 416 struct page *page, unsigned long vmaddr) 417 { 418 extern void __flush_anon_page(struct vm_area_struct *vma, 419 struct page *, unsigned long); 420 if (PageAnon(page)) 421 __flush_anon_page(vma, page, vmaddr); 422 } 423 424 #define flush_dcache_mmap_lock(mapping) \ 425 spin_lock_irq(&(mapping)->tree_lock) 426 #define flush_dcache_mmap_unlock(mapping) \ 427 spin_unlock_irq(&(mapping)->tree_lock) 428 429 #define flush_icache_user_range(vma,page,addr,len) \ 430 flush_dcache_page(page) 431 432 /* 433 * We don't appear to need to do anything here. In fact, if we did, we'd 434 * duplicate cache flushing elsewhere performed by flush_dcache_page(). 435 */ 436 #define flush_icache_page(vma,page) do { } while (0) 437 438 static inline void flush_ioremap_region(unsigned long phys, void __iomem *virt, 439 unsigned offset, size_t size) 440 { 441 const void *start = (void __force *)virt + offset; 442 dmac_inv_range(start, start + size); 443 } 444 445 /* 446 * flush_cache_vmap() is used when creating mappings (eg, via vmap, 447 * vmalloc, ioremap etc) in kernel space for pages. On non-VIPT 448 * caches, since the direct-mappings of these pages may contain cached 449 * data, we need to do a full cache flush to ensure that writebacks 450 * don't corrupt data placed into these pages via the new mappings. 451 */ 452 static inline void flush_cache_vmap(unsigned long start, unsigned long end) 453 { 454 if (!cache_is_vipt_nonaliasing()) 455 flush_cache_all(); 456 else 457 /* 458 * set_pte_at() called from vmap_pte_range() does not 459 * have a DSB after cleaning the cache line. 460 */ 461 dsb(); 462 } 463 464 static inline void flush_cache_vunmap(unsigned long start, unsigned long end) 465 { 466 if (!cache_is_vipt_nonaliasing()) 467 flush_cache_all(); 468 } 469 470 #endif 471