1*724ba675SRob Herring// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 4*724ba675SRob Herring * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring#include "stm32mp131.dtsi" 8*724ba675SRob Herring 9*724ba675SRob Herring/ { 10*724ba675SRob Herring soc { 11*724ba675SRob Herring m_can1: can@4400e000 { 12*724ba675SRob Herring compatible = "bosch,m_can"; 13*724ba675SRob Herring reg = <0x4400e000 0x400>, <0x44011000 0x1400>; 14*724ba675SRob Herring reg-names = "m_can", "message_ram"; 15*724ba675SRob Herring interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 16*724ba675SRob Herring <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 17*724ba675SRob Herring interrupt-names = "int0", "int1"; 18*724ba675SRob Herring clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; 19*724ba675SRob Herring clock-names = "hclk", "cclk"; 20*724ba675SRob Herring bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; 21*724ba675SRob Herring status = "disabled"; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring m_can2: can@4400f000 { 25*724ba675SRob Herring compatible = "bosch,m_can"; 26*724ba675SRob Herring reg = <0x4400f000 0x400>, <0x44011000 0x2800>; 27*724ba675SRob Herring reg-names = "m_can", "message_ram"; 28*724ba675SRob Herring interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 29*724ba675SRob Herring <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 30*724ba675SRob Herring interrupt-names = "int0", "int1"; 31*724ba675SRob Herring clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; 32*724ba675SRob Herring clock-names = "hclk", "cclk"; 33*724ba675SRob Herring bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; 34*724ba675SRob Herring status = "disabled"; 35*724ba675SRob Herring }; 36*724ba675SRob Herring 37*724ba675SRob Herring adc_1: adc@48003000 { 38*724ba675SRob Herring compatible = "st,stm32mp13-adc-core"; 39*724ba675SRob Herring reg = <0x48003000 0x400>; 40*724ba675SRob Herring interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 41*724ba675SRob Herring clocks = <&rcc ADC1>, <&rcc ADC1_K>; 42*724ba675SRob Herring clock-names = "bus", "adc"; 43*724ba675SRob Herring interrupt-controller; 44*724ba675SRob Herring #interrupt-cells = <1>; 45*724ba675SRob Herring #address-cells = <1>; 46*724ba675SRob Herring #size-cells = <0>; 47*724ba675SRob Herring status = "disabled"; 48*724ba675SRob Herring 49*724ba675SRob Herring adc1: adc@0 { 50*724ba675SRob Herring compatible = "st,stm32mp13-adc"; 51*724ba675SRob Herring #io-channel-cells = <1>; 52*724ba675SRob Herring #address-cells = <1>; 53*724ba675SRob Herring #size-cells = <0>; 54*724ba675SRob Herring reg = <0x0>; 55*724ba675SRob Herring interrupt-parent = <&adc_1>; 56*724ba675SRob Herring interrupts = <0>; 57*724ba675SRob Herring dmas = <&dmamux1 9 0x400 0x80000001>; 58*724ba675SRob Herring dma-names = "rx"; 59*724ba675SRob Herring status = "disabled"; 60*724ba675SRob Herring 61*724ba675SRob Herring channel@18 { 62*724ba675SRob Herring reg = <18>; 63*724ba675SRob Herring label = "vrefint"; 64*724ba675SRob Herring }; 65*724ba675SRob Herring }; 66*724ba675SRob Herring }; 67*724ba675SRob Herring }; 68*724ba675SRob Herring}; 69