1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0+ OR MIT 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device tree for Colibri VF61 Cortex-M4 support 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2015 Stefan Agner 6*724ba675SRob Herring */ 7*724ba675SRob Herring 8*724ba675SRob Herring/dts-v1/; 9*724ba675SRob Herring#include "vf610m4.dtsi" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring model = "VF610 Cortex-M4"; 13*724ba675SRob Herring compatible = "fsl,vf610m4"; 14*724ba675SRob Herring 15*724ba675SRob Herring chosen { 16*724ba675SRob Herring bootargs = "clk_ignore_unused init=/linuxrc rw"; 17*724ba675SRob Herring stdout-path = "serial2:115200"; 18*724ba675SRob Herring }; 19*724ba675SRob Herring 20*724ba675SRob Herring memory@8c000000 { 21*724ba675SRob Herring device_type = "memory"; 22*724ba675SRob Herring reg = <0x8c000000 0x3000000>; 23*724ba675SRob Herring }; 24*724ba675SRob Herring}; 25*724ba675SRob Herring 26*724ba675SRob Herring&gpio0 { 27*724ba675SRob Herring status = "disabled"; 28*724ba675SRob Herring}; 29*724ba675SRob Herring 30*724ba675SRob Herring&gpio1 { 31*724ba675SRob Herring status = "disabled"; 32*724ba675SRob Herring}; 33*724ba675SRob Herring 34*724ba675SRob Herring&gpio2 { 35*724ba675SRob Herring status = "disabled"; 36*724ba675SRob Herring}; 37*724ba675SRob Herring 38*724ba675SRob Herring&gpio3 { 39*724ba675SRob Herring status = "disabled"; 40*724ba675SRob Herring}; 41*724ba675SRob Herring 42*724ba675SRob Herring&gpio4 { 43*724ba675SRob Herring status = "disabled"; 44*724ba675SRob Herring}; 45*724ba675SRob Herring 46*724ba675SRob Herring&uart2 { 47*724ba675SRob Herring pinctrl-names = "default"; 48*724ba675SRob Herring pinctrl-0 = <&pinctrl_uart2>; 49*724ba675SRob Herring status = "okay"; 50*724ba675SRob Herring}; 51*724ba675SRob Herring 52*724ba675SRob Herring&iomuxc { 53*724ba675SRob Herring vf610-colibri { 54*724ba675SRob Herring pinctrl_uart2: uart2grp { 55*724ba675SRob Herring fsl,pins = < 56*724ba675SRob Herring VF610_PAD_PTD0__UART2_TX 0x21a2 57*724ba675SRob Herring VF610_PAD_PTD1__UART2_RX 0x21a1 58*724ba675SRob Herring VF610_PAD_PTD2__UART2_RTS 0x21a2 59*724ba675SRob Herring VF610_PAD_PTD3__UART2_CTS 0x21a1 60*724ba675SRob Herring >; 61*724ba675SRob Herring }; 62*724ba675SRob Herring }; 63*724ba675SRob Herring}; 64