1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright 2014 FEDEVEL, Inc. 4 * 5 * Author: Robert Nelson <robertcnelson@gmail.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10 11/ { 12 chosen { 13 stdout-path = &uart1; 14 }; 15 16 reg_3p3v: regulator-3p3v { 17 compatible = "regulator-fixed"; 18 regulator-name = "3P3V"; 19 regulator-min-microvolt = <3300000>; 20 regulator-max-microvolt = <3300000>; 21 regulator-always-on; 22 }; 23 24 reg_usbh1_vbus: regulator-usbh1-vbus { 25 compatible = "regulator-fixed"; 26 pinctrl-names = "default"; 27 regulator-name = "usbh1_vbus"; 28 regulator-min-microvolt = <5000000>; 29 regulator-max-microvolt = <5000000>; 30 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; 31 enable-active-high; 32 }; 33 34 reg_usb_otg_vbus: regulator-otg-vbus { 35 compatible = "regulator-fixed"; 36 pinctrl-names = "default"; 37 regulator-name = "usb_otg_vbus"; 38 regulator-min-microvolt = <5000000>; 39 regulator-max-microvolt = <5000000>; 40 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 41 enable-active-high; 42 }; 43 44 leds { 45 compatible = "gpio-leds"; 46 pinctrl-names = "default"; 47 pinctrl-0 = <&pinctrl_led>; 48 49 led0: led-usr { 50 label = "usr"; 51 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 52 default-state = "off"; 53 linux,default-trigger = "heartbeat"; 54 }; 55 }; 56 57 sound { 58 compatible = "fsl,imx6-rex-sgtl5000", 59 "fsl,imx-audio-sgtl5000"; 60 model = "imx6-rex-sgtl5000"; 61 ssi-controller = <&ssi1>; 62 audio-codec = <&codec>; 63 audio-routing = 64 "MIC_IN", "Mic Jack", 65 "Mic Jack", "Mic Bias", 66 "Headphone Jack", "HP_OUT"; 67 mux-int-port = <1>; 68 mux-ext-port = <3>; 69 }; 70}; 71 72&audmux { 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_audmux>; 75 status = "okay"; 76}; 77 78&ecspi2 { 79 cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 80 pinctrl-names = "default"; 81 pinctrl-0 = <&pinctrl_ecspi2>; 82 status = "okay"; 83}; 84 85&ecspi3 { 86 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_ecspi3>; 89 status = "okay"; 90}; 91 92&fec { 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_enet>; 95 phy-mode = "rgmii"; 96 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; 97 status = "okay"; 98}; 99 100&hdmi { 101 ddc-i2c-bus = <&i2c2>; 102 status = "okay"; 103}; 104 105&i2c1 { 106 clock-frequency = <100000>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_i2c1>; 109 status = "okay"; 110 111 codec: sgtl5000@a { 112 compatible = "fsl,sgtl5000"; 113 reg = <0x0a>; 114 clocks = <&clks IMX6QDL_CLK_CKO>; 115 VDDA-supply = <®_3p3v>; 116 VDDIO-supply = <®_3p3v>; 117 }; 118}; 119 120&i2c2 { 121 clock-frequency = <100000>; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_i2c2>; 124 status = "okay"; 125 126 pca9535: gpio-expander@27 { 127 compatible = "nxp,pca9535"; 128 reg = <0x27>; 129 gpio-controller; 130 #gpio-cells = <2>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_pca9535>; 133 interrupt-parent = <&gpio6>; 134 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 135 interrupt-controller; 136 #interrupt-cells = <2>; 137 }; 138 139 eeprom@57 { 140 compatible = "atmel,24c02"; 141 reg = <0x57>; 142 }; 143}; 144 145&i2c3 { 146 clock-frequency = <100000>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_i2c3>; 149 status = "okay"; 150}; 151 152&iomuxc { 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_hog>; 155 156 imx6qdl-rex { 157 pinctrl_hog: hoggrp { 158 fsl,pins = < 159 /* SGTL5000 sys_mclk */ 160 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0 161 >; 162 }; 163 164 pinctrl_audmux: audmuxgrp { 165 fsl,pins = < 166 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 167 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 168 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 169 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 170 >; 171 }; 172 173 pinctrl_ecspi2: ecspi2grp { 174 fsl,pins = < 175 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 176 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 177 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 178 /* CS */ 179 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1 180 >; 181 }; 182 183 pinctrl_ecspi3: ecspi3grp { 184 fsl,pins = < 185 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 186 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 187 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 188 /* CS */ 189 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 190 >; 191 }; 192 193 pinctrl_enet: enetgrp { 194 fsl,pins = < 195 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 196 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 197 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 198 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 199 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 200 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 201 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 202 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 203 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 204 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 205 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 206 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 207 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 208 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 209 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 210 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 211 /* Phy reset */ 212 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 213 >; 214 }; 215 216 pinctrl_i2c1: i2c1grp { 217 fsl,pins = < 218 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 219 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 220 >; 221 }; 222 223 pinctrl_i2c2: i2c2grp { 224 fsl,pins = < 225 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 226 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 227 >; 228 }; 229 230 pinctrl_i2c3: i2c3grp { 231 fsl,pins = < 232 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 233 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 234 >; 235 }; 236 237 pinctrl_led: ledgrp { 238 fsl,pins = < 239 /* user led */ 240 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 241 >; 242 }; 243 244 pinctrl_pca9535: pca9535grp { 245 fsl,pins = < 246 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x17059 247 >; 248 }; 249 250 pinctrl_uart1: uart1grp { 251 fsl,pins = < 252 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 253 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 254 >; 255 }; 256 257 pinctrl_uart2: uart2grp { 258 fsl,pins = < 259 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 260 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 261 >; 262 }; 263 264 pinctrl_usbh1: usbh1grp { 265 fsl,pins = < 266 /* power enable, high active */ 267 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0 268 >; 269 }; 270 271 pinctrl_usbotg: usbotggrp { 272 fsl,pins = < 273 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 274 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 275 /* power enable, high active */ 276 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0 277 >; 278 }; 279 280 pinctrl_usdhc2: usdhc2grp { 281 fsl,pins = < 282 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 283 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 284 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 285 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 286 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 287 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 288 /* CD */ 289 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 290 /* WP */ 291 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0 292 >; 293 }; 294 295 pinctrl_usdhc3: usdhc3grp { 296 fsl,pins = < 297 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 298 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 299 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 300 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 301 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 302 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 303 /* CD */ 304 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 305 /* WP */ 306 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0 307 >; 308 }; 309 }; 310}; 311 312&ssi1 { 313 status = "okay"; 314}; 315 316&uart1 { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_uart1>; 319 status = "okay"; 320}; 321 322&uart2 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_uart2>; 325 status = "okay"; 326}; 327 328&usbh1 { 329 vbus-supply = <®_usbh1_vbus>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_usbh1>; 332 status = "okay"; 333}; 334 335&usbotg { 336 vbus-supply = <®_usb_otg_vbus>; 337 pinctrl-names = "default"; 338 pinctrl-0 = <&pinctrl_usbotg>; 339 status = "okay"; 340}; 341 342&usdhc2 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_usdhc2>; 345 bus-width = <4>; 346 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 347 wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; 348 status = "okay"; 349}; 350 351&usdhc3 { 352 pinctrl-names = "default"; 353 pinctrl-0 = <&pinctrl_usdhc3>; 354 bus-width = <4>; 355 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; 356 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 357 status = "okay"; 358}; 359