xref: /openbmc/linux/arch/arm/boot/dts/nspire/nspire-cx.dts (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only
2*724ba675SRob Herring/*
3*724ba675SRob Herring *  linux/arch/arm/boot/nspire-cx.dts
4*724ba675SRob Herring *
5*724ba675SRob Herring *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
6*724ba675SRob Herring */
7*724ba675SRob Herring/dts-v1/;
8*724ba675SRob Herring
9*724ba675SRob Herring/include/ "nspire.dtsi"
10*724ba675SRob Herring
11*724ba675SRob Herring&lcd {
12*724ba675SRob Herring	port {
13*724ba675SRob Herring		clcd_pads: endpoint {
14*724ba675SRob Herring			remote-endpoint = <&panel_in>;
15*724ba675SRob Herring		};
16*724ba675SRob Herring	};
17*724ba675SRob Herring};
18*724ba675SRob Herring
19*724ba675SRob Herring&fast_timer {
20*724ba675SRob Herring	/* compatible = "arm,sp804", "arm,primecell"; */
21*724ba675SRob Herring};
22*724ba675SRob Herring
23*724ba675SRob Herring&uart {
24*724ba675SRob Herring	compatible = "arm,pl011", "arm,primecell";
25*724ba675SRob Herring
26*724ba675SRob Herring	clocks = <&uart_clk>, <&apb_pclk>;
27*724ba675SRob Herring	clock-names = "uart_clk", "apb_pclk";
28*724ba675SRob Herring};
29*724ba675SRob Herring
30*724ba675SRob Herring&timer0 {
31*724ba675SRob Herring	compatible = "arm,sp804", "arm,primecell";
32*724ba675SRob Herring};
33*724ba675SRob Herring
34*724ba675SRob Herring&timer1 {
35*724ba675SRob Herring	compatible = "arm,sp804", "arm,primecell";
36*724ba675SRob Herring};
37*724ba675SRob Herring
38*724ba675SRob Herring&base_clk {
39*724ba675SRob Herring	compatible = "lsi,nspire-cx-clock";
40*724ba675SRob Herring};
41*724ba675SRob Herring
42*724ba675SRob Herring&ahb_clk {
43*724ba675SRob Herring	compatible = "lsi,nspire-cx-ahb-divider";
44*724ba675SRob Herring};
45*724ba675SRob Herring
46*724ba675SRob Herring&keypad {
47*724ba675SRob Herring	linux,keymap = <
48*724ba675SRob Herring	0x0000001c 	0x0001001c 	0x00040039
49*724ba675SRob Herring	0x0005002c 	0x00060015 	0x0007000b
50*724ba675SRob Herring	0x0008000f 	0x0100002d 	0x01010011
51*724ba675SRob Herring	0x0102002f 	0x01030004 	0x01040016
52*724ba675SRob Herring	0x01050014 	0x0106001f 	0x01070002
53*724ba675SRob Herring	0x010a006a 	0x02000013 	0x02010010
54*724ba675SRob Herring	0x02020019 	0x02030007 	0x02040018
55*724ba675SRob Herring	0x02050031 	0x02060032 	0x02070005
56*724ba675SRob Herring	0x02080028 	0x0209006c 	0x03000026
57*724ba675SRob Herring	0x03010025 	0x03020024 	0x0303000a
58*724ba675SRob Herring	0x03040017 	0x03050023 	0x03060022
59*724ba675SRob Herring	0x03070008 	0x03080035 	0x03090069
60*724ba675SRob Herring	0x04000021 	0x04010012 	0x04020020
61*724ba675SRob Herring	0x0404002e 	0x04050030 	0x0406001e
62*724ba675SRob Herring	0x0407000d 	0x04080037 	0x04090067
63*724ba675SRob Herring	0x05010038 	0x0502000c 	0x0503001b
64*724ba675SRob Herring	0x05040034 	0x0505001a 	0x05060006
65*724ba675SRob Herring	0x05080027 	0x0509000e 	0x050a006f
66*724ba675SRob Herring	0x0600002b 	0x0602004e 	0x06030068
67*724ba675SRob Herring	0x06040003 	0x0605006d 	0x06060009
68*724ba675SRob Herring	0x06070001 	0x0609000f 	0x0708002a
69*724ba675SRob Herring	0x0709001d 	0x070a0033 	>;
70*724ba675SRob Herring};
71*724ba675SRob Herring
72*724ba675SRob Herring&vbus_reg {
73*724ba675SRob Herring	gpio = <&gpio 2 0>;
74*724ba675SRob Herring};
75*724ba675SRob Herring
76*724ba675SRob Herring/ {
77*724ba675SRob Herring	model = "TI-NSPIRE CX";
78*724ba675SRob Herring	compatible = "ti,nspire-cx";
79*724ba675SRob Herring
80*724ba675SRob Herring	memory {
81*724ba675SRob Herring		device_type = "memory";
82*724ba675SRob Herring		reg = <0x10000000 0x4000000>; /* 64 MB */
83*724ba675SRob Herring	};
84*724ba675SRob Herring
85*724ba675SRob Herring	uart_clk: uart_clk {
86*724ba675SRob Herring		#clock-cells = <0>;
87*724ba675SRob Herring		compatible = "fixed-clock";
88*724ba675SRob Herring		clock-frequency = <12000000>;
89*724ba675SRob Herring	};
90*724ba675SRob Herring
91*724ba675SRob Herring	ahb {
92*724ba675SRob Herring		#address-cells = <1>;
93*724ba675SRob Herring		#size-cells = <1>;
94*724ba675SRob Herring
95*724ba675SRob Herring		intc: interrupt-controller@dc000000 {
96*724ba675SRob Herring			compatible = "arm,pl190-vic";
97*724ba675SRob Herring			interrupt-controller;
98*724ba675SRob Herring			reg = <0xdc000000 0x1000>;
99*724ba675SRob Herring			#interrupt-cells = <1>;
100*724ba675SRob Herring		};
101*724ba675SRob Herring
102*724ba675SRob Herring		apb@90000000 {
103*724ba675SRob Herring			#address-cells = <1>;
104*724ba675SRob Herring			#size-cells = <1>;
105*724ba675SRob Herring
106*724ba675SRob Herring			i2c@90050000 {
107*724ba675SRob Herring				compatible = "snps,designware-i2c";
108*724ba675SRob Herring				reg = <0x90050000 0x1000>;
109*724ba675SRob Herring				interrupts = <20>;
110*724ba675SRob Herring			};
111*724ba675SRob Herring		};
112*724ba675SRob Herring	};
113*724ba675SRob Herring
114*724ba675SRob Herring	panel {
115*724ba675SRob Herring		compatible = "ti,nspire-cx-lcd-panel";
116*724ba675SRob Herring		port {
117*724ba675SRob Herring			panel_in: endpoint {
118*724ba675SRob Herring				remote-endpoint = <&clcd_pads>;
119*724ba675SRob Herring			};
120*724ba675SRob Herring		};
121*724ba675SRob Herring	};
122*724ba675SRob Herring	chosen {
123*724ba675SRob Herring		bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
124*724ba675SRob Herring	};
125*724ba675SRob Herring};
126