1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> 4*724ba675SRob Herring */ 5*724ba675SRob Herring 6*724ba675SRob Herring/include/ "nspire.dtsi" 7*724ba675SRob Herring 8*724ba675SRob Herring&lcd { 9*724ba675SRob Herring port { 10*724ba675SRob Herring clcd_pads: endpoint { 11*724ba675SRob Herring remote-endpoint = <&panel_in>; 12*724ba675SRob Herring }; 13*724ba675SRob Herring }; 14*724ba675SRob Herring}; 15*724ba675SRob Herring 16*724ba675SRob Herring&fast_timer { 17*724ba675SRob Herring /* compatible = "lsi,zevio-timer"; */ 18*724ba675SRob Herring reg = <0x90010000 0x1000>, <0x900a0010 0x8>; 19*724ba675SRob Herring}; 20*724ba675SRob Herring 21*724ba675SRob Herring&uart { 22*724ba675SRob Herring compatible = "ns16550"; 23*724ba675SRob Herring reg-shift = <2>; 24*724ba675SRob Herring reg-io-width = <4>; 25*724ba675SRob Herring clocks = <&apb_pclk>; 26*724ba675SRob Herring no-loopback-test; 27*724ba675SRob Herring}; 28*724ba675SRob Herring 29*724ba675SRob Herring&timer0 { 30*724ba675SRob Herring /* compatible = "lsi,zevio-timer"; */ 31*724ba675SRob Herring reg = <0x900c0000 0x1000>, <0x900a0018 0x8>; 32*724ba675SRob Herring}; 33*724ba675SRob Herring 34*724ba675SRob Herring&timer1 { 35*724ba675SRob Herring compatible = "lsi,zevio-timer"; 36*724ba675SRob Herring reg = <0x900d0000 0x1000>, <0x900a0020 0x8>; 37*724ba675SRob Herring}; 38*724ba675SRob Herring 39*724ba675SRob Herring&keypad { 40*724ba675SRob Herring active-low; 41*724ba675SRob Herring 42*724ba675SRob Herring}; 43*724ba675SRob Herring 44*724ba675SRob Herring&base_clk { 45*724ba675SRob Herring compatible = "lsi,nspire-classic-clock"; 46*724ba675SRob Herring}; 47*724ba675SRob Herring 48*724ba675SRob Herring&ahb_clk { 49*724ba675SRob Herring compatible = "lsi,nspire-classic-ahb-divider"; 50*724ba675SRob Herring}; 51*724ba675SRob Herring 52*724ba675SRob Herring 53*724ba675SRob Herring&vbus_reg { 54*724ba675SRob Herring gpio = <&gpio 5 0>; 55*724ba675SRob Herring}; 56*724ba675SRob Herring 57*724ba675SRob Herring/ { 58*724ba675SRob Herring memory { 59*724ba675SRob Herring device_type = "memory"; 60*724ba675SRob Herring reg = <0x10000000 0x2000000>; /* 32 MB */ 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring ahb { 64*724ba675SRob Herring #address-cells = <1>; 65*724ba675SRob Herring #size-cells = <1>; 66*724ba675SRob Herring 67*724ba675SRob Herring intc: interrupt-controller@dc000000 { 68*724ba675SRob Herring compatible = "lsi,zevio-intc"; 69*724ba675SRob Herring interrupt-controller; 70*724ba675SRob Herring reg = <0xdc000000 0x1000>; 71*724ba675SRob Herring #interrupt-cells = <1>; 72*724ba675SRob Herring }; 73*724ba675SRob Herring }; 74*724ba675SRob Herring 75*724ba675SRob Herring panel { 76*724ba675SRob Herring compatible = "ti,nspire-classic-lcd-panel"; 77*724ba675SRob Herring port { 78*724ba675SRob Herring panel_in: endpoint { 79*724ba675SRob Herring remote-endpoint = <&clcd_pads>; 80*724ba675SRob Herring }; 81*724ba675SRob Herring }; 82*724ba675SRob Herring }; 83*724ba675SRob Herring chosen { 84*724ba675SRob Herring bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0"; 85*724ba675SRob Herring }; 86*724ba675SRob Herring}; 87