1*724ba675SRob Herring// SPDX-License-Identifier: ISC 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Device Tree file for the Intel IXDPG425 reference design. 4*724ba675SRob Herring * Derived from boardfiles written by MontaVista software. 5*724ba675SRob Herring * Ethernet set-up from OpenWrt. 6*724ba675SRob Herring * 7*724ba675SRob Herring * The device has 4 x FXS RJ11 ports for analog phones for 8*724ba675SRob Herring * internet telephony. (Not supported yet.) 9*724ba675SRob Herring * 10*724ba675SRob Herring * The device has 9 status LEDs we do not support yet. 11*724ba675SRob Herring * 12*724ba675SRob Herring * This device is very similar to ADI engingeering Coyote. 13*724ba675SRob Herring */ 14*724ba675SRob Herring 15*724ba675SRob Herring/dts-v1/; 16*724ba675SRob Herring 17*724ba675SRob Herring#include "intel-ixp42x.dtsi" 18*724ba675SRob Herring#include <dt-bindings/input/input.h> 19*724ba675SRob Herring 20*724ba675SRob Herring/ { 21*724ba675SRob Herring model = "Intel IXDPG425 reference design"; 22*724ba675SRob Herring compatible = "intel,ixdpg425", "intel,ixp42x"; 23*724ba675SRob Herring #address-cells = <1>; 24*724ba675SRob Herring #size-cells = <1>; 25*724ba675SRob Herring 26*724ba675SRob Herring memory@0 { 27*724ba675SRob Herring /* 32 MB SDRAM */ 28*724ba675SRob Herring device_type = "memory"; 29*724ba675SRob Herring reg = <0x00000000 0x02000000>; 30*724ba675SRob Herring }; 31*724ba675SRob Herring 32*724ba675SRob Herring chosen { 33*724ba675SRob Herring bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait"; 34*724ba675SRob Herring stdout-path = "uart0:115200n8"; 35*724ba675SRob Herring }; 36*724ba675SRob Herring 37*724ba675SRob Herring aliases { 38*724ba675SRob Herring serial0 = &uart0; 39*724ba675SRob Herring }; 40*724ba675SRob Herring 41*724ba675SRob Herring soc { 42*724ba675SRob Herring bus@c4000000 { 43*724ba675SRob Herring flash@0,0 { 44*724ba675SRob Herring compatible = "intel,ixp4xx-flash", "cfi-flash"; 45*724ba675SRob Herring bank-width = <2>; 46*724ba675SRob Herring /* 47*724ba675SRob Herring * CHECKME: the product brief says 16MB in a flash 48*724ba675SRob Herring * socket. 49*724ba675SRob Herring */ 50*724ba675SRob Herring reg = <0 0x00000000 0x1000000>; 51*724ba675SRob Herring 52*724ba675SRob Herring /* Configure expansion bus to allow writes */ 53*724ba675SRob Herring intel,ixp4xx-eb-write-enable = <1>; 54*724ba675SRob Herring 55*724ba675SRob Herring partitions { 56*724ba675SRob Herring compatible = "redboot-fis"; 57*724ba675SRob Herring /* CHECKME: guess this is Redboot FIS */ 58*724ba675SRob Herring fis-index-block = <0x7f>; 59*724ba675SRob Herring }; 60*724ba675SRob Herring }; 61*724ba675SRob Herring }; 62*724ba675SRob Herring 63*724ba675SRob Herring pci@c0000000 { 64*724ba675SRob Herring status = "okay"; 65*724ba675SRob Herring 66*724ba675SRob Herring /* 67*724ba675SRob Herring * Taken from IXDPG425 PCI boardfile. 68*724ba675SRob Herring * We have slots (IDSEL) 12, 13 and 14 with one assigned IRQ 69*724ba675SRob Herring * for 12 & 13 and one for 14. 70*724ba675SRob Herring */ 71*724ba675SRob Herring #interrupt-cells = <1>; 72*724ba675SRob Herring interrupt-map-mask = <0xf800 0 0 7>; 73*724ba675SRob Herring interrupt-map = 74*724ba675SRob Herring /* IDSEL 12 */ 75*724ba675SRob Herring <0x6000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 12 is irq 7 */ 76*724ba675SRob Herring <0x6000 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 12 is irq 7 */ 77*724ba675SRob Herring <0x6000 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 12 is irq 7 */ 78*724ba675SRob Herring <0x6000 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 12 is irq 7 */ 79*724ba675SRob Herring /* IDSEL 13 */ 80*724ba675SRob Herring <0x6800 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 13 is irq 7 */ 81*724ba675SRob Herring <0x6800 0 0 2 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 13 is irq 7 */ 82*724ba675SRob Herring <0x6800 0 0 3 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 13 is irq 7 */ 83*724ba675SRob Herring <0x6800 0 0 4 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 13 is irq 7 */ 84*724ba675SRob Herring /* IDSEL 14 */ 85*724ba675SRob Herring <0x7000 0 0 1 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 6 */ 86*724ba675SRob Herring <0x7000 0 0 2 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 14 is irq 6 */ 87*724ba675SRob Herring <0x7000 0 0 3 &gpio0 6 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 14 is irq 6 */ 88*724ba675SRob Herring <0x7000 0 0 4 &gpio0 6 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 14 is irq 6 */ 89*724ba675SRob Herring }; 90*724ba675SRob Herring 91*724ba675SRob Herring /* 92*724ba675SRob Herring * CHECKME: this ethernet setup seems dubious. Photos of the board shows some kind 93*724ba675SRob Herring * of Realtek DSA switch on the board. 94*724ba675SRob Herring */ 95*724ba675SRob Herring 96*724ba675SRob Herring /* EthB */ 97*724ba675SRob Herring ethernet@c8009000 { 98*724ba675SRob Herring status = "okay"; 99*724ba675SRob Herring queue-rx = <&qmgr 3>; 100*724ba675SRob Herring queue-txready = <&qmgr 20>; 101*724ba675SRob Herring phy-mode = "rgmii"; 102*724ba675SRob Herring phy-handle = <&phy5>; 103*724ba675SRob Herring 104*724ba675SRob Herring mdio { 105*724ba675SRob Herring #address-cells = <1>; 106*724ba675SRob Herring #size-cells = <0>; 107*724ba675SRob Herring 108*724ba675SRob Herring phy4: ethernet-phy@4 { 109*724ba675SRob Herring reg = <4>; 110*724ba675SRob Herring }; 111*724ba675SRob Herring 112*724ba675SRob Herring phy5: ethernet-phy@5 { 113*724ba675SRob Herring reg = <5>; 114*724ba675SRob Herring }; 115*724ba675SRob Herring }; 116*724ba675SRob Herring }; 117*724ba675SRob Herring 118*724ba675SRob Herring /* EthC */ 119*724ba675SRob Herring ethernet@c800a000 { 120*724ba675SRob Herring status = "okay"; 121*724ba675SRob Herring queue-rx = <&qmgr 4>; 122*724ba675SRob Herring queue-txready = <&qmgr 21>; 123*724ba675SRob Herring phy-mode = "rgmii"; 124*724ba675SRob Herring phy-handle = <&phy4>; 125*724ba675SRob Herring }; 126*724ba675SRob Herring }; 127*724ba675SRob Herring}; 128