1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 9 select ARCH_HAS_CURRENT_STACK_POINTER 10 select ARCH_HAS_DEBUG_VIRTUAL if MMU 11 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 12 select ARCH_HAS_ELF_RANDOMIZE 13 select ARCH_HAS_FORTIFY_SOURCE 14 select ARCH_HAS_KEEPINITRD 15 select ARCH_HAS_KCOV 16 select ARCH_HAS_MEMBARRIER_SYNC_CORE 17 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 18 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 19 select ARCH_HAS_SETUP_DMA_OPS 20 select ARCH_HAS_SET_MEMORY 21 select ARCH_STACKWALK 22 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 23 select ARCH_HAS_STRICT_MODULE_RWX if MMU 24 select ARCH_HAS_SYNC_DMA_FOR_DEVICE 25 select ARCH_HAS_SYNC_DMA_FOR_CPU 26 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 27 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_HAS_UBSAN_SANITIZE_ALL 32 select ARCH_MIGHT_HAVE_PC_PARPORT 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 37 select ARCH_USE_BUILTIN_BSWAP 38 select ARCH_USE_CMPXCHG_LOCKREF 39 select ARCH_USE_MEMTEST 40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 41 select ARCH_WANT_GENERAL_HUGETLB 42 select ARCH_WANT_IPC_PARSE_VERSION 43 select ARCH_WANT_LD_ORPHAN_WARN 44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 45 select BUILDTIME_TABLE_SORT if MMU 46 select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE) 47 select CLONE_BACKWARDS 48 select CPU_PM if SUSPEND || CPU_IDLE 49 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 50 select DMA_DECLARE_COHERENT 51 select DMA_GLOBAL_POOL if !MMU 52 select DMA_OPS 53 select DMA_NONCOHERENT_MMAP if MMU 54 select EDAC_SUPPORT 55 select EDAC_ATOMIC_SCRUB 56 select GENERIC_ALLOCATOR 57 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 58 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 59 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 60 select GENERIC_IRQ_IPI if SMP 61 select GENERIC_CPU_AUTOPROBE 62 select GENERIC_EARLY_IOREMAP 63 select GENERIC_IDLE_POLL_SETUP 64 select GENERIC_IRQ_MULTI_HANDLER 65 select GENERIC_IRQ_PROBE 66 select GENERIC_IRQ_SHOW 67 select GENERIC_IRQ_SHOW_LEVEL 68 select GENERIC_LIB_DEVMEM_IS_ALLOWED 69 select GENERIC_PCI_IOMAP 70 select GENERIC_SCHED_CLOCK 71 select GENERIC_SMP_IDLE_THREAD 72 select HARDIRQS_SW_RESEND 73 select HAS_IOPORT 74 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 75 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 76 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 77 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL 78 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 79 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 80 select HAVE_ARCH_KASAN_VMALLOC if HAVE_ARCH_KASAN 81 select HAVE_ARCH_MMAP_RND_BITS if MMU 82 select HAVE_ARCH_PFN_VALID 83 select HAVE_ARCH_SECCOMP 84 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 85 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 86 select HAVE_ARCH_TRACEHOOK 87 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 88 select HAVE_ARM_SMCCC if CPU_V7 89 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 90 select HAVE_CONTEXT_TRACKING_USER 91 select HAVE_C_RECORDMCOUNT 92 select HAVE_BUILDTIME_MCOUNT_SORT 93 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 94 select HAVE_DMA_CONTIGUOUS if MMU 95 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 96 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 97 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 98 select HAVE_EXIT_THREAD 99 select HAVE_FAST_GUP if ARM_LPAE 100 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 101 select HAVE_FUNCTION_ERROR_INJECTION 102 select HAVE_FUNCTION_GRAPH_TRACER 103 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 104 select HAVE_GCC_PLUGINS 105 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 106 select HAVE_IRQ_TIME_ACCOUNTING 107 select HAVE_KERNEL_GZIP 108 select HAVE_KERNEL_LZ4 109 select HAVE_KERNEL_LZMA 110 select HAVE_KERNEL_LZO 111 select HAVE_KERNEL_XZ 112 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 113 select HAVE_KRETPROBES if HAVE_KPROBES 114 select HAVE_MOD_ARCH_SPECIFIC 115 select HAVE_NMI 116 select HAVE_OPTPROBES if !THUMB2_KERNEL 117 select HAVE_PCI if MMU 118 select HAVE_PERF_EVENTS 119 select HAVE_PERF_REGS 120 select HAVE_PERF_USER_STACK_DUMP 121 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 122 select HAVE_REGS_AND_STACK_ACCESS_API 123 select HAVE_RSEQ 124 select HAVE_STACKPROTECTOR 125 select HAVE_SYSCALL_TRACEPOINTS 126 select HAVE_UID16 127 select HAVE_VIRT_CPU_ACCOUNTING_GEN 128 select IRQ_FORCED_THREADING 129 select MODULES_USE_ELF_REL 130 select NEED_DMA_MAP_STATE 131 select OF_EARLY_FLATTREE if OF 132 select OLD_SIGACTION 133 select OLD_SIGSUSPEND3 134 select PCI_DOMAINS_GENERIC if PCI 135 select PCI_SYSCALL if PCI 136 select PERF_USE_VMALLOC 137 select RTC_LIB 138 select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC) 139 select SYS_SUPPORTS_APM_EMULATION 140 select THREAD_INFO_IN_TASK 141 select TIMER_OF if OF 142 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS 143 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 144 select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 145 # Above selects are sorted alphabetically; please add new ones 146 # according to that. Thanks. 147 help 148 The ARM series is a line of low-power-consumption RISC chip designs 149 licensed by ARM Ltd and targeted at embedded applications and 150 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 151 manufactured, but legacy ARM-based PC hardware remains popular in 152 Europe. There is an ARM Linux project with a web page at 153 <http://www.arm.linux.org.uk/>. 154 155config ARM_HAS_GROUP_RELOCS 156 def_bool y 157 depends on !LD_IS_LLD || LLD_VERSION >= 140000 158 depends on !COMPILE_TEST 159 help 160 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group 161 relocations, which have been around for a long time, but were not 162 supported in LLD until version 14. The combined range is -/+ 256 MiB, 163 which is usually sufficient, but not for allyesconfig, so we disable 164 this feature when doing compile testing. 165 166config ARM_DMA_USE_IOMMU 167 bool 168 select NEED_SG_DMA_LENGTH 169 170if ARM_DMA_USE_IOMMU 171 172config ARM_DMA_IOMMU_ALIGNMENT 173 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 174 range 4 9 175 default 8 176 help 177 DMA mapping framework by default aligns all buffers to the smallest 178 PAGE_SIZE order which is greater than or equal to the requested buffer 179 size. This works well for buffers up to a few hundreds kilobytes, but 180 for larger buffers it just a waste of address space. Drivers which has 181 relatively small addressing window (like 64Mib) might run out of 182 virtual space with just a few allocations. 183 184 With this parameter you can specify the maximum PAGE_SIZE order for 185 DMA IOMMU buffers. Larger buffers will be aligned only to this 186 specified order. The order is expressed as a power of two multiplied 187 by the PAGE_SIZE. 188 189endif 190 191config SYS_SUPPORTS_APM_EMULATION 192 bool 193 194config HAVE_TCM 195 bool 196 select GENERIC_ALLOCATOR 197 198config HAVE_PROC_CPU 199 bool 200 201config NO_IOPORT_MAP 202 bool 203 204config SBUS 205 bool 206 207config STACKTRACE_SUPPORT 208 bool 209 default y 210 211config LOCKDEP_SUPPORT 212 bool 213 default y 214 215config ARCH_HAS_ILOG2_U32 216 bool 217 218config ARCH_HAS_ILOG2_U64 219 bool 220 221config ARCH_HAS_BANDGAP 222 bool 223 224config FIX_EARLYCON_MEM 225 def_bool y if MMU 226 227config GENERIC_HWEIGHT 228 bool 229 default y 230 231config GENERIC_CALIBRATE_DELAY 232 bool 233 default y 234 235config ARCH_MAY_HAVE_PC_FDC 236 bool 237 238config ARCH_SUPPORTS_UPROBES 239 def_bool y 240 241config GENERIC_ISA_DMA 242 bool 243 244config FIQ 245 bool 246 247config ARCH_MTD_XIP 248 bool 249 250config ARM_PATCH_PHYS_VIRT 251 bool "Patch physical to virtual translations at runtime" if EMBEDDED 252 default y 253 depends on MMU 254 help 255 Patch phys-to-virt and virt-to-phys translation functions at 256 boot and module load time according to the position of the 257 kernel in system memory. 258 259 This can only be used with non-XIP MMU kernels where the base 260 of physical memory is at a 2 MiB boundary. 261 262 Only disable this option if you know that you do not require 263 this feature (eg, building a kernel for a single machine) and 264 you need to shrink the kernel to the minimal size. 265 266config NEED_MACH_IO_H 267 bool 268 help 269 Select this when mach/io.h is required to provide special 270 definitions for this platform. The need for mach/io.h should 271 be avoided when possible. 272 273config NEED_MACH_MEMORY_H 274 bool 275 help 276 Select this when mach/memory.h is required to provide special 277 definitions for this platform. The need for mach/memory.h should 278 be avoided when possible. 279 280config PHYS_OFFSET 281 hex "Physical address of main memory" if MMU 282 depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR 283 default DRAM_BASE if !MMU 284 default 0x00000000 if ARCH_FOOTBRIDGE 285 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 286 default 0xa0000000 if ARCH_PXA 287 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 288 default 0 289 help 290 Please provide the physical address corresponding to the 291 location of main memory in your system. 292 293config GENERIC_BUG 294 def_bool y 295 depends on BUG 296 297config PGTABLE_LEVELS 298 int 299 default 3 if ARM_LPAE 300 default 2 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARM_SINGLE_ARMV7M 312 def_bool !MMU 313 select ARM_NVIC 314 select CPU_V7M 315 select NO_IOPORT_MAP 316 317config ARCH_MMAP_RND_BITS_MIN 318 default 8 319 320config ARCH_MMAP_RND_BITS_MAX 321 default 14 if PAGE_OFFSET=0x40000000 322 default 15 if PAGE_OFFSET=0x80000000 323 default 16 324 325config ARCH_MULTIPLATFORM 326 bool "Require kernel to be portable to multiple machines" if EXPERT 327 depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 328 default y 329 help 330 In general, all Arm machines can be supported in a single 331 kernel image, covering either Armv4/v5 or Armv6/v7. 332 333 However, some configuration options require hardcoding machine 334 specific physical addresses or enable errata workarounds that may 335 break other machines. 336 337 Selecting N here allows using those options, including 338 DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y. 339 340menu "Platform selection" 341 depends on MMU 342 343comment "CPU Core family selection" 344 345config ARCH_MULTI_V4 346 bool "ARMv4 based platforms (FA526, StrongARM)" 347 depends on !ARCH_MULTI_V6_V7 348 # https://github.com/llvm/llvm-project/issues/50764 349 depends on !LD_IS_LLD || LLD_VERSION >= 160000 350 select ARCH_MULTI_V4_V5 351 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) 352 353config ARCH_MULTI_V4T 354 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 355 depends on !ARCH_MULTI_V6_V7 356 # https://github.com/llvm/llvm-project/issues/50764 357 depends on !LD_IS_LLD || LLD_VERSION >= 160000 358 select ARCH_MULTI_V4_V5 359 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 360 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 361 CPU_ARM925T || CPU_ARM940T) 362 363config ARCH_MULTI_V5 364 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 365 depends on !ARCH_MULTI_V6_V7 366 select ARCH_MULTI_V4_V5 367 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 368 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 369 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 370 371config ARCH_MULTI_V4_V5 372 bool 373 374config ARCH_MULTI_V6 375 bool "ARMv6 based platforms (ARM11)" 376 select ARCH_MULTI_V6_V7 377 select CPU_V6K 378 379config ARCH_MULTI_V7 380 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 381 default y 382 select ARCH_MULTI_V6_V7 383 select CPU_V7 384 select HAVE_SMP 385 386config ARCH_MULTI_V6_V7 387 bool 388 select MIGHT_HAVE_CACHE_L2X0 389 390config ARCH_MULTI_CPU_AUTO 391 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 392 select ARCH_MULTI_V5 393 394endmenu 395 396config ARCH_VIRT 397 bool "Dummy Virtual Machine" 398 depends on ARCH_MULTI_V7 399 select ARM_AMBA 400 select ARM_GIC 401 select ARM_GIC_V2M if PCI 402 select ARM_GIC_V3 403 select ARM_GIC_V3_ITS if PCI 404 select ARM_PSCI 405 select HAVE_ARM_ARCH_TIMER 406 407config ARCH_AIROHA 408 bool "Airoha SoC Support" 409 depends on ARCH_MULTI_V7 410 select ARM_AMBA 411 select ARM_GIC 412 select ARM_GIC_V3 413 select ARM_PSCI 414 select HAVE_ARM_ARCH_TIMER 415 help 416 Support for Airoha EN7523 SoCs 417 418# 419# This is sorted alphabetically by mach-* pathname. However, plat-* 420# Kconfigs may be included either alphabetically (according to the 421# plat- suffix) or along side the corresponding mach-* source. 422# 423source "arch/arm/mach-actions/Kconfig" 424 425source "arch/arm/mach-alpine/Kconfig" 426 427source "arch/arm/mach-artpec/Kconfig" 428 429source "arch/arm/mach-asm9260/Kconfig" 430 431source "arch/arm/mach-aspeed/Kconfig" 432 433source "arch/arm/mach-at91/Kconfig" 434 435source "arch/arm/mach-axxia/Kconfig" 436 437source "arch/arm/mach-bcm/Kconfig" 438 439source "arch/arm/mach-berlin/Kconfig" 440 441source "arch/arm/mach-clps711x/Kconfig" 442 443source "arch/arm/mach-davinci/Kconfig" 444 445source "arch/arm/mach-digicolor/Kconfig" 446 447source "arch/arm/mach-dove/Kconfig" 448 449source "arch/arm/mach-ep93xx/Kconfig" 450 451source "arch/arm/mach-exynos/Kconfig" 452 453source "arch/arm/mach-footbridge/Kconfig" 454 455source "arch/arm/mach-gemini/Kconfig" 456 457source "arch/arm/mach-highbank/Kconfig" 458 459source "arch/arm/mach-hisi/Kconfig" 460 461source "arch/arm/mach-hpe/Kconfig" 462 463source "arch/arm/mach-imx/Kconfig" 464 465source "arch/arm/mach-ixp4xx/Kconfig" 466 467source "arch/arm/mach-keystone/Kconfig" 468 469source "arch/arm/mach-lpc32xx/Kconfig" 470 471source "arch/arm/mach-mediatek/Kconfig" 472 473source "arch/arm/mach-meson/Kconfig" 474 475source "arch/arm/mach-milbeaut/Kconfig" 476 477source "arch/arm/mach-mmp/Kconfig" 478 479source "arch/arm/mach-moxart/Kconfig" 480 481source "arch/arm/mach-mstar/Kconfig" 482 483source "arch/arm/mach-mv78xx0/Kconfig" 484 485source "arch/arm/mach-mvebu/Kconfig" 486 487source "arch/arm/mach-mxs/Kconfig" 488 489source "arch/arm/mach-nomadik/Kconfig" 490 491source "arch/arm/mach-npcm/Kconfig" 492 493source "arch/arm/mach-nspire/Kconfig" 494 495source "arch/arm/mach-omap1/Kconfig" 496 497source "arch/arm/mach-omap2/Kconfig" 498 499source "arch/arm/mach-orion5x/Kconfig" 500 501source "arch/arm/mach-pxa/Kconfig" 502 503source "arch/arm/mach-qcom/Kconfig" 504 505source "arch/arm/mach-rda/Kconfig" 506 507source "arch/arm/mach-realtek/Kconfig" 508 509source "arch/arm/mach-rpc/Kconfig" 510 511source "arch/arm/mach-rockchip/Kconfig" 512 513source "arch/arm/mach-s3c/Kconfig" 514 515source "arch/arm/mach-s5pv210/Kconfig" 516 517source "arch/arm/mach-sa1100/Kconfig" 518 519source "arch/arm/mach-shmobile/Kconfig" 520 521source "arch/arm/mach-socfpga/Kconfig" 522 523source "arch/arm/mach-spear/Kconfig" 524 525source "arch/arm/mach-sti/Kconfig" 526 527source "arch/arm/mach-stm32/Kconfig" 528 529source "arch/arm/mach-sunplus/Kconfig" 530 531source "arch/arm/mach-sunxi/Kconfig" 532 533source "arch/arm/mach-tegra/Kconfig" 534 535source "arch/arm/mach-uniphier/Kconfig" 536 537source "arch/arm/mach-ux500/Kconfig" 538 539source "arch/arm/mach-versatile/Kconfig" 540 541source "arch/arm/mach-vt8500/Kconfig" 542 543source "arch/arm/mach-zynq/Kconfig" 544 545# ARMv7-M architecture 546config ARCH_LPC18XX 547 bool "NXP LPC18xx/LPC43xx" 548 depends on ARM_SINGLE_ARMV7M 549 select ARCH_HAS_RESET_CONTROLLER 550 select ARM_AMBA 551 select CLKSRC_LPC32XX 552 select PINCTRL 553 help 554 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 555 high performance microcontrollers. 556 557config ARCH_MPS2 558 bool "ARM MPS2 platform" 559 depends on ARM_SINGLE_ARMV7M 560 select ARM_AMBA 561 select CLKSRC_MPS2 562 help 563 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 564 with a range of available cores like Cortex-M3/M4/M7. 565 566 Please, note that depends which Application Note is used memory map 567 for the platform may vary, so adjustment of RAM base might be needed. 568 569# Definitions to make life easier 570config ARCH_ACORN 571 bool 572 573config PLAT_ORION 574 bool 575 select CLKSRC_MMIO 576 select GENERIC_IRQ_CHIP 577 select IRQ_DOMAIN 578 579config PLAT_ORION_LEGACY 580 bool 581 select PLAT_ORION 582 583config PLAT_VERSATILE 584 bool 585 586source "arch/arm/mm/Kconfig" 587 588config IWMMXT 589 bool "Enable iWMMXt support" 590 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 591 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 592 help 593 Enable support for iWMMXt context switching at run time if 594 running on a CPU that supports it. 595 596if !MMU 597source "arch/arm/Kconfig-nommu" 598endif 599 600config PJ4B_ERRATA_4742 601 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 602 depends on CPU_PJ4B && MACH_ARMADA_370 603 default y 604 help 605 When coming out of either a Wait for Interrupt (WFI) or a Wait for 606 Event (WFE) IDLE states, a specific timing sensitivity exists between 607 the retiring WFI/WFE instructions and the newly issued subsequent 608 instructions. This sensitivity can result in a CPU hang scenario. 609 Workaround: 610 The software must insert either a Data Synchronization Barrier (DSB) 611 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 612 instruction 613 614config ARM_ERRATA_326103 615 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 616 depends on CPU_V6 617 help 618 Executing a SWP instruction to read-only memory does not set bit 11 619 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 620 treat the access as a read, preventing a COW from occurring and 621 causing the faulting task to livelock. 622 623config ARM_ERRATA_411920 624 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 625 depends on CPU_V6 || CPU_V6K 626 help 627 Invalidation of the Instruction Cache operation can 628 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 629 It does not affect the MPCore. This option enables the ARM Ltd. 630 recommended workaround. 631 632config ARM_ERRATA_430973 633 bool "ARM errata: Stale prediction on replaced interworking branch" 634 depends on CPU_V7 635 help 636 This option enables the workaround for the 430973 Cortex-A8 637 r1p* erratum. If a code sequence containing an ARM/Thumb 638 interworking branch is replaced with another code sequence at the 639 same virtual address, whether due to self-modifying code or virtual 640 to physical address re-mapping, Cortex-A8 does not recover from the 641 stale interworking branch prediction. This results in Cortex-A8 642 executing the new code sequence in the incorrect ARM or Thumb state. 643 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 644 and also flushes the branch target cache at every context switch. 645 Note that setting specific bits in the ACTLR register may not be 646 available in non-secure mode. 647 648config ARM_ERRATA_458693 649 bool "ARM errata: Processor deadlock when a false hazard is created" 650 depends on CPU_V7 651 depends on !ARCH_MULTIPLATFORM 652 help 653 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 654 erratum. For very specific sequences of memory operations, it is 655 possible for a hazard condition intended for a cache line to instead 656 be incorrectly associated with a different cache line. This false 657 hazard might then cause a processor deadlock. The workaround enables 658 the L1 caching of the NEON accesses and disables the PLD instruction 659 in the ACTLR register. Note that setting specific bits in the ACTLR 660 register may not be available in non-secure mode and thus is not 661 available on a multiplatform kernel. This should be applied by the 662 bootloader instead. 663 664config ARM_ERRATA_460075 665 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 666 depends on CPU_V7 667 depends on !ARCH_MULTIPLATFORM 668 help 669 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 670 erratum. Any asynchronous access to the L2 cache may encounter a 671 situation in which recent store transactions to the L2 cache are lost 672 and overwritten with stale memory contents from external memory. The 673 workaround disables the write-allocate mode for the L2 cache via the 674 ACTLR register. Note that setting specific bits in the ACTLR register 675 may not be available in non-secure mode and thus is not available on 676 a multiplatform kernel. This should be applied by the bootloader 677 instead. 678 679config ARM_ERRATA_742230 680 bool "ARM errata: DMB operation may be faulty" 681 depends on CPU_V7 && SMP 682 depends on !ARCH_MULTIPLATFORM 683 help 684 This option enables the workaround for the 742230 Cortex-A9 685 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 686 between two write operations may not ensure the correct visibility 687 ordering of the two writes. This workaround sets a specific bit in 688 the diagnostic register of the Cortex-A9 which causes the DMB 689 instruction to behave as a DSB, ensuring the correct behaviour of 690 the two writes. Note that setting specific bits in the diagnostics 691 register may not be available in non-secure mode and thus is not 692 available on a multiplatform kernel. This should be applied by the 693 bootloader instead. 694 695config ARM_ERRATA_742231 696 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 697 depends on CPU_V7 && SMP 698 depends on !ARCH_MULTIPLATFORM 699 help 700 This option enables the workaround for the 742231 Cortex-A9 701 (r2p0..r2p2) erratum. Under certain conditions, specific to the 702 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 703 accessing some data located in the same cache line, may get corrupted 704 data due to bad handling of the address hazard when the line gets 705 replaced from one of the CPUs at the same time as another CPU is 706 accessing it. This workaround sets specific bits in the diagnostic 707 register of the Cortex-A9 which reduces the linefill issuing 708 capabilities of the processor. Note that setting specific bits in the 709 diagnostics register may not be available in non-secure mode and thus 710 is not available on a multiplatform kernel. This should be applied by 711 the bootloader instead. 712 713config ARM_ERRATA_643719 714 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 715 depends on CPU_V7 && SMP 716 default y 717 help 718 This option enables the workaround for the 643719 Cortex-A9 (prior to 719 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 720 register returns zero when it should return one. The workaround 721 corrects this value, ensuring cache maintenance operations which use 722 it behave as intended and avoiding data corruption. 723 724config ARM_ERRATA_720789 725 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 726 depends on CPU_V7 727 help 728 This option enables the workaround for the 720789 Cortex-A9 (prior to 729 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 730 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 731 As a consequence of this erratum, some TLB entries which should be 732 invalidated are not, resulting in an incoherency in the system page 733 tables. The workaround changes the TLB flushing routines to invalidate 734 entries regardless of the ASID. 735 736config ARM_ERRATA_743622 737 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 738 depends on CPU_V7 739 depends on !ARCH_MULTIPLATFORM 740 help 741 This option enables the workaround for the 743622 Cortex-A9 742 (r2p*) erratum. Under very rare conditions, a faulty 743 optimisation in the Cortex-A9 Store Buffer may lead to data 744 corruption. This workaround sets a specific bit in the diagnostic 745 register of the Cortex-A9 which disables the Store Buffer 746 optimisation, preventing the defect from occurring. This has no 747 visible impact on the overall performance or power consumption of the 748 processor. Note that setting specific bits in the diagnostics register 749 may not be available in non-secure mode and thus is not available on a 750 multiplatform kernel. This should be applied by the bootloader instead. 751 752config ARM_ERRATA_751472 753 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 754 depends on CPU_V7 755 depends on !ARCH_MULTIPLATFORM 756 help 757 This option enables the workaround for the 751472 Cortex-A9 (prior 758 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 759 completion of a following broadcasted operation if the second 760 operation is received by a CPU before the ICIALLUIS has completed, 761 potentially leading to corrupted entries in the cache or TLB. 762 Note that setting specific bits in the diagnostics register may 763 not be available in non-secure mode and thus is not available on 764 a multiplatform kernel. This should be applied by the bootloader 765 instead. 766 767config ARM_ERRATA_754322 768 bool "ARM errata: possible faulty MMU translations following an ASID switch" 769 depends on CPU_V7 770 help 771 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 772 r3p*) erratum. A speculative memory access may cause a page table walk 773 which starts prior to an ASID switch but completes afterwards. This 774 can populate the micro-TLB with a stale entry which may be hit with 775 the new ASID. This workaround places two dsb instructions in the mm 776 switching code so that no page table walks can cross the ASID switch. 777 778config ARM_ERRATA_754327 779 bool "ARM errata: no automatic Store Buffer drain" 780 depends on CPU_V7 && SMP 781 help 782 This option enables the workaround for the 754327 Cortex-A9 (prior to 783 r2p0) erratum. The Store Buffer does not have any automatic draining 784 mechanism and therefore a livelock may occur if an external agent 785 continuously polls a memory location waiting to observe an update. 786 This workaround defines cpu_relax() as smp_mb(), preventing correctly 787 written polling loops from denying visibility of updates to memory. 788 789config ARM_ERRATA_364296 790 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 791 depends on CPU_V6 792 help 793 This options enables the workaround for the 364296 ARM1136 794 r0p2 erratum (possible cache data corruption with 795 hit-under-miss enabled). It sets the undocumented bit 31 in 796 the auxiliary control register and the FI bit in the control 797 register, thus disabling hit-under-miss without putting the 798 processor into full low interrupt latency mode. ARM11MPCore 799 is not affected. 800 801config ARM_ERRATA_764369 802 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 803 depends on CPU_V7 && SMP 804 help 805 This option enables the workaround for erratum 764369 806 affecting Cortex-A9 MPCore with two or more processors (all 807 current revisions). Under certain timing circumstances, a data 808 cache line maintenance operation by MVA targeting an Inner 809 Shareable memory region may fail to proceed up to either the 810 Point of Coherency or to the Point of Unification of the 811 system. This workaround adds a DSB instruction before the 812 relevant cache maintenance functions and sets a specific bit 813 in the diagnostic control register of the SCU. 814 815config ARM_ERRATA_764319 816 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" 817 depends on CPU_V7 818 help 819 This option enables the workaround for the 764319 Cortex A-9 erratum. 820 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an 821 unexpected Undefined Instruction exception when the DBGSWENABLE 822 external pin is set to 0, even when the CP14 accesses are performed 823 from a privileged mode. This work around catches the exception in a 824 way the kernel does not stop execution. 825 826config ARM_ERRATA_775420 827 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 828 depends on CPU_V7 829 help 830 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 831 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 832 operation aborts with MMU exception, it might cause the processor 833 to deadlock. This workaround puts DSB before executing ISB if 834 an abort may occur on cache maintenance. 835 836config ARM_ERRATA_798181 837 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 838 depends on CPU_V7 && SMP 839 help 840 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 841 adequately shooting down all use of the old entries. This 842 option enables the Linux kernel workaround for this erratum 843 which sends an IPI to the CPUs that are running the same ASID 844 as the one being invalidated. 845 846config ARM_ERRATA_773022 847 bool "ARM errata: incorrect instructions may be executed from loop buffer" 848 depends on CPU_V7 849 help 850 This option enables the workaround for the 773022 Cortex-A15 851 (up to r0p4) erratum. In certain rare sequences of code, the 852 loop buffer may deliver incorrect instructions. This 853 workaround disables the loop buffer to avoid the erratum. 854 855config ARM_ERRATA_818325_852422 856 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 857 depends on CPU_V7 858 help 859 This option enables the workaround for: 860 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 861 instruction might deadlock. Fixed in r0p1. 862 - Cortex-A12 852422: Execution of a sequence of instructions might 863 lead to either a data corruption or a CPU deadlock. Not fixed in 864 any Cortex-A12 cores yet. 865 This workaround for all both errata involves setting bit[12] of the 866 Feature Register. This bit disables an optimisation applied to a 867 sequence of 2 instructions that use opposing condition codes. 868 869config ARM_ERRATA_821420 870 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 871 depends on CPU_V7 872 help 873 This option enables the workaround for the 821420 Cortex-A12 874 (all revs) erratum. In very rare timing conditions, a sequence 875 of VMOV to Core registers instructions, for which the second 876 one is in the shadow of a branch or abort, can lead to a 877 deadlock when the VMOV instructions are issued out-of-order. 878 879config ARM_ERRATA_825619 880 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 881 depends on CPU_V7 882 help 883 This option enables the workaround for the 825619 Cortex-A12 884 (all revs) erratum. Within rare timing constraints, executing a 885 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 886 and Device/Strongly-Ordered loads and stores might cause deadlock 887 888config ARM_ERRATA_857271 889 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 890 depends on CPU_V7 891 help 892 This option enables the workaround for the 857271 Cortex-A12 893 (all revs) erratum. Under very rare timing conditions, the CPU might 894 hang. The workaround is expected to have a < 1% performance impact. 895 896config ARM_ERRATA_852421 897 bool "ARM errata: A17: DMB ST might fail to create order between stores" 898 depends on CPU_V7 899 help 900 This option enables the workaround for the 852421 Cortex-A17 901 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 902 execution of a DMB ST instruction might fail to properly order 903 stores from GroupA and stores from GroupB. 904 905config ARM_ERRATA_852423 906 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 907 depends on CPU_V7 908 help 909 This option enables the workaround for: 910 - Cortex-A17 852423: Execution of a sequence of instructions might 911 lead to either a data corruption or a CPU deadlock. Not fixed in 912 any Cortex-A17 cores yet. 913 This is identical to Cortex-A12 erratum 852422. It is a separate 914 config option from the A12 erratum due to the way errata are checked 915 for and handled. 916 917config ARM_ERRATA_857272 918 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 919 depends on CPU_V7 920 help 921 This option enables the workaround for the 857272 Cortex-A17 erratum. 922 This erratum is not known to be fixed in any A17 revision. 923 This is identical to Cortex-A12 erratum 857271. It is a separate 924 config option from the A12 erratum due to the way errata are checked 925 for and handled. 926 927endmenu 928 929source "arch/arm/common/Kconfig" 930 931menu "Bus support" 932 933config ISA 934 bool 935 help 936 Find out whether you have ISA slots on your motherboard. ISA is the 937 name of a bus system, i.e. the way the CPU talks to the other stuff 938 inside your box. Other bus systems are PCI, EISA, MicroChannel 939 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 940 newer boards don't support it. If you have ISA, say Y, otherwise N. 941 942# Select ISA DMA interface 943config ISA_DMA_API 944 bool 945 946config ARM_ERRATA_814220 947 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 948 depends on CPU_V7 949 help 950 The v7 ARM states that all cache and branch predictor maintenance 951 operations that do not specify an address execute, relative to 952 each other, in program order. 953 However, because of this erratum, an L2 set/way cache maintenance 954 operation can overtake an L1 set/way cache maintenance operation. 955 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 956 r0p4, r0p5. 957 958endmenu 959 960menu "Kernel Features" 961 962config HAVE_SMP 963 bool 964 help 965 This option should be selected by machines which have an SMP- 966 capable CPU. 967 968 The only effect of this option is to make the SMP-related 969 options available to the user for configuration. 970 971config SMP 972 bool "Symmetric Multi-Processing" 973 depends on CPU_V6K || CPU_V7 974 depends on HAVE_SMP 975 depends on MMU || ARM_MPU 976 select IRQ_WORK 977 help 978 This enables support for systems with more than one CPU. If you have 979 a system with only one CPU, say N. If you have a system with more 980 than one CPU, say Y. 981 982 If you say N here, the kernel will run on uni- and multiprocessor 983 machines, but will use only one CPU of a multiprocessor machine. If 984 you say Y here, the kernel will run on many, but not all, 985 uniprocessor machines. On a uniprocessor machine, the kernel 986 will run faster if you say N here. 987 988 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>, 989 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 990 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 991 992 If you don't know what to do here, say N. 993 994config SMP_ON_UP 995 bool "Allow booting SMP kernel on uniprocessor systems" 996 depends on SMP && MMU 997 default y 998 help 999 SMP kernels contain instructions which fail on non-SMP processors. 1000 Enabling this option allows the kernel to modify itself to make 1001 these instructions safe. Disabling it allows about 1K of space 1002 savings. 1003 1004 If you don't know what to do here, say Y. 1005 1006 1007config CURRENT_POINTER_IN_TPIDRURO 1008 def_bool y 1009 depends on CPU_32v6K && !CPU_V6 1010 1011config IRQSTACKS 1012 def_bool y 1013 select HAVE_IRQ_EXIT_ON_IRQ_STACK 1014 select HAVE_SOFTIRQ_ON_OWN_STACK 1015 1016config ARM_CPU_TOPOLOGY 1017 bool "Support cpu topology definition" 1018 depends on SMP && CPU_V7 1019 default y 1020 help 1021 Support ARM cpu topology definition. The MPIDR register defines 1022 affinity between processors which is then used to describe the cpu 1023 topology of an ARM System. 1024 1025config SCHED_MC 1026 bool "Multi-core scheduler support" 1027 depends on ARM_CPU_TOPOLOGY 1028 help 1029 Multi-core scheduler support improves the CPU scheduler's decision 1030 making when dealing with multi-core CPU chips at a cost of slightly 1031 increased overhead in some places. If unsure say N here. 1032 1033config SCHED_SMT 1034 bool "SMT scheduler support" 1035 depends on ARM_CPU_TOPOLOGY 1036 help 1037 Improves the CPU scheduler's decision making when dealing with 1038 MultiThreading at a cost of slightly increased overhead in some 1039 places. If unsure say N here. 1040 1041config HAVE_ARM_SCU 1042 bool 1043 help 1044 This option enables support for the ARM snoop control unit 1045 1046config HAVE_ARM_ARCH_TIMER 1047 bool "Architected timer support" 1048 depends on CPU_V7 1049 select ARM_ARCH_TIMER 1050 help 1051 This option enables support for the ARM architected timer 1052 1053config HAVE_ARM_TWD 1054 bool 1055 help 1056 This options enables support for the ARM timer and watchdog unit 1057 1058config MCPM 1059 bool "Multi-Cluster Power Management" 1060 depends on CPU_V7 && SMP 1061 help 1062 This option provides the common power management infrastructure 1063 for (multi-)cluster based systems, such as big.LITTLE based 1064 systems. 1065 1066config MCPM_QUAD_CLUSTER 1067 bool 1068 depends on MCPM 1069 help 1070 To avoid wasting resources unnecessarily, MCPM only supports up 1071 to 2 clusters by default. 1072 Platforms with 3 or 4 clusters that use MCPM must select this 1073 option to allow the additional clusters to be managed. 1074 1075config BIG_LITTLE 1076 bool "big.LITTLE support (Experimental)" 1077 depends on CPU_V7 && SMP 1078 select MCPM 1079 help 1080 This option enables support selections for the big.LITTLE 1081 system architecture. 1082 1083config BL_SWITCHER 1084 bool "big.LITTLE switcher support" 1085 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1086 select CPU_PM 1087 help 1088 The big.LITTLE "switcher" provides the core functionality to 1089 transparently handle transition between a cluster of A15's 1090 and a cluster of A7's in a big.LITTLE system. 1091 1092config BL_SWITCHER_DUMMY_IF 1093 tristate "Simple big.LITTLE switcher user interface" 1094 depends on BL_SWITCHER && DEBUG_KERNEL 1095 help 1096 This is a simple and dummy char dev interface to control 1097 the big.LITTLE switcher core code. It is meant for 1098 debugging purposes only. 1099 1100choice 1101 prompt "Memory split" 1102 depends on MMU 1103 default VMSPLIT_3G 1104 help 1105 Select the desired split between kernel and user memory. 1106 1107 If you are not absolutely sure what you are doing, leave this 1108 option alone! 1109 1110 config VMSPLIT_3G 1111 bool "3G/1G user/kernel split" 1112 config VMSPLIT_3G_OPT 1113 depends on !ARM_LPAE 1114 bool "3G/1G user/kernel split (for full 1G low memory)" 1115 config VMSPLIT_2G 1116 bool "2G/2G user/kernel split" 1117 config VMSPLIT_1G 1118 bool "1G/3G user/kernel split" 1119endchoice 1120 1121config PAGE_OFFSET 1122 hex 1123 default PHYS_OFFSET if !MMU 1124 default 0x40000000 if VMSPLIT_1G 1125 default 0x80000000 if VMSPLIT_2G 1126 default 0xB0000000 if VMSPLIT_3G_OPT 1127 default 0xC0000000 1128 1129config KASAN_SHADOW_OFFSET 1130 hex 1131 depends on KASAN 1132 default 0x1f000000 if PAGE_OFFSET=0x40000000 1133 default 0x5f000000 if PAGE_OFFSET=0x80000000 1134 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1135 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1136 default 0xffffffff 1137 1138config NR_CPUS 1139 int "Maximum number of CPUs (2-32)" 1140 range 2 16 if DEBUG_KMAP_LOCAL 1141 range 2 32 if !DEBUG_KMAP_LOCAL 1142 depends on SMP 1143 default "4" 1144 help 1145 The maximum number of CPUs that the kernel can support. 1146 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1147 debugging is enabled, which uses half of the per-CPU fixmap 1148 slots as guard regions. 1149 1150config HOTPLUG_CPU 1151 bool "Support for hot-pluggable CPUs" 1152 depends on SMP 1153 select GENERIC_IRQ_MIGRATION 1154 help 1155 Say Y here to experiment with turning CPUs off and on. CPUs 1156 can be controlled through /sys/devices/system/cpu. 1157 1158config ARM_PSCI 1159 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1160 depends on HAVE_ARM_SMCCC 1161 select ARM_PSCI_FW 1162 help 1163 Say Y here if you want Linux to communicate with system firmware 1164 implementing the PSCI specification for CPU-centric power 1165 management operations described in ARM document number ARM DEN 1166 0022A ("Power State Coordination Interface System Software on 1167 ARM processors"). 1168 1169config HZ_FIXED 1170 int 1171 default 128 if SOC_AT91RM9200 1172 default 0 1173 1174choice 1175 depends on HZ_FIXED = 0 1176 prompt "Timer frequency" 1177 1178config HZ_100 1179 bool "100 Hz" 1180 1181config HZ_200 1182 bool "200 Hz" 1183 1184config HZ_250 1185 bool "250 Hz" 1186 1187config HZ_300 1188 bool "300 Hz" 1189 1190config HZ_500 1191 bool "500 Hz" 1192 1193config HZ_1000 1194 bool "1000 Hz" 1195 1196endchoice 1197 1198config HZ 1199 int 1200 default HZ_FIXED if HZ_FIXED != 0 1201 default 100 if HZ_100 1202 default 200 if HZ_200 1203 default 250 if HZ_250 1204 default 300 if HZ_300 1205 default 500 if HZ_500 1206 default 1000 1207 1208config SCHED_HRTICK 1209 def_bool HIGH_RES_TIMERS 1210 1211config THUMB2_KERNEL 1212 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1213 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1214 default y if CPU_THUMBONLY 1215 select ARM_UNWIND 1216 help 1217 By enabling this option, the kernel will be compiled in 1218 Thumb-2 mode. 1219 1220 If unsure, say N. 1221 1222config ARM_PATCH_IDIV 1223 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1224 depends on CPU_32v7 1225 default y 1226 help 1227 The ARM compiler inserts calls to __aeabi_idiv() and 1228 __aeabi_uidiv() when it needs to perform division on signed 1229 and unsigned integers. Some v7 CPUs have support for the sdiv 1230 and udiv instructions that can be used to implement those 1231 functions. 1232 1233 Enabling this option allows the kernel to modify itself to 1234 replace the first two instructions of these library functions 1235 with the sdiv or udiv plus "bx lr" instructions when the CPU 1236 it is running on supports them. Typically this will be faster 1237 and less power intensive than running the original library 1238 code to do integer division. 1239 1240config AEABI 1241 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1242 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1243 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1244 help 1245 This option allows for the kernel to be compiled using the latest 1246 ARM ABI (aka EABI). This is only useful if you are using a user 1247 space environment that is also compiled with EABI. 1248 1249 Since there are major incompatibilities between the legacy ABI and 1250 EABI, especially with regard to structure member alignment, this 1251 option also changes the kernel syscall calling convention to 1252 disambiguate both ABIs and allow for backward compatibility support 1253 (selected with CONFIG_OABI_COMPAT). 1254 1255 To use this you need GCC version 4.0.0 or later. 1256 1257config OABI_COMPAT 1258 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1259 depends on AEABI && !THUMB2_KERNEL 1260 help 1261 This option preserves the old syscall interface along with the 1262 new (ARM EABI) one. It also provides a compatibility layer to 1263 intercept syscalls that have structure arguments which layout 1264 in memory differs between the legacy ABI and the new ARM EABI 1265 (only for non "thumb" binaries). This option adds a tiny 1266 overhead to all syscalls and produces a slightly larger kernel. 1267 1268 The seccomp filter system will not be available when this is 1269 selected, since there is no way yet to sensibly distinguish 1270 between calling conventions during filtering. 1271 1272 If you know you'll be using only pure EABI user space then you 1273 can say N here. If this option is not selected and you attempt 1274 to execute a legacy ABI binary then the result will be 1275 UNPREDICTABLE (in fact it can be predicted that it won't work 1276 at all). If in doubt say N. 1277 1278config ARCH_SELECT_MEMORY_MODEL 1279 def_bool y 1280 1281config ARCH_FLATMEM_ENABLE 1282 def_bool !(ARCH_RPC || ARCH_SA1100) 1283 1284config ARCH_SPARSEMEM_ENABLE 1285 def_bool !ARCH_FOOTBRIDGE 1286 select SPARSEMEM_STATIC if SPARSEMEM 1287 1288config HIGHMEM 1289 bool "High Memory Support" 1290 depends on MMU 1291 select KMAP_LOCAL 1292 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY 1293 help 1294 The address space of ARM processors is only 4 Gigabytes large 1295 and it has to accommodate user address space, kernel address 1296 space as well as some memory mapped IO. That means that, if you 1297 have a large amount of physical memory and/or IO, not all of the 1298 memory can be "permanently mapped" by the kernel. The physical 1299 memory that is not permanently mapped is called "high memory". 1300 1301 Depending on the selected kernel/user memory split, minimum 1302 vmalloc space and actual amount of RAM, you may not need this 1303 option which should result in a slightly faster kernel. 1304 1305 If unsure, say n. 1306 1307config HIGHPTE 1308 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1309 depends on HIGHMEM 1310 default y 1311 help 1312 The VM uses one page of physical memory for each page table. 1313 For systems with a lot of processes, this can use a lot of 1314 precious low memory, eventually leading to low memory being 1315 consumed by page tables. Setting this option will allow 1316 user-space 2nd level page tables to reside in high memory. 1317 1318config CPU_SW_DOMAIN_PAN 1319 bool "Enable use of CPU domains to implement privileged no-access" 1320 depends on MMU && !ARM_LPAE 1321 default y 1322 help 1323 Increase kernel security by ensuring that normal kernel accesses 1324 are unable to access userspace addresses. This can help prevent 1325 use-after-free bugs becoming an exploitable privilege escalation 1326 by ensuring that magic values (such as LIST_POISON) will always 1327 fault when dereferenced. 1328 1329 CPUs with low-vector mappings use a best-efforts implementation. 1330 Their lower 1MB needs to remain accessible for the vectors, but 1331 the remainder of userspace will become appropriately inaccessible. 1332 1333config HW_PERF_EVENTS 1334 def_bool y 1335 depends on ARM_PMU 1336 1337config ARM_MODULE_PLTS 1338 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1339 depends on MODULES 1340 select KASAN_VMALLOC if KASAN 1341 default y 1342 help 1343 Allocate PLTs when loading modules so that jumps and calls whose 1344 targets are too far away for their relative offsets to be encoded 1345 in the instructions themselves can be bounced via veneers in the 1346 module's PLT. This allows modules to be allocated in the generic 1347 vmalloc area after the dedicated module memory area has been 1348 exhausted. The modules will use slightly more memory, but after 1349 rounding up to page size, the actual memory footprint is usually 1350 the same. 1351 1352 Disabling this is usually safe for small single-platform 1353 configurations. If unsure, say y. 1354 1355config ARCH_FORCE_MAX_ORDER 1356 int "Order of maximal physically contiguous allocations" 1357 default "11" if SOC_AM33XX 1358 default "8" if SA1111 1359 default "10" 1360 help 1361 The kernel page allocator limits the size of maximal physically 1362 contiguous allocations. The limit is called MAX_ORDER and it 1363 defines the maximal power of two of number of pages that can be 1364 allocated as a single contiguous block. This option allows 1365 overriding the default setting when ability to allocate very 1366 large blocks of physically contiguous memory is required. 1367 1368 Don't change if unsure. 1369 1370config ALIGNMENT_TRAP 1371 def_bool CPU_CP15_MMU 1372 select HAVE_PROC_CPU if PROC_FS 1373 help 1374 ARM processors cannot fetch/store information which is not 1375 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1376 address divisible by 4. On 32-bit ARM processors, these non-aligned 1377 fetch/store instructions will be emulated in software if you say 1378 here, which has a severe performance impact. This is necessary for 1379 correct operation of some network protocols. With an IP-only 1380 configuration it is safe to say N, otherwise say Y. 1381 1382config UACCESS_WITH_MEMCPY 1383 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1384 depends on MMU 1385 default y if CPU_FEROCEON 1386 help 1387 Implement faster copy_to_user and clear_user methods for CPU 1388 cores where a 8-word STM instruction give significantly higher 1389 memory write throughput than a sequence of individual 32bit stores. 1390 1391 A possible side effect is a slight increase in scheduling latency 1392 between threads sharing the same address space if they invoke 1393 such copy operations with large buffers. 1394 1395 However, if the CPU data cache is using a write-allocate mode, 1396 this option is unlikely to provide any performance gain. 1397 1398config PARAVIRT 1399 bool "Enable paravirtualization code" 1400 help 1401 This changes the kernel so it can modify itself when it is run 1402 under a hypervisor, potentially improving performance significantly 1403 over full virtualization. 1404 1405config PARAVIRT_TIME_ACCOUNTING 1406 bool "Paravirtual steal time accounting" 1407 select PARAVIRT 1408 help 1409 Select this option to enable fine granularity task steal time 1410 accounting. Time spent executing other tasks in parallel with 1411 the current vCPU is discounted from the vCPU power. To account for 1412 that, there can be a small performance impact. 1413 1414 If in doubt, say N here. 1415 1416config XEN_DOM0 1417 def_bool y 1418 depends on XEN 1419 1420config XEN 1421 bool "Xen guest support on ARM" 1422 depends on ARM && AEABI && OF 1423 depends on CPU_V7 && !CPU_V6 1424 depends on !GENERIC_ATOMIC64 1425 depends on MMU 1426 select ARCH_DMA_ADDR_T_64BIT 1427 select ARM_PSCI 1428 select SWIOTLB 1429 select SWIOTLB_XEN 1430 select PARAVIRT 1431 help 1432 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1433 1434config CC_HAVE_STACKPROTECTOR_TLS 1435 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0) 1436 1437config STACKPROTECTOR_PER_TASK 1438 bool "Use a unique stack canary value for each task" 1439 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA 1440 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS 1441 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS 1442 default y 1443 help 1444 Due to the fact that GCC uses an ordinary symbol reference from 1445 which to load the value of the stack canary, this value can only 1446 change at reboot time on SMP systems, and all tasks running in the 1447 kernel's address space are forced to use the same canary value for 1448 the entire duration that the system is up. 1449 1450 Enable this option to switch to a different method that uses a 1451 different canary value for each task. 1452 1453endmenu 1454 1455menu "Boot options" 1456 1457config USE_OF 1458 bool "Flattened Device Tree support" 1459 select IRQ_DOMAIN 1460 select OF 1461 help 1462 Include support for flattened device tree machine descriptions. 1463 1464config ATAGS 1465 bool "Support for the traditional ATAGS boot data passing" 1466 default y 1467 help 1468 This is the traditional way of passing data to the kernel at boot 1469 time. If you are solely relying on the flattened device tree (or 1470 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1471 to remove ATAGS support from your kernel binary. 1472 1473config DEPRECATED_PARAM_STRUCT 1474 bool "Provide old way to pass kernel parameters" 1475 depends on ATAGS 1476 help 1477 This was deprecated in 2001 and announced to live on for 5 years. 1478 Some old boot loaders still use this way. 1479 1480# Compressed boot loader in ROM. Yes, we really want to ask about 1481# TEXT and BSS so we preserve their values in the config files. 1482config ZBOOT_ROM_TEXT 1483 hex "Compressed ROM boot loader base address" 1484 default 0x0 1485 help 1486 The physical address at which the ROM-able zImage is to be 1487 placed in the target. Platforms which normally make use of 1488 ROM-able zImage formats normally set this to a suitable 1489 value in their defconfig file. 1490 1491 If ZBOOT_ROM is not enabled, this has no effect. 1492 1493config ZBOOT_ROM_BSS 1494 hex "Compressed ROM boot loader BSS address" 1495 default 0x0 1496 help 1497 The base address of an area of read/write memory in the target 1498 for the ROM-able zImage which must be available while the 1499 decompressor is running. It must be large enough to hold the 1500 entire decompressed kernel plus an additional 128 KiB. 1501 Platforms which normally make use of ROM-able zImage formats 1502 normally set this to a suitable value in their defconfig file. 1503 1504 If ZBOOT_ROM is not enabled, this has no effect. 1505 1506config ZBOOT_ROM 1507 bool "Compressed boot loader in ROM/flash" 1508 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1509 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1510 help 1511 Say Y here if you intend to execute your compressed kernel image 1512 (zImage) directly from ROM or flash. If unsure, say N. 1513 1514config ARM_APPENDED_DTB 1515 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1516 depends on OF 1517 help 1518 With this option, the boot code will look for a device tree binary 1519 (DTB) appended to zImage 1520 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1521 1522 This is meant as a backward compatibility convenience for those 1523 systems with a bootloader that can't be upgraded to accommodate 1524 the documented boot protocol using a device tree. 1525 1526 Beware that there is very little in terms of protection against 1527 this option being confused by leftover garbage in memory that might 1528 look like a DTB header after a reboot if no actual DTB is appended 1529 to zImage. Do not leave this option active in a production kernel 1530 if you don't intend to always append a DTB. Proper passing of the 1531 location into r2 of a bootloader provided DTB is always preferable 1532 to this option. 1533 1534config ARM_ATAG_DTB_COMPAT 1535 bool "Supplement the appended DTB with traditional ATAG information" 1536 depends on ARM_APPENDED_DTB 1537 help 1538 Some old bootloaders can't be updated to a DTB capable one, yet 1539 they provide ATAGs with memory configuration, the ramdisk address, 1540 the kernel cmdline string, etc. Such information is dynamically 1541 provided by the bootloader and can't always be stored in a static 1542 DTB. To allow a device tree enabled kernel to be used with such 1543 bootloaders, this option allows zImage to extract the information 1544 from the ATAG list and store it at run time into the appended DTB. 1545 1546choice 1547 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1548 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1549 1550config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1551 bool "Use bootloader kernel arguments if available" 1552 help 1553 Uses the command-line options passed by the boot loader instead of 1554 the device tree bootargs property. If the boot loader doesn't provide 1555 any, the device tree bootargs property will be used. 1556 1557config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1558 bool "Extend with bootloader kernel arguments" 1559 help 1560 The command-line arguments provided by the boot loader will be 1561 appended to the the device tree bootargs property. 1562 1563endchoice 1564 1565config CMDLINE 1566 string "Default kernel command string" 1567 default "" 1568 help 1569 On some architectures (e.g. CATS), there is currently no way 1570 for the boot loader to pass arguments to the kernel. For these 1571 architectures, you should supply some command-line options at build 1572 time by entering them here. As a minimum, you should specify the 1573 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1574 1575choice 1576 prompt "Kernel command line type" if CMDLINE != "" 1577 default CMDLINE_FROM_BOOTLOADER 1578 1579config CMDLINE_FROM_BOOTLOADER 1580 bool "Use bootloader kernel arguments if available" 1581 help 1582 Uses the command-line options passed by the boot loader. If 1583 the boot loader doesn't provide any, the default kernel command 1584 string provided in CMDLINE will be used. 1585 1586config CMDLINE_EXTEND 1587 bool "Extend bootloader kernel arguments" 1588 help 1589 The command-line arguments provided by the boot loader will be 1590 appended to the default kernel command string. 1591 1592config CMDLINE_FORCE 1593 bool "Always use the default kernel command string" 1594 help 1595 Always use the default kernel command string, even if the boot 1596 loader passes other arguments to the kernel. 1597 This is useful if you cannot or don't want to change the 1598 command-line options your boot loader passes to the kernel. 1599endchoice 1600 1601config XIP_KERNEL 1602 bool "Kernel Execute-In-Place from ROM" 1603 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1604 depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP 1605 help 1606 Execute-In-Place allows the kernel to run from non-volatile storage 1607 directly addressable by the CPU, such as NOR flash. This saves RAM 1608 space since the text section of the kernel is not loaded from flash 1609 to RAM. Read-write sections, such as the data section and stack, 1610 are still copied to RAM. The XIP kernel is not compressed since 1611 it has to run directly from flash, so it will take more space to 1612 store it. The flash address used to link the kernel object files, 1613 and for storing it, is configuration dependent. Therefore, if you 1614 say Y here, you must know the proper physical address where to 1615 store the kernel image depending on your own flash memory usage. 1616 1617 Also note that the make target becomes "make xipImage" rather than 1618 "make zImage" or "make Image". The final kernel binary to put in 1619 ROM memory will be arch/arm/boot/xipImage. 1620 1621 If unsure, say N. 1622 1623config XIP_PHYS_ADDR 1624 hex "XIP Kernel Physical Location" 1625 depends on XIP_KERNEL 1626 default "0x00080000" 1627 help 1628 This is the physical address in your flash memory the kernel will 1629 be linked for and stored to. This address is dependent on your 1630 own flash usage. 1631 1632config XIP_DEFLATED_DATA 1633 bool "Store kernel .data section compressed in ROM" 1634 depends on XIP_KERNEL 1635 select ZLIB_INFLATE 1636 help 1637 Before the kernel is actually executed, its .data section has to be 1638 copied to RAM from ROM. This option allows for storing that data 1639 in compressed form and decompressed to RAM rather than merely being 1640 copied, saving some precious ROM space. A possible drawback is a 1641 slightly longer boot delay. 1642 1643config KEXEC 1644 bool "Kexec system call (EXPERIMENTAL)" 1645 depends on (!SMP || PM_SLEEP_SMP) 1646 depends on MMU 1647 select KEXEC_CORE 1648 help 1649 kexec is a system call that implements the ability to shutdown your 1650 current kernel, and to start another kernel. It is like a reboot 1651 but it is independent of the system firmware. And like a reboot 1652 you can start any kernel with it, not just Linux. 1653 1654 It is an ongoing process to be certain the hardware in a machine 1655 is properly shutdown, so do not be surprised if this code does not 1656 initially work for you. 1657 1658config ATAGS_PROC 1659 bool "Export atags in procfs" 1660 depends on ATAGS && KEXEC 1661 default y 1662 help 1663 Should the atags used to boot the kernel be exported in an "atags" 1664 file in procfs. Useful with kexec. 1665 1666config CRASH_DUMP 1667 bool "Build kdump crash kernel (EXPERIMENTAL)" 1668 help 1669 Generate crash dump after being started by kexec. This should 1670 be normally only set in special crash dump kernels which are 1671 loaded in the main kernel with kexec-tools into a specially 1672 reserved region and then later executed after a crash by 1673 kdump/kexec. The crash dump kernel must be compiled to a 1674 memory address not used by the main kernel 1675 1676 For more details see Documentation/admin-guide/kdump/kdump.rst 1677 1678config AUTO_ZRELADDR 1679 bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM 1680 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100) 1681 help 1682 ZRELADDR is the physical address where the decompressed kernel 1683 image will be placed. If AUTO_ZRELADDR is selected, the address 1684 will be determined at run-time, either by masking the current IP 1685 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1686 This assumes the zImage being placed in the first 128MB from 1687 start of memory. 1688 1689config EFI_STUB 1690 bool 1691 1692config EFI 1693 bool "UEFI runtime support" 1694 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1695 select UCS2_STRING 1696 select EFI_PARAMS_FROM_FDT 1697 select EFI_STUB 1698 select EFI_GENERIC_STUB 1699 select EFI_RUNTIME_WRAPPERS 1700 help 1701 This option provides support for runtime services provided 1702 by UEFI firmware (such as non-volatile variables, realtime 1703 clock, and platform reset). A UEFI stub is also provided to 1704 allow the kernel to be booted as an EFI application. This 1705 is only useful for kernels that may run on systems that have 1706 UEFI firmware. 1707 1708config DMI 1709 bool "Enable support for SMBIOS (DMI) tables" 1710 depends on EFI 1711 default y 1712 help 1713 This enables SMBIOS/DMI feature for systems. 1714 1715 This option is only useful on systems that have UEFI firmware. 1716 However, even with this option, the resultant kernel should 1717 continue to boot on existing non-UEFI platforms. 1718 1719 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1720 i.e., the the practice of identifying the platform via DMI to 1721 decide whether certain workarounds for buggy hardware and/or 1722 firmware need to be enabled. This would require the DMI subsystem 1723 to be enabled much earlier than we do on ARM, which is non-trivial. 1724 1725endmenu 1726 1727menu "CPU Power Management" 1728 1729source "drivers/cpufreq/Kconfig" 1730 1731source "drivers/cpuidle/Kconfig" 1732 1733endmenu 1734 1735menu "Floating point emulation" 1736 1737comment "At least one emulation must be selected" 1738 1739config FPE_NWFPE 1740 bool "NWFPE math emulation" 1741 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1742 help 1743 Say Y to include the NWFPE floating point emulator in the kernel. 1744 This is necessary to run most binaries. Linux does not currently 1745 support floating point hardware so you need to say Y here even if 1746 your machine has an FPA or floating point co-processor podule. 1747 1748 You may say N here if you are going to load the Acorn FPEmulator 1749 early in the bootup. 1750 1751config FPE_NWFPE_XP 1752 bool "Support extended precision" 1753 depends on FPE_NWFPE 1754 help 1755 Say Y to include 80-bit support in the kernel floating-point 1756 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1757 Note that gcc does not generate 80-bit operations by default, 1758 so in most cases this option only enlarges the size of the 1759 floating point emulator without any good reason. 1760 1761 You almost surely want to say N here. 1762 1763config FPE_FASTFPE 1764 bool "FastFPE math emulation (EXPERIMENTAL)" 1765 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1766 help 1767 Say Y here to include the FAST floating point emulator in the kernel. 1768 This is an experimental much faster emulator which now also has full 1769 precision for the mantissa. It does not support any exceptions. 1770 It is very simple, and approximately 3-6 times faster than NWFPE. 1771 1772 It should be sufficient for most programs. It may be not suitable 1773 for scientific calculations, but you have to check this for yourself. 1774 If you do not feel you need a faster FP emulation you should better 1775 choose NWFPE. 1776 1777config VFP 1778 bool "VFP-format floating point maths" 1779 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1780 help 1781 Say Y to include VFP support code in the kernel. This is needed 1782 if your hardware includes a VFP unit. 1783 1784 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1785 release notes and additional status information. 1786 1787 Say N if your target does not have VFP hardware. 1788 1789config VFPv3 1790 bool 1791 depends on VFP 1792 default y if CPU_V7 1793 1794config NEON 1795 bool "Advanced SIMD (NEON) Extension support" 1796 depends on VFPv3 && CPU_V7 1797 help 1798 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1799 Extension. 1800 1801config KERNEL_MODE_NEON 1802 bool "Support for NEON in kernel mode" 1803 depends on NEON && AEABI 1804 help 1805 Say Y to include support for NEON in kernel mode. 1806 1807endmenu 1808 1809menu "Power management options" 1810 1811source "kernel/power/Kconfig" 1812 1813config ARCH_SUSPEND_POSSIBLE 1814 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1815 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1816 def_bool y 1817 1818config ARM_CPU_SUSPEND 1819 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1820 depends on ARCH_SUSPEND_POSSIBLE 1821 1822config ARCH_HIBERNATION_POSSIBLE 1823 bool 1824 depends on MMU 1825 default y if ARCH_SUSPEND_POSSIBLE 1826 1827endmenu 1828 1829source "arch/arm/Kconfig.assembler" 1830