1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_CLOCKSOURCE_DATA 6 select ARCH_HAS_DEBUG_VIRTUAL 7 select ARCH_HAS_DEVMEM_IS_ALLOWED 8 select ARCH_HAS_ELF_RANDOMIZE 9 select ARCH_HAS_SET_MEMORY 10 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 11 select ARCH_HAS_STRICT_MODULE_RWX if MMU 12 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 13 select ARCH_HAVE_CUSTOM_GPIO_H 14 select ARCH_HAS_GCOV_PROFILE_ALL 15 select ARCH_MIGHT_HAVE_PC_PARPORT 16 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 17 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 18 select ARCH_SUPPORTS_ATOMIC_RMW 19 select ARCH_USE_BUILTIN_BSWAP 20 select ARCH_USE_CMPXCHG_LOCKREF 21 select ARCH_WANT_IPC_PARSE_VERSION 22 select BUILDTIME_EXTABLE_SORT if MMU 23 select CLONE_BACKWARDS 24 select CPU_PM if (SUSPEND || CPU_IDLE) 25 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 26 select DMA_NOOP_OPS if !MMU 27 select EDAC_SUPPORT 28 select EDAC_ATOMIC_SCRUB 29 select GENERIC_ALLOCATOR 30 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 31 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 32 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 33 select GENERIC_CPU_AUTOPROBE 34 select GENERIC_EARLY_IOREMAP 35 select GENERIC_IDLE_POLL_SETUP 36 select GENERIC_IRQ_PROBE 37 select GENERIC_IRQ_SHOW 38 select GENERIC_IRQ_SHOW_LEVEL 39 select GENERIC_PCI_IOMAP 40 select GENERIC_SCHED_CLOCK 41 select GENERIC_SMP_IDLE_THREAD 42 select GENERIC_STRNCPY_FROM_USER 43 select GENERIC_STRNLEN_USER 44 select HANDLE_DOMAIN_IRQ 45 select HARDIRQS_SW_RESEND 46 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 47 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 48 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 49 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 50 select HAVE_ARCH_MMAP_RND_BITS if MMU 51 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 52 select HAVE_ARCH_TRACEHOOK 53 select HAVE_ARM_SMCCC if CPU_V7 54 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 55 select HAVE_CC_STACKPROTECTOR 56 select HAVE_CONTEXT_TRACKING 57 select HAVE_C_RECORDMCOUNT 58 select HAVE_DEBUG_KMEMLEAK 59 select HAVE_DMA_API_DEBUG 60 select HAVE_DMA_CONTIGUOUS if MMU 61 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 62 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 63 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 64 select HAVE_EXIT_THREAD 65 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 66 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 67 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 68 select HAVE_GCC_PLUGINS 69 select HAVE_GENERIC_DMA_COHERENT 70 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 71 select HAVE_IDE if PCI || ISA || PCMCIA 72 select HAVE_IRQ_TIME_ACCOUNTING 73 select HAVE_KERNEL_GZIP 74 select HAVE_KERNEL_LZ4 75 select HAVE_KERNEL_LZMA 76 select HAVE_KERNEL_LZO 77 select HAVE_KERNEL_XZ 78 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 79 select HAVE_KRETPROBES if (HAVE_KPROBES) 80 select HAVE_MEMBLOCK 81 select HAVE_MOD_ARCH_SPECIFIC 82 select HAVE_NMI 83 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 84 select HAVE_OPTPROBES if !THUMB2_KERNEL 85 select HAVE_PERF_EVENTS 86 select HAVE_PERF_REGS 87 select HAVE_PERF_USER_STACK_DUMP 88 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 89 select HAVE_REGS_AND_STACK_ACCESS_API 90 select HAVE_SYSCALL_TRACEPOINTS 91 select HAVE_UID16 92 select HAVE_VIRT_CPU_ACCOUNTING_GEN 93 select IRQ_FORCED_THREADING 94 select MODULES_USE_ELF_REL 95 select NO_BOOTMEM 96 select OF_EARLY_FLATTREE if OF 97 select OF_RESERVED_MEM if OF 98 select OLD_SIGACTION 99 select OLD_SIGSUSPEND3 100 select PERF_USE_VMALLOC 101 select RTC_LIB 102 select SYS_SUPPORTS_APM_EMULATION 103 # Above selects are sorted alphabetically; please add new ones 104 # according to that. Thanks. 105 help 106 The ARM series is a line of low-power-consumption RISC chip designs 107 licensed by ARM Ltd and targeted at embedded applications and 108 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 109 manufactured, but legacy ARM-based PC hardware remains popular in 110 Europe. There is an ARM Linux project with a web page at 111 <http://www.arm.linux.org.uk/>. 112 113config ARM_HAS_SG_CHAIN 114 select ARCH_HAS_SG_CHAIN 115 bool 116 117config NEED_SG_DMA_LENGTH 118 bool 119 120config ARM_DMA_USE_IOMMU 121 bool 122 select ARM_HAS_SG_CHAIN 123 select NEED_SG_DMA_LENGTH 124 125if ARM_DMA_USE_IOMMU 126 127config ARM_DMA_IOMMU_ALIGNMENT 128 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 129 range 4 9 130 default 8 131 help 132 DMA mapping framework by default aligns all buffers to the smallest 133 PAGE_SIZE order which is greater than or equal to the requested buffer 134 size. This works well for buffers up to a few hundreds kilobytes, but 135 for larger buffers it just a waste of address space. Drivers which has 136 relatively small addressing window (like 64Mib) might run out of 137 virtual space with just a few allocations. 138 139 With this parameter you can specify the maximum PAGE_SIZE order for 140 DMA IOMMU buffers. Larger buffers will be aligned only to this 141 specified order. The order is expressed as a power of two multiplied 142 by the PAGE_SIZE. 143 144endif 145 146config MIGHT_HAVE_PCI 147 bool 148 149config SYS_SUPPORTS_APM_EMULATION 150 bool 151 152config HAVE_TCM 153 bool 154 select GENERIC_ALLOCATOR 155 156config HAVE_PROC_CPU 157 bool 158 159config NO_IOPORT_MAP 160 bool 161 162config EISA 163 bool 164 ---help--- 165 The Extended Industry Standard Architecture (EISA) bus was 166 developed as an open alternative to the IBM MicroChannel bus. 167 168 The EISA bus provided some of the features of the IBM MicroChannel 169 bus while maintaining backward compatibility with cards made for 170 the older ISA bus. The EISA bus saw limited use between 1988 and 171 1995 when it was made obsolete by the PCI bus. 172 173 Say Y here if you are building a kernel for an EISA-based machine. 174 175 Otherwise, say N. 176 177config SBUS 178 bool 179 180config STACKTRACE_SUPPORT 181 bool 182 default y 183 184config LOCKDEP_SUPPORT 185 bool 186 default y 187 188config TRACE_IRQFLAGS_SUPPORT 189 bool 190 default !CPU_V7M 191 192config RWSEM_XCHGADD_ALGORITHM 193 bool 194 default y 195 196config ARCH_HAS_ILOG2_U32 197 bool 198 199config ARCH_HAS_ILOG2_U64 200 bool 201 202config ARCH_HAS_BANDGAP 203 bool 204 205config FIX_EARLYCON_MEM 206 def_bool y if MMU 207 208config GENERIC_HWEIGHT 209 bool 210 default y 211 212config GENERIC_CALIBRATE_DELAY 213 bool 214 default y 215 216config ARCH_MAY_HAVE_PC_FDC 217 bool 218 219config ZONE_DMA 220 bool 221 222config NEED_DMA_MAP_STATE 223 def_bool y 224 225config ARCH_SUPPORTS_UPROBES 226 def_bool y 227 228config ARCH_HAS_DMA_SET_COHERENT_MASK 229 bool 230 231config GENERIC_ISA_DMA 232 bool 233 234config FIQ 235 bool 236 237config NEED_RET_TO_USER 238 bool 239 240config ARCH_MTD_XIP 241 bool 242 243config VECTORS_BASE 244 hex 245 default 0xffff0000 if MMU || CPU_HIGH_VECTOR 246 default DRAM_BASE if REMAP_VECTORS_TO_RAM 247 default 0x00000000 248 help 249 The base address of exception vectors. This must be two pages 250 in size. 251 252config ARM_PATCH_PHYS_VIRT 253 bool "Patch physical to virtual translations at runtime" if EMBEDDED 254 default y 255 depends on !XIP_KERNEL && MMU 256 help 257 Patch phys-to-virt and virt-to-phys translation functions at 258 boot and module load time according to the position of the 259 kernel in system memory. 260 261 This can only be used with non-XIP MMU kernels where the base 262 of physical memory is at a 16MB boundary. 263 264 Only disable this option if you know that you do not require 265 this feature (eg, building a kernel for a single machine) and 266 you need to shrink the kernel to the minimal size. 267 268config NEED_MACH_IO_H 269 bool 270 help 271 Select this when mach/io.h is required to provide special 272 definitions for this platform. The need for mach/io.h should 273 be avoided when possible. 274 275config NEED_MACH_MEMORY_H 276 bool 277 help 278 Select this when mach/memory.h is required to provide special 279 definitions for this platform. The need for mach/memory.h should 280 be avoided when possible. 281 282config PHYS_OFFSET 283 hex "Physical address of main memory" if MMU 284 depends on !ARM_PATCH_PHYS_VIRT 285 default DRAM_BASE if !MMU 286 default 0x00000000 if ARCH_EBSA110 || \ 287 ARCH_FOOTBRIDGE || \ 288 ARCH_INTEGRATOR || \ 289 ARCH_IOP13XX || \ 290 ARCH_KS8695 || \ 291 ARCH_REALVIEW 292 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 293 default 0x20000000 if ARCH_S5PV210 294 default 0xc0000000 if ARCH_SA1100 295 help 296 Please provide the physical address corresponding to the 297 location of main memory in your system. 298 299config GENERIC_BUG 300 def_bool y 301 depends on BUG 302 303config PGTABLE_LEVELS 304 int 305 default 3 if ARM_LPAE 306 default 2 307 308source "init/Kconfig" 309 310source "kernel/Kconfig.freezer" 311 312menu "System Type" 313 314config MMU 315 bool "MMU-based Paged Memory Management Support" 316 default y 317 help 318 Select if you want MMU-based virtualised addressing space 319 support by paged memory management. If unsure, say 'Y'. 320 321config ARCH_MMAP_RND_BITS_MIN 322 default 8 323 324config ARCH_MMAP_RND_BITS_MAX 325 default 14 if PAGE_OFFSET=0x40000000 326 default 15 if PAGE_OFFSET=0x80000000 327 default 16 328 329# 330# The "ARM system type" choice list is ordered alphabetically by option 331# text. Please add new entries in the option alphabetic order. 332# 333choice 334 prompt "ARM system type" 335 default ARM_SINGLE_ARMV7M if !MMU 336 default ARCH_MULTIPLATFORM if MMU 337 338config ARCH_MULTIPLATFORM 339 bool "Allow multiple platforms to be selected" 340 depends on MMU 341 select ARM_HAS_SG_CHAIN 342 select ARM_PATCH_PHYS_VIRT 343 select AUTO_ZRELADDR 344 select TIMER_OF 345 select COMMON_CLK 346 select GENERIC_CLOCKEVENTS 347 select MIGHT_HAVE_PCI 348 select MULTI_IRQ_HANDLER 349 select PCI_DOMAINS if PCI 350 select SPARSE_IRQ 351 select USE_OF 352 353config ARM_SINGLE_ARMV7M 354 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 355 depends on !MMU 356 select ARM_NVIC 357 select AUTO_ZRELADDR 358 select TIMER_OF 359 select COMMON_CLK 360 select CPU_V7M 361 select GENERIC_CLOCKEVENTS 362 select NO_IOPORT_MAP 363 select SPARSE_IRQ 364 select USE_OF 365 366config ARCH_EBSA110 367 bool "EBSA-110" 368 select ARCH_USES_GETTIMEOFFSET 369 select CPU_SA110 370 select ISA 371 select NEED_MACH_IO_H 372 select NEED_MACH_MEMORY_H 373 select NO_IOPORT_MAP 374 help 375 This is an evaluation board for the StrongARM processor available 376 from Digital. It has limited hardware on-board, including an 377 Ethernet interface, two PCMCIA sockets, two serial ports and a 378 parallel port. 379 380config ARCH_EP93XX 381 bool "EP93xx-based" 382 select ARCH_HAS_HOLES_MEMORYMODEL 383 select ARM_AMBA 384 imply ARM_PATCH_PHYS_VIRT 385 select ARM_VIC 386 select AUTO_ZRELADDR 387 select CLKDEV_LOOKUP 388 select CLKSRC_MMIO 389 select CPU_ARM920T 390 select GENERIC_CLOCKEVENTS 391 select GPIOLIB 392 help 393 This enables support for the Cirrus EP93xx series of CPUs. 394 395config ARCH_FOOTBRIDGE 396 bool "FootBridge" 397 select CPU_SA110 398 select FOOTBRIDGE 399 select GENERIC_CLOCKEVENTS 400 select HAVE_IDE 401 select NEED_MACH_IO_H if !MMU 402 select NEED_MACH_MEMORY_H 403 help 404 Support for systems based on the DC21285 companion chip 405 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 406 407config ARCH_NETX 408 bool "Hilscher NetX based" 409 select ARM_VIC 410 select CLKSRC_MMIO 411 select CPU_ARM926T 412 select GENERIC_CLOCKEVENTS 413 help 414 This enables support for systems based on the Hilscher NetX Soc 415 416config ARCH_IOP13XX 417 bool "IOP13xx-based" 418 depends on MMU 419 select CPU_XSC3 420 select NEED_MACH_MEMORY_H 421 select NEED_RET_TO_USER 422 select PCI 423 select PLAT_IOP 424 select VMSPLIT_1G 425 select SPARSE_IRQ 426 help 427 Support for Intel's IOP13XX (XScale) family of processors. 428 429config ARCH_IOP32X 430 bool "IOP32x-based" 431 depends on MMU 432 select CPU_XSCALE 433 select GPIO_IOP 434 select GPIOLIB 435 select NEED_RET_TO_USER 436 select PCI 437 select PLAT_IOP 438 help 439 Support for Intel's 80219 and IOP32X (XScale) family of 440 processors. 441 442config ARCH_IOP33X 443 bool "IOP33x-based" 444 depends on MMU 445 select CPU_XSCALE 446 select GPIO_IOP 447 select GPIOLIB 448 select NEED_RET_TO_USER 449 select PCI 450 select PLAT_IOP 451 help 452 Support for Intel's IOP33X (XScale) family of processors. 453 454config ARCH_IXP4XX 455 bool "IXP4xx-based" 456 depends on MMU 457 select ARCH_HAS_DMA_SET_COHERENT_MASK 458 select ARCH_SUPPORTS_BIG_ENDIAN 459 select CLKSRC_MMIO 460 select CPU_XSCALE 461 select DMABOUNCE if PCI 462 select GENERIC_CLOCKEVENTS 463 select GPIOLIB 464 select MIGHT_HAVE_PCI 465 select NEED_MACH_IO_H 466 select USB_EHCI_BIG_ENDIAN_DESC 467 select USB_EHCI_BIG_ENDIAN_MMIO 468 help 469 Support for Intel's IXP4XX (XScale) family of processors. 470 471config ARCH_DOVE 472 bool "Marvell Dove" 473 select CPU_PJ4 474 select GENERIC_CLOCKEVENTS 475 select GPIOLIB 476 select MIGHT_HAVE_PCI 477 select MULTI_IRQ_HANDLER 478 select MVEBU_MBUS 479 select PINCTRL 480 select PINCTRL_DOVE 481 select PLAT_ORION_LEGACY 482 select SPARSE_IRQ 483 select PM_GENERIC_DOMAINS if PM 484 help 485 Support for the Marvell Dove SoC 88AP510 486 487config ARCH_KS8695 488 bool "Micrel/Kendin KS8695" 489 select CLKSRC_MMIO 490 select CPU_ARM922T 491 select GENERIC_CLOCKEVENTS 492 select GPIOLIB 493 select NEED_MACH_MEMORY_H 494 help 495 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 496 System-on-Chip devices. 497 498config ARCH_W90X900 499 bool "Nuvoton W90X900 CPU" 500 select CLKDEV_LOOKUP 501 select CLKSRC_MMIO 502 select CPU_ARM926T 503 select GENERIC_CLOCKEVENTS 504 select GPIOLIB 505 help 506 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 507 At present, the w90x900 has been renamed nuc900, regarding 508 the ARM series product line, you can login the following 509 link address to know more. 510 511 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 512 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 513 514config ARCH_LPC32XX 515 bool "NXP LPC32XX" 516 select ARM_AMBA 517 select CLKDEV_LOOKUP 518 select CLKSRC_LPC32XX 519 select COMMON_CLK 520 select CPU_ARM926T 521 select GENERIC_CLOCKEVENTS 522 select GPIOLIB 523 select MULTI_IRQ_HANDLER 524 select SPARSE_IRQ 525 select USE_OF 526 help 527 Support for the NXP LPC32XX family of processors 528 529config ARCH_PXA 530 bool "PXA2xx/PXA3xx-based" 531 depends on MMU 532 select ARCH_MTD_XIP 533 select ARM_CPU_SUSPEND if PM 534 select AUTO_ZRELADDR 535 select COMMON_CLK 536 select CLKDEV_LOOKUP 537 select CLKSRC_PXA 538 select CLKSRC_MMIO 539 select TIMER_OF 540 select CPU_XSCALE if !CPU_XSC3 541 select GENERIC_CLOCKEVENTS 542 select GPIO_PXA 543 select GPIOLIB 544 select HAVE_IDE 545 select IRQ_DOMAIN 546 select MULTI_IRQ_HANDLER 547 select PLAT_PXA 548 select SPARSE_IRQ 549 help 550 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 551 552config ARCH_RPC 553 bool "RiscPC" 554 depends on MMU 555 select ARCH_ACORN 556 select ARCH_MAY_HAVE_PC_FDC 557 select ARCH_SPARSEMEM_ENABLE 558 select ARCH_USES_GETTIMEOFFSET 559 select CPU_SA110 560 select FIQ 561 select HAVE_IDE 562 select HAVE_PATA_PLATFORM 563 select ISA_DMA_API 564 select NEED_MACH_IO_H 565 select NEED_MACH_MEMORY_H 566 select NO_IOPORT_MAP 567 help 568 On the Acorn Risc-PC, Linux can support the internal IDE disk and 569 CD-ROM interface, serial and parallel port, and the floppy drive. 570 571config ARCH_SA1100 572 bool "SA1100-based" 573 select ARCH_MTD_XIP 574 select ARCH_SPARSEMEM_ENABLE 575 select CLKDEV_LOOKUP 576 select CLKSRC_MMIO 577 select CLKSRC_PXA 578 select TIMER_OF if OF 579 select CPU_FREQ 580 select CPU_SA1100 581 select GENERIC_CLOCKEVENTS 582 select GPIOLIB 583 select HAVE_IDE 584 select IRQ_DOMAIN 585 select ISA 586 select MULTI_IRQ_HANDLER 587 select NEED_MACH_MEMORY_H 588 select SPARSE_IRQ 589 help 590 Support for StrongARM 11x0 based boards. 591 592config ARCH_S3C24XX 593 bool "Samsung S3C24XX SoCs" 594 select ATAGS 595 select CLKDEV_LOOKUP 596 select CLKSRC_SAMSUNG_PWM 597 select GENERIC_CLOCKEVENTS 598 select GPIO_SAMSUNG 599 select GPIOLIB 600 select HAVE_S3C2410_I2C if I2C 601 select HAVE_S3C2410_WATCHDOG if WATCHDOG 602 select HAVE_S3C_RTC if RTC_CLASS 603 select MULTI_IRQ_HANDLER 604 select NEED_MACH_IO_H 605 select SAMSUNG_ATAGS 606 help 607 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 608 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 609 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 610 Samsung SMDK2410 development board (and derivatives). 611 612config ARCH_DAVINCI 613 bool "TI DaVinci" 614 select ARCH_HAS_HOLES_MEMORYMODEL 615 select CLKDEV_LOOKUP 616 select CPU_ARM926T 617 select GENERIC_ALLOCATOR 618 select GENERIC_CLOCKEVENTS 619 select GENERIC_IRQ_CHIP 620 select GPIOLIB 621 select HAVE_IDE 622 select USE_OF 623 select ZONE_DMA 624 help 625 Support for TI's DaVinci platform. 626 627config ARCH_OMAP1 628 bool "TI OMAP1" 629 depends on MMU 630 select ARCH_HAS_HOLES_MEMORYMODEL 631 select ARCH_OMAP 632 select CLKDEV_LOOKUP 633 select CLKSRC_MMIO 634 select GENERIC_CLOCKEVENTS 635 select GENERIC_IRQ_CHIP 636 select GPIOLIB 637 select HAVE_IDE 638 select IRQ_DOMAIN 639 select MULTI_IRQ_HANDLER 640 select NEED_MACH_IO_H if PCCARD 641 select NEED_MACH_MEMORY_H 642 select SPARSE_IRQ 643 help 644 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 645 646endchoice 647 648menu "Multiple platform selection" 649 depends on ARCH_MULTIPLATFORM 650 651comment "CPU Core family selection" 652 653config ARCH_MULTI_V4 654 bool "ARMv4 based platforms (FA526)" 655 depends on !ARCH_MULTI_V6_V7 656 select ARCH_MULTI_V4_V5 657 select CPU_FA526 658 659config ARCH_MULTI_V4T 660 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 661 depends on !ARCH_MULTI_V6_V7 662 select ARCH_MULTI_V4_V5 663 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 664 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 665 CPU_ARM925T || CPU_ARM940T) 666 667config ARCH_MULTI_V5 668 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 669 depends on !ARCH_MULTI_V6_V7 670 select ARCH_MULTI_V4_V5 671 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 672 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 673 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 674 675config ARCH_MULTI_V4_V5 676 bool 677 678config ARCH_MULTI_V6 679 bool "ARMv6 based platforms (ARM11)" 680 select ARCH_MULTI_V6_V7 681 select CPU_V6K 682 683config ARCH_MULTI_V7 684 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 685 default y 686 select ARCH_MULTI_V6_V7 687 select CPU_V7 688 select HAVE_SMP 689 690config ARCH_MULTI_V6_V7 691 bool 692 select MIGHT_HAVE_CACHE_L2X0 693 694config ARCH_MULTI_CPU_AUTO 695 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 696 select ARCH_MULTI_V5 697 698endmenu 699 700config ARCH_VIRT 701 bool "Dummy Virtual Machine" 702 depends on ARCH_MULTI_V7 703 select ARM_AMBA 704 select ARM_GIC 705 select ARM_GIC_V2M if PCI 706 select ARM_GIC_V3 707 select ARM_GIC_V3_ITS if PCI 708 select ARM_PSCI 709 select HAVE_ARM_ARCH_TIMER 710 711# 712# This is sorted alphabetically by mach-* pathname. However, plat-* 713# Kconfigs may be included either alphabetically (according to the 714# plat- suffix) or along side the corresponding mach-* source. 715# 716source "arch/arm/mach-mvebu/Kconfig" 717 718source "arch/arm/mach-actions/Kconfig" 719 720source "arch/arm/mach-alpine/Kconfig" 721 722source "arch/arm/mach-artpec/Kconfig" 723 724source "arch/arm/mach-asm9260/Kconfig" 725 726source "arch/arm/mach-at91/Kconfig" 727 728source "arch/arm/mach-axxia/Kconfig" 729 730source "arch/arm/mach-bcm/Kconfig" 731 732source "arch/arm/mach-berlin/Kconfig" 733 734source "arch/arm/mach-clps711x/Kconfig" 735 736source "arch/arm/mach-cns3xxx/Kconfig" 737 738source "arch/arm/mach-davinci/Kconfig" 739 740source "arch/arm/mach-digicolor/Kconfig" 741 742source "arch/arm/mach-dove/Kconfig" 743 744source "arch/arm/mach-ep93xx/Kconfig" 745 746source "arch/arm/mach-footbridge/Kconfig" 747 748source "arch/arm/mach-gemini/Kconfig" 749 750source "arch/arm/mach-highbank/Kconfig" 751 752source "arch/arm/mach-hisi/Kconfig" 753 754source "arch/arm/mach-integrator/Kconfig" 755 756source "arch/arm/mach-iop32x/Kconfig" 757 758source "arch/arm/mach-iop33x/Kconfig" 759 760source "arch/arm/mach-iop13xx/Kconfig" 761 762source "arch/arm/mach-ixp4xx/Kconfig" 763 764source "arch/arm/mach-keystone/Kconfig" 765 766source "arch/arm/mach-ks8695/Kconfig" 767 768source "arch/arm/mach-meson/Kconfig" 769 770source "arch/arm/mach-moxart/Kconfig" 771 772source "arch/arm/mach-aspeed/Kconfig" 773 774source "arch/arm/mach-mv78xx0/Kconfig" 775 776source "arch/arm/mach-imx/Kconfig" 777 778source "arch/arm/mach-mediatek/Kconfig" 779 780source "arch/arm/mach-mxs/Kconfig" 781 782source "arch/arm/mach-netx/Kconfig" 783 784source "arch/arm/mach-nomadik/Kconfig" 785 786source "arch/arm/mach-nspire/Kconfig" 787 788source "arch/arm/plat-omap/Kconfig" 789 790source "arch/arm/mach-omap1/Kconfig" 791 792source "arch/arm/mach-omap2/Kconfig" 793 794source "arch/arm/mach-orion5x/Kconfig" 795 796source "arch/arm/mach-picoxcell/Kconfig" 797 798source "arch/arm/mach-pxa/Kconfig" 799source "arch/arm/plat-pxa/Kconfig" 800 801source "arch/arm/mach-mmp/Kconfig" 802 803source "arch/arm/mach-oxnas/Kconfig" 804 805source "arch/arm/mach-qcom/Kconfig" 806 807source "arch/arm/mach-realview/Kconfig" 808 809source "arch/arm/mach-rockchip/Kconfig" 810 811source "arch/arm/mach-sa1100/Kconfig" 812 813source "arch/arm/mach-socfpga/Kconfig" 814 815source "arch/arm/mach-spear/Kconfig" 816 817source "arch/arm/mach-sti/Kconfig" 818 819source "arch/arm/mach-stm32/Kconfig" 820 821source "arch/arm/mach-s3c24xx/Kconfig" 822 823source "arch/arm/mach-s3c64xx/Kconfig" 824 825source "arch/arm/mach-s5pv210/Kconfig" 826 827source "arch/arm/mach-exynos/Kconfig" 828source "arch/arm/plat-samsung/Kconfig" 829 830source "arch/arm/mach-shmobile/Kconfig" 831 832source "arch/arm/mach-sunxi/Kconfig" 833 834source "arch/arm/mach-prima2/Kconfig" 835 836source "arch/arm/mach-tango/Kconfig" 837 838source "arch/arm/mach-tegra/Kconfig" 839 840source "arch/arm/mach-u300/Kconfig" 841 842source "arch/arm/mach-uniphier/Kconfig" 843 844source "arch/arm/mach-ux500/Kconfig" 845 846source "arch/arm/mach-versatile/Kconfig" 847 848source "arch/arm/mach-vexpress/Kconfig" 849source "arch/arm/plat-versatile/Kconfig" 850 851source "arch/arm/mach-vt8500/Kconfig" 852 853source "arch/arm/mach-w90x900/Kconfig" 854 855source "arch/arm/mach-zx/Kconfig" 856 857source "arch/arm/mach-zynq/Kconfig" 858 859# ARMv7-M architecture 860config ARCH_EFM32 861 bool "Energy Micro efm32" 862 depends on ARM_SINGLE_ARMV7M 863 select GPIOLIB 864 help 865 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 866 processors. 867 868config ARCH_LPC18XX 869 bool "NXP LPC18xx/LPC43xx" 870 depends on ARM_SINGLE_ARMV7M 871 select ARCH_HAS_RESET_CONTROLLER 872 select ARM_AMBA 873 select CLKSRC_LPC32XX 874 select PINCTRL 875 help 876 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 877 high performance microcontrollers. 878 879config ARCH_MPS2 880 bool "ARM MPS2 platform" 881 depends on ARM_SINGLE_ARMV7M 882 select ARM_AMBA 883 select CLKSRC_MPS2 884 help 885 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 886 with a range of available cores like Cortex-M3/M4/M7. 887 888 Please, note that depends which Application Note is used memory map 889 for the platform may vary, so adjustment of RAM base might be needed. 890 891# Definitions to make life easier 892config ARCH_ACORN 893 bool 894 895config PLAT_IOP 896 bool 897 select GENERIC_CLOCKEVENTS 898 899config PLAT_ORION 900 bool 901 select CLKSRC_MMIO 902 select COMMON_CLK 903 select GENERIC_IRQ_CHIP 904 select IRQ_DOMAIN 905 906config PLAT_ORION_LEGACY 907 bool 908 select PLAT_ORION 909 910config PLAT_PXA 911 bool 912 913config PLAT_VERSATILE 914 bool 915 916source "arch/arm/firmware/Kconfig" 917 918source arch/arm/mm/Kconfig 919 920config IWMMXT 921 bool "Enable iWMMXt support" 922 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 923 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 924 help 925 Enable support for iWMMXt context switching at run time if 926 running on a CPU that supports it. 927 928config MULTI_IRQ_HANDLER 929 bool 930 help 931 Allow each machine to specify it's own IRQ handler at run time. 932 933if !MMU 934source "arch/arm/Kconfig-nommu" 935endif 936 937config PJ4B_ERRATA_4742 938 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 939 depends on CPU_PJ4B && MACH_ARMADA_370 940 default y 941 help 942 When coming out of either a Wait for Interrupt (WFI) or a Wait for 943 Event (WFE) IDLE states, a specific timing sensitivity exists between 944 the retiring WFI/WFE instructions and the newly issued subsequent 945 instructions. This sensitivity can result in a CPU hang scenario. 946 Workaround: 947 The software must insert either a Data Synchronization Barrier (DSB) 948 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 949 instruction 950 951config ARM_ERRATA_326103 952 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 953 depends on CPU_V6 954 help 955 Executing a SWP instruction to read-only memory does not set bit 11 956 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 957 treat the access as a read, preventing a COW from occurring and 958 causing the faulting task to livelock. 959 960config ARM_ERRATA_411920 961 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 962 depends on CPU_V6 || CPU_V6K 963 help 964 Invalidation of the Instruction Cache operation can 965 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 966 It does not affect the MPCore. This option enables the ARM Ltd. 967 recommended workaround. 968 969config ARM_ERRATA_430973 970 bool "ARM errata: Stale prediction on replaced interworking branch" 971 depends on CPU_V7 972 help 973 This option enables the workaround for the 430973 Cortex-A8 974 r1p* erratum. If a code sequence containing an ARM/Thumb 975 interworking branch is replaced with another code sequence at the 976 same virtual address, whether due to self-modifying code or virtual 977 to physical address re-mapping, Cortex-A8 does not recover from the 978 stale interworking branch prediction. This results in Cortex-A8 979 executing the new code sequence in the incorrect ARM or Thumb state. 980 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 981 and also flushes the branch target cache at every context switch. 982 Note that setting specific bits in the ACTLR register may not be 983 available in non-secure mode. 984 985config ARM_ERRATA_458693 986 bool "ARM errata: Processor deadlock when a false hazard is created" 987 depends on CPU_V7 988 depends on !ARCH_MULTIPLATFORM 989 help 990 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 991 erratum. For very specific sequences of memory operations, it is 992 possible for a hazard condition intended for a cache line to instead 993 be incorrectly associated with a different cache line. This false 994 hazard might then cause a processor deadlock. The workaround enables 995 the L1 caching of the NEON accesses and disables the PLD instruction 996 in the ACTLR register. Note that setting specific bits in the ACTLR 997 register may not be available in non-secure mode. 998 999config ARM_ERRATA_460075 1000 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 1001 depends on CPU_V7 1002 depends on !ARCH_MULTIPLATFORM 1003 help 1004 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 1005 erratum. Any asynchronous access to the L2 cache may encounter a 1006 situation in which recent store transactions to the L2 cache are lost 1007 and overwritten with stale memory contents from external memory. The 1008 workaround disables the write-allocate mode for the L2 cache via the 1009 ACTLR register. Note that setting specific bits in the ACTLR register 1010 may not be available in non-secure mode. 1011 1012config ARM_ERRATA_742230 1013 bool "ARM errata: DMB operation may be faulty" 1014 depends on CPU_V7 && SMP 1015 depends on !ARCH_MULTIPLATFORM 1016 help 1017 This option enables the workaround for the 742230 Cortex-A9 1018 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1019 between two write operations may not ensure the correct visibility 1020 ordering of the two writes. This workaround sets a specific bit in 1021 the diagnostic register of the Cortex-A9 which causes the DMB 1022 instruction to behave as a DSB, ensuring the correct behaviour of 1023 the two writes. 1024 1025config ARM_ERRATA_742231 1026 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1027 depends on CPU_V7 && SMP 1028 depends on !ARCH_MULTIPLATFORM 1029 help 1030 This option enables the workaround for the 742231 Cortex-A9 1031 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1032 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1033 accessing some data located in the same cache line, may get corrupted 1034 data due to bad handling of the address hazard when the line gets 1035 replaced from one of the CPUs at the same time as another CPU is 1036 accessing it. This workaround sets specific bits in the diagnostic 1037 register of the Cortex-A9 which reduces the linefill issuing 1038 capabilities of the processor. 1039 1040config ARM_ERRATA_643719 1041 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1042 depends on CPU_V7 && SMP 1043 default y 1044 help 1045 This option enables the workaround for the 643719 Cortex-A9 (prior to 1046 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1047 register returns zero when it should return one. The workaround 1048 corrects this value, ensuring cache maintenance operations which use 1049 it behave as intended and avoiding data corruption. 1050 1051config ARM_ERRATA_720789 1052 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1053 depends on CPU_V7 1054 help 1055 This option enables the workaround for the 720789 Cortex-A9 (prior to 1056 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1057 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1058 As a consequence of this erratum, some TLB entries which should be 1059 invalidated are not, resulting in an incoherency in the system page 1060 tables. The workaround changes the TLB flushing routines to invalidate 1061 entries regardless of the ASID. 1062 1063config ARM_ERRATA_743622 1064 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1065 depends on CPU_V7 1066 depends on !ARCH_MULTIPLATFORM 1067 help 1068 This option enables the workaround for the 743622 Cortex-A9 1069 (r2p*) erratum. Under very rare conditions, a faulty 1070 optimisation in the Cortex-A9 Store Buffer may lead to data 1071 corruption. This workaround sets a specific bit in the diagnostic 1072 register of the Cortex-A9 which disables the Store Buffer 1073 optimisation, preventing the defect from occurring. This has no 1074 visible impact on the overall performance or power consumption of the 1075 processor. 1076 1077config ARM_ERRATA_751472 1078 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1079 depends on CPU_V7 1080 depends on !ARCH_MULTIPLATFORM 1081 help 1082 This option enables the workaround for the 751472 Cortex-A9 (prior 1083 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1084 completion of a following broadcasted operation if the second 1085 operation is received by a CPU before the ICIALLUIS has completed, 1086 potentially leading to corrupted entries in the cache or TLB. 1087 1088config ARM_ERRATA_754322 1089 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1090 depends on CPU_V7 1091 help 1092 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1093 r3p*) erratum. A speculative memory access may cause a page table walk 1094 which starts prior to an ASID switch but completes afterwards. This 1095 can populate the micro-TLB with a stale entry which may be hit with 1096 the new ASID. This workaround places two dsb instructions in the mm 1097 switching code so that no page table walks can cross the ASID switch. 1098 1099config ARM_ERRATA_754327 1100 bool "ARM errata: no automatic Store Buffer drain" 1101 depends on CPU_V7 && SMP 1102 help 1103 This option enables the workaround for the 754327 Cortex-A9 (prior to 1104 r2p0) erratum. The Store Buffer does not have any automatic draining 1105 mechanism and therefore a livelock may occur if an external agent 1106 continuously polls a memory location waiting to observe an update. 1107 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1108 written polling loops from denying visibility of updates to memory. 1109 1110config ARM_ERRATA_364296 1111 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1112 depends on CPU_V6 1113 help 1114 This options enables the workaround for the 364296 ARM1136 1115 r0p2 erratum (possible cache data corruption with 1116 hit-under-miss enabled). It sets the undocumented bit 31 in 1117 the auxiliary control register and the FI bit in the control 1118 register, thus disabling hit-under-miss without putting the 1119 processor into full low interrupt latency mode. ARM11MPCore 1120 is not affected. 1121 1122config ARM_ERRATA_764369 1123 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1124 depends on CPU_V7 && SMP 1125 help 1126 This option enables the workaround for erratum 764369 1127 affecting Cortex-A9 MPCore with two or more processors (all 1128 current revisions). Under certain timing circumstances, a data 1129 cache line maintenance operation by MVA targeting an Inner 1130 Shareable memory region may fail to proceed up to either the 1131 Point of Coherency or to the Point of Unification of the 1132 system. This workaround adds a DSB instruction before the 1133 relevant cache maintenance functions and sets a specific bit 1134 in the diagnostic control register of the SCU. 1135 1136config ARM_ERRATA_775420 1137 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1138 depends on CPU_V7 1139 help 1140 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1141 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1142 operation aborts with MMU exception, it might cause the processor 1143 to deadlock. This workaround puts DSB before executing ISB if 1144 an abort may occur on cache maintenance. 1145 1146config ARM_ERRATA_798181 1147 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1148 depends on CPU_V7 && SMP 1149 help 1150 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1151 adequately shooting down all use of the old entries. This 1152 option enables the Linux kernel workaround for this erratum 1153 which sends an IPI to the CPUs that are running the same ASID 1154 as the one being invalidated. 1155 1156config ARM_ERRATA_773022 1157 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1158 depends on CPU_V7 1159 help 1160 This option enables the workaround for the 773022 Cortex-A15 1161 (up to r0p4) erratum. In certain rare sequences of code, the 1162 loop buffer may deliver incorrect instructions. This 1163 workaround disables the loop buffer to avoid the erratum. 1164 1165config ARM_ERRATA_818325_852422 1166 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1167 depends on CPU_V7 1168 help 1169 This option enables the workaround for: 1170 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1171 instruction might deadlock. Fixed in r0p1. 1172 - Cortex-A12 852422: Execution of a sequence of instructions might 1173 lead to either a data corruption or a CPU deadlock. Not fixed in 1174 any Cortex-A12 cores yet. 1175 This workaround for all both errata involves setting bit[12] of the 1176 Feature Register. This bit disables an optimisation applied to a 1177 sequence of 2 instructions that use opposing condition codes. 1178 1179config ARM_ERRATA_821420 1180 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1181 depends on CPU_V7 1182 help 1183 This option enables the workaround for the 821420 Cortex-A12 1184 (all revs) erratum. In very rare timing conditions, a sequence 1185 of VMOV to Core registers instructions, for which the second 1186 one is in the shadow of a branch or abort, can lead to a 1187 deadlock when the VMOV instructions are issued out-of-order. 1188 1189config ARM_ERRATA_825619 1190 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1191 depends on CPU_V7 1192 help 1193 This option enables the workaround for the 825619 Cortex-A12 1194 (all revs) erratum. Within rare timing constraints, executing a 1195 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1196 and Device/Strongly-Ordered loads and stores might cause deadlock 1197 1198config ARM_ERRATA_852421 1199 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1200 depends on CPU_V7 1201 help 1202 This option enables the workaround for the 852421 Cortex-A17 1203 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1204 execution of a DMB ST instruction might fail to properly order 1205 stores from GroupA and stores from GroupB. 1206 1207config ARM_ERRATA_852423 1208 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1209 depends on CPU_V7 1210 help 1211 This option enables the workaround for: 1212 - Cortex-A17 852423: Execution of a sequence of instructions might 1213 lead to either a data corruption or a CPU deadlock. Not fixed in 1214 any Cortex-A17 cores yet. 1215 This is identical to Cortex-A12 erratum 852422. It is a separate 1216 config option from the A12 erratum due to the way errata are checked 1217 for and handled. 1218 1219endmenu 1220 1221source "arch/arm/common/Kconfig" 1222 1223menu "Bus support" 1224 1225config ISA 1226 bool 1227 help 1228 Find out whether you have ISA slots on your motherboard. ISA is the 1229 name of a bus system, i.e. the way the CPU talks to the other stuff 1230 inside your box. Other bus systems are PCI, EISA, MicroChannel 1231 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1232 newer boards don't support it. If you have ISA, say Y, otherwise N. 1233 1234# Select ISA DMA controller support 1235config ISA_DMA 1236 bool 1237 select ISA_DMA_API 1238 1239# Select ISA DMA interface 1240config ISA_DMA_API 1241 bool 1242 1243config PCI 1244 bool "PCI support" if MIGHT_HAVE_PCI 1245 help 1246 Find out whether you have a PCI motherboard. PCI is the name of a 1247 bus system, i.e. the way the CPU talks to the other stuff inside 1248 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1249 VESA. If you have PCI, say Y, otherwise N. 1250 1251config PCI_DOMAINS 1252 bool 1253 depends on PCI 1254 1255config PCI_DOMAINS_GENERIC 1256 def_bool PCI_DOMAINS 1257 1258config PCI_NANOENGINE 1259 bool "BSE nanoEngine PCI support" 1260 depends on SA1100_NANOENGINE 1261 help 1262 Enable PCI on the BSE nanoEngine board. 1263 1264config PCI_SYSCALL 1265 def_bool PCI 1266 1267config PCI_HOST_ITE8152 1268 bool 1269 depends on PCI && MACH_ARMCORE 1270 default y 1271 select DMABOUNCE 1272 1273source "drivers/pci/Kconfig" 1274 1275source "drivers/pcmcia/Kconfig" 1276 1277endmenu 1278 1279menu "Kernel Features" 1280 1281config HAVE_SMP 1282 bool 1283 help 1284 This option should be selected by machines which have an SMP- 1285 capable CPU. 1286 1287 The only effect of this option is to make the SMP-related 1288 options available to the user for configuration. 1289 1290config SMP 1291 bool "Symmetric Multi-Processing" 1292 depends on CPU_V6K || CPU_V7 1293 depends on GENERIC_CLOCKEVENTS 1294 depends on HAVE_SMP 1295 depends on MMU || ARM_MPU 1296 select IRQ_WORK 1297 help 1298 This enables support for systems with more than one CPU. If you have 1299 a system with only one CPU, say N. If you have a system with more 1300 than one CPU, say Y. 1301 1302 If you say N here, the kernel will run on uni- and multiprocessor 1303 machines, but will use only one CPU of a multiprocessor machine. If 1304 you say Y here, the kernel will run on many, but not all, 1305 uniprocessor machines. On a uniprocessor machine, the kernel 1306 will run faster if you say N here. 1307 1308 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1309 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at 1310 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1311 1312 If you don't know what to do here, say N. 1313 1314config SMP_ON_UP 1315 bool "Allow booting SMP kernel on uniprocessor systems" 1316 depends on SMP && !XIP_KERNEL && MMU 1317 default y 1318 help 1319 SMP kernels contain instructions which fail on non-SMP processors. 1320 Enabling this option allows the kernel to modify itself to make 1321 these instructions safe. Disabling it allows about 1K of space 1322 savings. 1323 1324 If you don't know what to do here, say Y. 1325 1326config ARM_CPU_TOPOLOGY 1327 bool "Support cpu topology definition" 1328 depends on SMP && CPU_V7 1329 default y 1330 help 1331 Support ARM cpu topology definition. The MPIDR register defines 1332 affinity between processors which is then used to describe the cpu 1333 topology of an ARM System. 1334 1335config SCHED_MC 1336 bool "Multi-core scheduler support" 1337 depends on ARM_CPU_TOPOLOGY 1338 help 1339 Multi-core scheduler support improves the CPU scheduler's decision 1340 making when dealing with multi-core CPU chips at a cost of slightly 1341 increased overhead in some places. If unsure say N here. 1342 1343config SCHED_SMT 1344 bool "SMT scheduler support" 1345 depends on ARM_CPU_TOPOLOGY 1346 help 1347 Improves the CPU scheduler's decision making when dealing with 1348 MultiThreading at a cost of slightly increased overhead in some 1349 places. If unsure say N here. 1350 1351config HAVE_ARM_SCU 1352 bool 1353 help 1354 This option enables support for the ARM system coherency unit 1355 1356config HAVE_ARM_ARCH_TIMER 1357 bool "Architected timer support" 1358 depends on CPU_V7 1359 select ARM_ARCH_TIMER 1360 select GENERIC_CLOCKEVENTS 1361 help 1362 This option enables support for the ARM architected timer 1363 1364config HAVE_ARM_TWD 1365 bool 1366 select TIMER_OF if OF 1367 help 1368 This options enables support for the ARM timer and watchdog unit 1369 1370config MCPM 1371 bool "Multi-Cluster Power Management" 1372 depends on CPU_V7 && SMP 1373 help 1374 This option provides the common power management infrastructure 1375 for (multi-)cluster based systems, such as big.LITTLE based 1376 systems. 1377 1378config MCPM_QUAD_CLUSTER 1379 bool 1380 depends on MCPM 1381 help 1382 To avoid wasting resources unnecessarily, MCPM only supports up 1383 to 2 clusters by default. 1384 Platforms with 3 or 4 clusters that use MCPM must select this 1385 option to allow the additional clusters to be managed. 1386 1387config BIG_LITTLE 1388 bool "big.LITTLE support (Experimental)" 1389 depends on CPU_V7 && SMP 1390 select MCPM 1391 help 1392 This option enables support selections for the big.LITTLE 1393 system architecture. 1394 1395config BL_SWITCHER 1396 bool "big.LITTLE switcher support" 1397 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1398 select CPU_PM 1399 help 1400 The big.LITTLE "switcher" provides the core functionality to 1401 transparently handle transition between a cluster of A15's 1402 and a cluster of A7's in a big.LITTLE system. 1403 1404config BL_SWITCHER_DUMMY_IF 1405 tristate "Simple big.LITTLE switcher user interface" 1406 depends on BL_SWITCHER && DEBUG_KERNEL 1407 help 1408 This is a simple and dummy char dev interface to control 1409 the big.LITTLE switcher core code. It is meant for 1410 debugging purposes only. 1411 1412choice 1413 prompt "Memory split" 1414 depends on MMU 1415 default VMSPLIT_3G 1416 help 1417 Select the desired split between kernel and user memory. 1418 1419 If you are not absolutely sure what you are doing, leave this 1420 option alone! 1421 1422 config VMSPLIT_3G 1423 bool "3G/1G user/kernel split" 1424 config VMSPLIT_3G_OPT 1425 depends on !ARM_LPAE 1426 bool "3G/1G user/kernel split (for full 1G low memory)" 1427 config VMSPLIT_2G 1428 bool "2G/2G user/kernel split" 1429 config VMSPLIT_1G 1430 bool "1G/3G user/kernel split" 1431endchoice 1432 1433config PAGE_OFFSET 1434 hex 1435 default PHYS_OFFSET if !MMU 1436 default 0x40000000 if VMSPLIT_1G 1437 default 0x80000000 if VMSPLIT_2G 1438 default 0xB0000000 if VMSPLIT_3G_OPT 1439 default 0xC0000000 1440 1441config NR_CPUS 1442 int "Maximum number of CPUs (2-32)" 1443 range 2 32 1444 depends on SMP 1445 default "4" 1446 1447config HOTPLUG_CPU 1448 bool "Support for hot-pluggable CPUs" 1449 depends on SMP 1450 help 1451 Say Y here to experiment with turning CPUs off and on. CPUs 1452 can be controlled through /sys/devices/system/cpu. 1453 1454config ARM_PSCI 1455 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1456 depends on HAVE_ARM_SMCCC 1457 select ARM_PSCI_FW 1458 help 1459 Say Y here if you want Linux to communicate with system firmware 1460 implementing the PSCI specification for CPU-centric power 1461 management operations described in ARM document number ARM DEN 1462 0022A ("Power State Coordination Interface System Software on 1463 ARM processors"). 1464 1465# The GPIO number here must be sorted by descending number. In case of 1466# a multiplatform kernel, we just want the highest value required by the 1467# selected platforms. 1468config ARCH_NR_GPIO 1469 int 1470 default 2048 if ARCH_SOCFPGA 1471 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \ 1472 ARCH_ZYNQ 1473 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1474 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1475 default 416 if ARCH_SUNXI 1476 default 392 if ARCH_U8500 1477 default 352 if ARCH_VT8500 1478 default 288 if ARCH_ROCKCHIP 1479 default 264 if MACH_H4700 1480 default 0 1481 help 1482 Maximum number of GPIOs in the system. 1483 1484 If unsure, leave the default value. 1485 1486source kernel/Kconfig.preempt 1487 1488config HZ_FIXED 1489 int 1490 default 200 if ARCH_EBSA110 1491 default 128 if SOC_AT91RM9200 1492 default 0 1493 1494choice 1495 depends on HZ_FIXED = 0 1496 prompt "Timer frequency" 1497 1498config HZ_100 1499 bool "100 Hz" 1500 1501config HZ_200 1502 bool "200 Hz" 1503 1504config HZ_250 1505 bool "250 Hz" 1506 1507config HZ_300 1508 bool "300 Hz" 1509 1510config HZ_500 1511 bool "500 Hz" 1512 1513config HZ_1000 1514 bool "1000 Hz" 1515 1516endchoice 1517 1518config HZ 1519 int 1520 default HZ_FIXED if HZ_FIXED != 0 1521 default 100 if HZ_100 1522 default 200 if HZ_200 1523 default 250 if HZ_250 1524 default 300 if HZ_300 1525 default 500 if HZ_500 1526 default 1000 1527 1528config SCHED_HRTICK 1529 def_bool HIGH_RES_TIMERS 1530 1531config THUMB2_KERNEL 1532 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1533 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1534 default y if CPU_THUMBONLY 1535 select ARM_ASM_UNIFIED 1536 select ARM_UNWIND 1537 help 1538 By enabling this option, the kernel will be compiled in 1539 Thumb-2 mode. A compiler/assembler that understand the unified 1540 ARM-Thumb syntax is needed. 1541 1542 If unsure, say N. 1543 1544config THUMB2_AVOID_R_ARM_THM_JUMP11 1545 bool "Work around buggy Thumb-2 short branch relocations in gas" 1546 depends on THUMB2_KERNEL && MODULES 1547 default y 1548 help 1549 Various binutils versions can resolve Thumb-2 branches to 1550 locally-defined, preemptible global symbols as short-range "b.n" 1551 branch instructions. 1552 1553 This is a problem, because there's no guarantee the final 1554 destination of the symbol, or any candidate locations for a 1555 trampoline, are within range of the branch. For this reason, the 1556 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1557 relocation in modules at all, and it makes little sense to add 1558 support. 1559 1560 The symptom is that the kernel fails with an "unsupported 1561 relocation" error when loading some modules. 1562 1563 Until fixed tools are available, passing 1564 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1565 code which hits this problem, at the cost of a bit of extra runtime 1566 stack usage in some cases. 1567 1568 The problem is described in more detail at: 1569 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1570 1571 Only Thumb-2 kernels are affected. 1572 1573 Unless you are sure your tools don't have this problem, say Y. 1574 1575config ARM_ASM_UNIFIED 1576 bool 1577 1578config ARM_PATCH_IDIV 1579 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1580 depends on CPU_32v7 && !XIP_KERNEL 1581 default y 1582 help 1583 The ARM compiler inserts calls to __aeabi_idiv() and 1584 __aeabi_uidiv() when it needs to perform division on signed 1585 and unsigned integers. Some v7 CPUs have support for the sdiv 1586 and udiv instructions that can be used to implement those 1587 functions. 1588 1589 Enabling this option allows the kernel to modify itself to 1590 replace the first two instructions of these library functions 1591 with the sdiv or udiv plus "bx lr" instructions when the CPU 1592 it is running on supports them. Typically this will be faster 1593 and less power intensive than running the original library 1594 code to do integer division. 1595 1596config AEABI 1597 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1598 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1599 help 1600 This option allows for the kernel to be compiled using the latest 1601 ARM ABI (aka EABI). This is only useful if you are using a user 1602 space environment that is also compiled with EABI. 1603 1604 Since there are major incompatibilities between the legacy ABI and 1605 EABI, especially with regard to structure member alignment, this 1606 option also changes the kernel syscall calling convention to 1607 disambiguate both ABIs and allow for backward compatibility support 1608 (selected with CONFIG_OABI_COMPAT). 1609 1610 To use this you need GCC version 4.0.0 or later. 1611 1612config OABI_COMPAT 1613 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1614 depends on AEABI && !THUMB2_KERNEL 1615 help 1616 This option preserves the old syscall interface along with the 1617 new (ARM EABI) one. It also provides a compatibility layer to 1618 intercept syscalls that have structure arguments which layout 1619 in memory differs between the legacy ABI and the new ARM EABI 1620 (only for non "thumb" binaries). This option adds a tiny 1621 overhead to all syscalls and produces a slightly larger kernel. 1622 1623 The seccomp filter system will not be available when this is 1624 selected, since there is no way yet to sensibly distinguish 1625 between calling conventions during filtering. 1626 1627 If you know you'll be using only pure EABI user space then you 1628 can say N here. If this option is not selected and you attempt 1629 to execute a legacy ABI binary then the result will be 1630 UNPREDICTABLE (in fact it can be predicted that it won't work 1631 at all). If in doubt say N. 1632 1633config ARCH_HAS_HOLES_MEMORYMODEL 1634 bool 1635 1636config ARCH_SPARSEMEM_ENABLE 1637 bool 1638 1639config ARCH_SPARSEMEM_DEFAULT 1640 def_bool ARCH_SPARSEMEM_ENABLE 1641 1642config ARCH_SELECT_MEMORY_MODEL 1643 def_bool ARCH_SPARSEMEM_ENABLE 1644 1645config HAVE_ARCH_PFN_VALID 1646 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1647 1648config HAVE_GENERIC_GUP 1649 def_bool y 1650 depends on ARM_LPAE 1651 1652config HIGHMEM 1653 bool "High Memory Support" 1654 depends on MMU 1655 help 1656 The address space of ARM processors is only 4 Gigabytes large 1657 and it has to accommodate user address space, kernel address 1658 space as well as some memory mapped IO. That means that, if you 1659 have a large amount of physical memory and/or IO, not all of the 1660 memory can be "permanently mapped" by the kernel. The physical 1661 memory that is not permanently mapped is called "high memory". 1662 1663 Depending on the selected kernel/user memory split, minimum 1664 vmalloc space and actual amount of RAM, you may not need this 1665 option which should result in a slightly faster kernel. 1666 1667 If unsure, say n. 1668 1669config HIGHPTE 1670 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1671 depends on HIGHMEM 1672 default y 1673 help 1674 The VM uses one page of physical memory for each page table. 1675 For systems with a lot of processes, this can use a lot of 1676 precious low memory, eventually leading to low memory being 1677 consumed by page tables. Setting this option will allow 1678 user-space 2nd level page tables to reside in high memory. 1679 1680config CPU_SW_DOMAIN_PAN 1681 bool "Enable use of CPU domains to implement privileged no-access" 1682 depends on MMU && !ARM_LPAE 1683 default y 1684 help 1685 Increase kernel security by ensuring that normal kernel accesses 1686 are unable to access userspace addresses. This can help prevent 1687 use-after-free bugs becoming an exploitable privilege escalation 1688 by ensuring that magic values (such as LIST_POISON) will always 1689 fault when dereferenced. 1690 1691 CPUs with low-vector mappings use a best-efforts implementation. 1692 Their lower 1MB needs to remain accessible for the vectors, but 1693 the remainder of userspace will become appropriately inaccessible. 1694 1695config HW_PERF_EVENTS 1696 def_bool y 1697 depends on ARM_PMU 1698 1699config SYS_SUPPORTS_HUGETLBFS 1700 def_bool y 1701 depends on ARM_LPAE 1702 1703config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1704 def_bool y 1705 depends on ARM_LPAE 1706 1707config ARCH_WANT_GENERAL_HUGETLB 1708 def_bool y 1709 1710config ARM_MODULE_PLTS 1711 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1712 depends on MODULES 1713 help 1714 Allocate PLTs when loading modules so that jumps and calls whose 1715 targets are too far away for their relative offsets to be encoded 1716 in the instructions themselves can be bounced via veneers in the 1717 module's PLT. This allows modules to be allocated in the generic 1718 vmalloc area after the dedicated module memory area has been 1719 exhausted. The modules will use slightly more memory, but after 1720 rounding up to page size, the actual memory footprint is usually 1721 the same. 1722 1723 Say y if you are getting out of memory errors while loading modules 1724 1725source "mm/Kconfig" 1726 1727config FORCE_MAX_ZONEORDER 1728 int "Maximum zone order" 1729 default "12" if SOC_AM33XX 1730 default "9" if SA1111 || ARCH_EFM32 1731 default "11" 1732 help 1733 The kernel memory allocator divides physically contiguous memory 1734 blocks into "zones", where each zone is a power of two number of 1735 pages. This option selects the largest power of two that the kernel 1736 keeps in the memory allocator. If you need to allocate very large 1737 blocks of physically contiguous memory, then you may need to 1738 increase this value. 1739 1740 This config option is actually maximum order plus one. For example, 1741 a value of 11 means that the largest free memory block is 2^10 pages. 1742 1743config ALIGNMENT_TRAP 1744 bool 1745 depends on CPU_CP15_MMU 1746 default y if !ARCH_EBSA110 1747 select HAVE_PROC_CPU if PROC_FS 1748 help 1749 ARM processors cannot fetch/store information which is not 1750 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1751 address divisible by 4. On 32-bit ARM processors, these non-aligned 1752 fetch/store instructions will be emulated in software if you say 1753 here, which has a severe performance impact. This is necessary for 1754 correct operation of some network protocols. With an IP-only 1755 configuration it is safe to say N, otherwise say Y. 1756 1757config UACCESS_WITH_MEMCPY 1758 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1759 depends on MMU 1760 default y if CPU_FEROCEON 1761 help 1762 Implement faster copy_to_user and clear_user methods for CPU 1763 cores where a 8-word STM instruction give significantly higher 1764 memory write throughput than a sequence of individual 32bit stores. 1765 1766 A possible side effect is a slight increase in scheduling latency 1767 between threads sharing the same address space if they invoke 1768 such copy operations with large buffers. 1769 1770 However, if the CPU data cache is using a write-allocate mode, 1771 this option is unlikely to provide any performance gain. 1772 1773config SECCOMP 1774 bool 1775 prompt "Enable seccomp to safely compute untrusted bytecode" 1776 ---help--- 1777 This kernel feature is useful for number crunching applications 1778 that may need to compute untrusted bytecode during their 1779 execution. By using pipes or other transports made available to 1780 the process as file descriptors supporting the read/write 1781 syscalls, it's possible to isolate those applications in 1782 their own address space using seccomp. Once seccomp is 1783 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1784 and the task is only allowed to execute a few safe syscalls 1785 defined by each seccomp mode. 1786 1787config SWIOTLB 1788 def_bool y 1789 1790config IOMMU_HELPER 1791 def_bool SWIOTLB 1792 1793config PARAVIRT 1794 bool "Enable paravirtualization code" 1795 help 1796 This changes the kernel so it can modify itself when it is run 1797 under a hypervisor, potentially improving performance significantly 1798 over full virtualization. 1799 1800config PARAVIRT_TIME_ACCOUNTING 1801 bool "Paravirtual steal time accounting" 1802 select PARAVIRT 1803 default n 1804 help 1805 Select this option to enable fine granularity task steal time 1806 accounting. Time spent executing other tasks in parallel with 1807 the current vCPU is discounted from the vCPU power. To account for 1808 that, there can be a small performance impact. 1809 1810 If in doubt, say N here. 1811 1812config XEN_DOM0 1813 def_bool y 1814 depends on XEN 1815 1816config XEN 1817 bool "Xen guest support on ARM" 1818 depends on ARM && AEABI && OF 1819 depends on CPU_V7 && !CPU_V6 1820 depends on !GENERIC_ATOMIC64 1821 depends on MMU 1822 select ARCH_DMA_ADDR_T_64BIT 1823 select ARM_PSCI 1824 select SWIOTLB_XEN 1825 select PARAVIRT 1826 help 1827 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1828 1829endmenu 1830 1831menu "Boot options" 1832 1833config USE_OF 1834 bool "Flattened Device Tree support" 1835 select IRQ_DOMAIN 1836 select OF 1837 help 1838 Include support for flattened device tree machine descriptions. 1839 1840config ATAGS 1841 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1842 default y 1843 help 1844 This is the traditional way of passing data to the kernel at boot 1845 time. If you are solely relying on the flattened device tree (or 1846 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1847 to remove ATAGS support from your kernel binary. If unsure, 1848 leave this to y. 1849 1850config DEPRECATED_PARAM_STRUCT 1851 bool "Provide old way to pass kernel parameters" 1852 depends on ATAGS 1853 help 1854 This was deprecated in 2001 and announced to live on for 5 years. 1855 Some old boot loaders still use this way. 1856 1857# Compressed boot loader in ROM. Yes, we really want to ask about 1858# TEXT and BSS so we preserve their values in the config files. 1859config ZBOOT_ROM_TEXT 1860 hex "Compressed ROM boot loader base address" 1861 default "0" 1862 help 1863 The physical address at which the ROM-able zImage is to be 1864 placed in the target. Platforms which normally make use of 1865 ROM-able zImage formats normally set this to a suitable 1866 value in their defconfig file. 1867 1868 If ZBOOT_ROM is not enabled, this has no effect. 1869 1870config ZBOOT_ROM_BSS 1871 hex "Compressed ROM boot loader BSS address" 1872 default "0" 1873 help 1874 The base address of an area of read/write memory in the target 1875 for the ROM-able zImage which must be available while the 1876 decompressor is running. It must be large enough to hold the 1877 entire decompressed kernel plus an additional 128 KiB. 1878 Platforms which normally make use of ROM-able zImage formats 1879 normally set this to a suitable value in their defconfig file. 1880 1881 If ZBOOT_ROM is not enabled, this has no effect. 1882 1883config ZBOOT_ROM 1884 bool "Compressed boot loader in ROM/flash" 1885 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1886 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1887 help 1888 Say Y here if you intend to execute your compressed kernel image 1889 (zImage) directly from ROM or flash. If unsure, say N. 1890 1891config ARM_APPENDED_DTB 1892 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1893 depends on OF 1894 help 1895 With this option, the boot code will look for a device tree binary 1896 (DTB) appended to zImage 1897 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1898 1899 This is meant as a backward compatibility convenience for those 1900 systems with a bootloader that can't be upgraded to accommodate 1901 the documented boot protocol using a device tree. 1902 1903 Beware that there is very little in terms of protection against 1904 this option being confused by leftover garbage in memory that might 1905 look like a DTB header after a reboot if no actual DTB is appended 1906 to zImage. Do not leave this option active in a production kernel 1907 if you don't intend to always append a DTB. Proper passing of the 1908 location into r2 of a bootloader provided DTB is always preferable 1909 to this option. 1910 1911config ARM_ATAG_DTB_COMPAT 1912 bool "Supplement the appended DTB with traditional ATAG information" 1913 depends on ARM_APPENDED_DTB 1914 help 1915 Some old bootloaders can't be updated to a DTB capable one, yet 1916 they provide ATAGs with memory configuration, the ramdisk address, 1917 the kernel cmdline string, etc. Such information is dynamically 1918 provided by the bootloader and can't always be stored in a static 1919 DTB. To allow a device tree enabled kernel to be used with such 1920 bootloaders, this option allows zImage to extract the information 1921 from the ATAG list and store it at run time into the appended DTB. 1922 1923choice 1924 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1925 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1926 1927config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1928 bool "Use bootloader kernel arguments if available" 1929 help 1930 Uses the command-line options passed by the boot loader instead of 1931 the device tree bootargs property. If the boot loader doesn't provide 1932 any, the device tree bootargs property will be used. 1933 1934config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1935 bool "Extend with bootloader kernel arguments" 1936 help 1937 The command-line arguments provided by the boot loader will be 1938 appended to the the device tree bootargs property. 1939 1940endchoice 1941 1942config CMDLINE 1943 string "Default kernel command string" 1944 default "" 1945 help 1946 On some architectures (EBSA110 and CATS), there is currently no way 1947 for the boot loader to pass arguments to the kernel. For these 1948 architectures, you should supply some command-line options at build 1949 time by entering them here. As a minimum, you should specify the 1950 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1951 1952choice 1953 prompt "Kernel command line type" if CMDLINE != "" 1954 default CMDLINE_FROM_BOOTLOADER 1955 depends on ATAGS 1956 1957config CMDLINE_FROM_BOOTLOADER 1958 bool "Use bootloader kernel arguments if available" 1959 help 1960 Uses the command-line options passed by the boot loader. If 1961 the boot loader doesn't provide any, the default kernel command 1962 string provided in CMDLINE will be used. 1963 1964config CMDLINE_EXTEND 1965 bool "Extend bootloader kernel arguments" 1966 help 1967 The command-line arguments provided by the boot loader will be 1968 appended to the default kernel command string. 1969 1970config CMDLINE_FORCE 1971 bool "Always use the default kernel command string" 1972 help 1973 Always use the default kernel command string, even if the boot 1974 loader passes other arguments to the kernel. 1975 This is useful if you cannot or don't want to change the 1976 command-line options your boot loader passes to the kernel. 1977endchoice 1978 1979config XIP_KERNEL 1980 bool "Kernel Execute-In-Place from ROM" 1981 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1982 help 1983 Execute-In-Place allows the kernel to run from non-volatile storage 1984 directly addressable by the CPU, such as NOR flash. This saves RAM 1985 space since the text section of the kernel is not loaded from flash 1986 to RAM. Read-write sections, such as the data section and stack, 1987 are still copied to RAM. The XIP kernel is not compressed since 1988 it has to run directly from flash, so it will take more space to 1989 store it. The flash address used to link the kernel object files, 1990 and for storing it, is configuration dependent. Therefore, if you 1991 say Y here, you must know the proper physical address where to 1992 store the kernel image depending on your own flash memory usage. 1993 1994 Also note that the make target becomes "make xipImage" rather than 1995 "make zImage" or "make Image". The final kernel binary to put in 1996 ROM memory will be arch/arm/boot/xipImage. 1997 1998 If unsure, say N. 1999 2000config XIP_PHYS_ADDR 2001 hex "XIP Kernel Physical Location" 2002 depends on XIP_KERNEL 2003 default "0x00080000" 2004 help 2005 This is the physical address in your flash memory the kernel will 2006 be linked for and stored to. This address is dependent on your 2007 own flash usage. 2008 2009config KEXEC 2010 bool "Kexec system call (EXPERIMENTAL)" 2011 depends on (!SMP || PM_SLEEP_SMP) 2012 depends on !CPU_V7M 2013 select KEXEC_CORE 2014 help 2015 kexec is a system call that implements the ability to shutdown your 2016 current kernel, and to start another kernel. It is like a reboot 2017 but it is independent of the system firmware. And like a reboot 2018 you can start any kernel with it, not just Linux. 2019 2020 It is an ongoing process to be certain the hardware in a machine 2021 is properly shutdown, so do not be surprised if this code does not 2022 initially work for you. 2023 2024config ATAGS_PROC 2025 bool "Export atags in procfs" 2026 depends on ATAGS && KEXEC 2027 default y 2028 help 2029 Should the atags used to boot the kernel be exported in an "atags" 2030 file in procfs. Useful with kexec. 2031 2032config CRASH_DUMP 2033 bool "Build kdump crash kernel (EXPERIMENTAL)" 2034 help 2035 Generate crash dump after being started by kexec. This should 2036 be normally only set in special crash dump kernels which are 2037 loaded in the main kernel with kexec-tools into a specially 2038 reserved region and then later executed after a crash by 2039 kdump/kexec. The crash dump kernel must be compiled to a 2040 memory address not used by the main kernel 2041 2042 For more details see Documentation/kdump/kdump.txt 2043 2044config AUTO_ZRELADDR 2045 bool "Auto calculation of the decompressed kernel image address" 2046 help 2047 ZRELADDR is the physical address where the decompressed kernel 2048 image will be placed. If AUTO_ZRELADDR is selected, the address 2049 will be determined at run-time by masking the current IP with 2050 0xf8000000. This assumes the zImage being placed in the first 128MB 2051 from start of memory. 2052 2053config EFI_STUB 2054 bool 2055 2056config EFI 2057 bool "UEFI runtime support" 2058 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2059 select UCS2_STRING 2060 select EFI_PARAMS_FROM_FDT 2061 select EFI_STUB 2062 select EFI_ARMSTUB 2063 select EFI_RUNTIME_WRAPPERS 2064 ---help--- 2065 This option provides support for runtime services provided 2066 by UEFI firmware (such as non-volatile variables, realtime 2067 clock, and platform reset). A UEFI stub is also provided to 2068 allow the kernel to be booted as an EFI application. This 2069 is only useful for kernels that may run on systems that have 2070 UEFI firmware. 2071 2072config DMI 2073 bool "Enable support for SMBIOS (DMI) tables" 2074 depends on EFI 2075 default y 2076 help 2077 This enables SMBIOS/DMI feature for systems. 2078 2079 This option is only useful on systems that have UEFI firmware. 2080 However, even with this option, the resultant kernel should 2081 continue to boot on existing non-UEFI platforms. 2082 2083 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2084 i.e., the the practice of identifying the platform via DMI to 2085 decide whether certain workarounds for buggy hardware and/or 2086 firmware need to be enabled. This would require the DMI subsystem 2087 to be enabled much earlier than we do on ARM, which is non-trivial. 2088 2089endmenu 2090 2091menu "CPU Power Management" 2092 2093source "drivers/cpufreq/Kconfig" 2094 2095source "drivers/cpuidle/Kconfig" 2096 2097endmenu 2098 2099menu "Floating point emulation" 2100 2101comment "At least one emulation must be selected" 2102 2103config FPE_NWFPE 2104 bool "NWFPE math emulation" 2105 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2106 ---help--- 2107 Say Y to include the NWFPE floating point emulator in the kernel. 2108 This is necessary to run most binaries. Linux does not currently 2109 support floating point hardware so you need to say Y here even if 2110 your machine has an FPA or floating point co-processor podule. 2111 2112 You may say N here if you are going to load the Acorn FPEmulator 2113 early in the bootup. 2114 2115config FPE_NWFPE_XP 2116 bool "Support extended precision" 2117 depends on FPE_NWFPE 2118 help 2119 Say Y to include 80-bit support in the kernel floating-point 2120 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2121 Note that gcc does not generate 80-bit operations by default, 2122 so in most cases this option only enlarges the size of the 2123 floating point emulator without any good reason. 2124 2125 You almost surely want to say N here. 2126 2127config FPE_FASTFPE 2128 bool "FastFPE math emulation (EXPERIMENTAL)" 2129 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2130 ---help--- 2131 Say Y here to include the FAST floating point emulator in the kernel. 2132 This is an experimental much faster emulator which now also has full 2133 precision for the mantissa. It does not support any exceptions. 2134 It is very simple, and approximately 3-6 times faster than NWFPE. 2135 2136 It should be sufficient for most programs. It may be not suitable 2137 for scientific calculations, but you have to check this for yourself. 2138 If you do not feel you need a faster FP emulation you should better 2139 choose NWFPE. 2140 2141config VFP 2142 bool "VFP-format floating point maths" 2143 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2144 help 2145 Say Y to include VFP support code in the kernel. This is needed 2146 if your hardware includes a VFP unit. 2147 2148 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2149 release notes and additional status information. 2150 2151 Say N if your target does not have VFP hardware. 2152 2153config VFPv3 2154 bool 2155 depends on VFP 2156 default y if CPU_V7 2157 2158config NEON 2159 bool "Advanced SIMD (NEON) Extension support" 2160 depends on VFPv3 && CPU_V7 2161 help 2162 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2163 Extension. 2164 2165config KERNEL_MODE_NEON 2166 bool "Support for NEON in kernel mode" 2167 depends on NEON && AEABI 2168 help 2169 Say Y to include support for NEON in kernel mode. 2170 2171endmenu 2172 2173menu "Userspace binary formats" 2174 2175source "fs/Kconfig.binfmt" 2176 2177endmenu 2178 2179menu "Power management options" 2180 2181source "kernel/power/Kconfig" 2182 2183config ARCH_SUSPEND_POSSIBLE 2184 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2185 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2186 def_bool y 2187 2188config ARM_CPU_SUSPEND 2189 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2190 depends on ARCH_SUSPEND_POSSIBLE 2191 2192config ARCH_HIBERNATION_POSSIBLE 2193 bool 2194 depends on MMU 2195 default y if ARCH_SUSPEND_POSSIBLE 2196 2197endmenu 2198 2199source "net/Kconfig" 2200 2201source "drivers/Kconfig" 2202 2203source "drivers/firmware/Kconfig" 2204 2205source "fs/Kconfig" 2206 2207source "arch/arm/Kconfig.debug" 2208 2209source "security/Kconfig" 2210 2211source "crypto/Kconfig" 2212if CRYPTO 2213source "arch/arm/crypto/Kconfig" 2214endif 2215 2216source "lib/Kconfig" 2217 2218source "arch/arm/kvm/Kconfig" 2219