1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 25 select ARCH_HAVE_CUSTOM_GPIO_H 26 select ARCH_HAS_GCOV_PROFILE_ALL 27 select ARCH_KEEP_MEMBLOCK 28 select ARCH_MIGHT_HAVE_PC_PARPORT 29 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 30 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 31 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 32 select ARCH_SUPPORTS_ATOMIC_RMW 33 select ARCH_USE_BUILTIN_BSWAP 34 select ARCH_USE_CMPXCHG_LOCKREF 35 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 36 select ARCH_WANT_IPC_PARSE_VERSION 37 select ARCH_WANT_LD_ORPHAN_WARN 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_OPS 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_IRQ_IPI if SMP 53 select GENERIC_CPU_AUTOPROBE 54 select GENERIC_EARLY_IOREMAP 55 select GENERIC_IDLE_POLL_SETUP 56 select GENERIC_IRQ_PROBE 57 select GENERIC_IRQ_SHOW 58 select GENERIC_IRQ_SHOW_LEVEL 59 select GENERIC_LIB_DEVMEM_IS_ALLOWED 60 select GENERIC_PCI_IOMAP 61 select GENERIC_SCHED_CLOCK 62 select GENERIC_SMP_IDLE_THREAD 63 select GENERIC_STRNCPY_FROM_USER 64 select GENERIC_STRNLEN_USER 65 select HANDLE_DOMAIN_IRQ 66 select HARDIRQS_SW_RESEND 67 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 68 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 69 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 71 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 72 select HAVE_ARCH_MMAP_RND_BITS if MMU 73 select HAVE_ARCH_PFN_VALID 74 select HAVE_ARCH_SECCOMP 75 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 76 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 77 select HAVE_ARCH_TRACEHOOK 78 select HAVE_ARM_SMCCC if CPU_V7 79 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 80 select HAVE_CONTEXT_TRACKING 81 select HAVE_C_RECORDMCOUNT 82 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 83 select HAVE_DMA_CONTIGUOUS if MMU 84 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 85 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 86 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 87 select HAVE_EXIT_THREAD 88 select HAVE_FAST_GUP if ARM_LPAE 89 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 90 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 91 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 92 select HAVE_GCC_PLUGINS 93 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 94 select HAVE_IDE if PCI || ISA || PCMCIA 95 select HAVE_IRQ_TIME_ACCOUNTING 96 select HAVE_KERNEL_GZIP 97 select HAVE_KERNEL_LZ4 98 select HAVE_KERNEL_LZMA 99 select HAVE_KERNEL_LZO 100 select HAVE_KERNEL_XZ 101 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 102 select HAVE_KRETPROBES if HAVE_KPROBES 103 select HAVE_MOD_ARCH_SPECIFIC 104 select HAVE_NMI 105 select HAVE_OPTPROBES if !THUMB2_KERNEL 106 select HAVE_PERF_EVENTS 107 select HAVE_PERF_REGS 108 select HAVE_PERF_USER_STACK_DUMP 109 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 110 select HAVE_REGS_AND_STACK_ACCESS_API 111 select HAVE_RSEQ 112 select HAVE_STACKPROTECTOR 113 select HAVE_SYSCALL_TRACEPOINTS 114 select HAVE_UID16 115 select HAVE_VIRT_CPU_ACCOUNTING_GEN 116 select IRQ_FORCED_THREADING 117 select MODULES_USE_ELF_REL 118 select NEED_DMA_MAP_STATE 119 select OF_EARLY_FLATTREE if OF 120 select OLD_SIGACTION 121 select OLD_SIGSUSPEND3 122 select PCI_SYSCALL if PCI 123 select PERF_USE_VMALLOC 124 select RTC_LIB 125 select SET_FS 126 select SYS_SUPPORTS_APM_EMULATION 127 # Above selects are sorted alphabetically; please add new ones 128 # according to that. Thanks. 129 help 130 The ARM series is a line of low-power-consumption RISC chip designs 131 licensed by ARM Ltd and targeted at embedded applications and 132 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 133 manufactured, but legacy ARM-based PC hardware remains popular in 134 Europe. There is an ARM Linux project with a web page at 135 <http://www.arm.linux.org.uk/>. 136 137config ARM_HAS_SG_CHAIN 138 bool 139 140config ARM_DMA_USE_IOMMU 141 bool 142 select ARM_HAS_SG_CHAIN 143 select NEED_SG_DMA_LENGTH 144 145if ARM_DMA_USE_IOMMU 146 147config ARM_DMA_IOMMU_ALIGNMENT 148 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 149 range 4 9 150 default 8 151 help 152 DMA mapping framework by default aligns all buffers to the smallest 153 PAGE_SIZE order which is greater than or equal to the requested buffer 154 size. This works well for buffers up to a few hundreds kilobytes, but 155 for larger buffers it just a waste of address space. Drivers which has 156 relatively small addressing window (like 64Mib) might run out of 157 virtual space with just a few allocations. 158 159 With this parameter you can specify the maximum PAGE_SIZE order for 160 DMA IOMMU buffers. Larger buffers will be aligned only to this 161 specified order. The order is expressed as a power of two multiplied 162 by the PAGE_SIZE. 163 164endif 165 166config SYS_SUPPORTS_APM_EMULATION 167 bool 168 169config HAVE_TCM 170 bool 171 select GENERIC_ALLOCATOR 172 173config HAVE_PROC_CPU 174 bool 175 176config NO_IOPORT_MAP 177 bool 178 179config SBUS 180 bool 181 182config STACKTRACE_SUPPORT 183 bool 184 default y 185 186config LOCKDEP_SUPPORT 187 bool 188 default y 189 190config TRACE_IRQFLAGS_SUPPORT 191 bool 192 default !CPU_V7M 193 194config ARCH_HAS_ILOG2_U32 195 bool 196 197config ARCH_HAS_ILOG2_U64 198 bool 199 200config ARCH_HAS_BANDGAP 201 bool 202 203config FIX_EARLYCON_MEM 204 def_bool y if MMU 205 206config GENERIC_HWEIGHT 207 bool 208 default y 209 210config GENERIC_CALIBRATE_DELAY 211 bool 212 default y 213 214config ARCH_MAY_HAVE_PC_FDC 215 bool 216 217config ZONE_DMA 218 bool 219 220config ARCH_SUPPORTS_UPROBES 221 def_bool y 222 223config ARCH_HAS_DMA_SET_COHERENT_MASK 224 bool 225 226config GENERIC_ISA_DMA 227 bool 228 229config FIQ 230 bool 231 232config NEED_RET_TO_USER 233 bool 234 235config ARCH_MTD_XIP 236 bool 237 238config ARM_PATCH_PHYS_VIRT 239 bool "Patch physical to virtual translations at runtime" if EMBEDDED 240 default y 241 depends on !XIP_KERNEL && MMU 242 help 243 Patch phys-to-virt and virt-to-phys translation functions at 244 boot and module load time according to the position of the 245 kernel in system memory. 246 247 This can only be used with non-XIP MMU kernels where the base 248 of physical memory is at a 2 MiB boundary. 249 250 Only disable this option if you know that you do not require 251 this feature (eg, building a kernel for a single machine) and 252 you need to shrink the kernel to the minimal size. 253 254config NEED_MACH_IO_H 255 bool 256 help 257 Select this when mach/io.h is required to provide special 258 definitions for this platform. The need for mach/io.h should 259 be avoided when possible. 260 261config NEED_MACH_MEMORY_H 262 bool 263 help 264 Select this when mach/memory.h is required to provide special 265 definitions for this platform. The need for mach/memory.h should 266 be avoided when possible. 267 268config PHYS_OFFSET 269 hex "Physical address of main memory" if MMU 270 depends on !ARM_PATCH_PHYS_VIRT 271 default DRAM_BASE if !MMU 272 default 0x00000000 if ARCH_FOOTBRIDGE 273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 274 default 0x20000000 if ARCH_S5PV210 275 default 0xc0000000 if ARCH_SA1100 276 help 277 Please provide the physical address corresponding to the 278 location of main memory in your system. 279 280config GENERIC_BUG 281 def_bool y 282 depends on BUG 283 284config PGTABLE_LEVELS 285 int 286 default 3 if ARM_LPAE 287 default 2 288 289menu "System Type" 290 291config MMU 292 bool "MMU-based Paged Memory Management Support" 293 default y 294 help 295 Select if you want MMU-based virtualised addressing space 296 support by paged memory management. If unsure, say 'Y'. 297 298config ARCH_MMAP_RND_BITS_MIN 299 default 8 300 301config ARCH_MMAP_RND_BITS_MAX 302 default 14 if PAGE_OFFSET=0x40000000 303 default 15 if PAGE_OFFSET=0x80000000 304 default 16 305 306# 307# The "ARM system type" choice list is ordered alphabetically by option 308# text. Please add new entries in the option alphabetic order. 309# 310choice 311 prompt "ARM system type" 312 default ARM_SINGLE_ARMV7M if !MMU 313 default ARCH_MULTIPLATFORM if MMU 314 315config ARCH_MULTIPLATFORM 316 bool "Allow multiple platforms to be selected" 317 depends on MMU 318 select ARCH_FLATMEM_ENABLE 319 select ARCH_SPARSEMEM_ENABLE 320 select ARCH_SELECT_MEMORY_MODEL 321 select ARM_HAS_SG_CHAIN 322 select ARM_PATCH_PHYS_VIRT 323 select AUTO_ZRELADDR 324 select TIMER_OF 325 select COMMON_CLK 326 select GENERIC_IRQ_MULTI_HANDLER 327 select HAVE_PCI 328 select PCI_DOMAINS_GENERIC if PCI 329 select SPARSE_IRQ 330 select USE_OF 331 332config ARM_SINGLE_ARMV7M 333 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 334 depends on !MMU 335 select ARM_NVIC 336 select AUTO_ZRELADDR 337 select TIMER_OF 338 select COMMON_CLK 339 select CPU_V7M 340 select NO_IOPORT_MAP 341 select SPARSE_IRQ 342 select USE_OF 343 344config ARCH_EP93XX 345 bool "EP93xx-based" 346 select ARCH_SPARSEMEM_ENABLE 347 select ARM_AMBA 348 imply ARM_PATCH_PHYS_VIRT 349 select ARM_VIC 350 select AUTO_ZRELADDR 351 select CLKDEV_LOOKUP 352 select CLKSRC_MMIO 353 select CPU_ARM920T 354 select GPIOLIB 355 select HAVE_LEGACY_CLK 356 help 357 This enables support for the Cirrus EP93xx series of CPUs. 358 359config ARCH_FOOTBRIDGE 360 bool "FootBridge" 361 select CPU_SA110 362 select FOOTBRIDGE 363 select HAVE_IDE 364 select NEED_MACH_IO_H if !MMU 365 select NEED_MACH_MEMORY_H 366 help 367 Support for systems based on the DC21285 companion chip 368 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 369 370config ARCH_IOP32X 371 bool "IOP32x-based" 372 depends on MMU 373 select CPU_XSCALE 374 select GPIO_IOP 375 select GPIOLIB 376 select NEED_RET_TO_USER 377 select FORCE_PCI 378 select PLAT_IOP 379 help 380 Support for Intel's 80219 and IOP32X (XScale) family of 381 processors. 382 383config ARCH_IXP4XX 384 bool "IXP4xx-based" 385 depends on MMU 386 select ARCH_HAS_DMA_SET_COHERENT_MASK 387 select ARCH_SUPPORTS_BIG_ENDIAN 388 select CPU_XSCALE 389 select DMABOUNCE if PCI 390 select GENERIC_IRQ_MULTI_HANDLER 391 select GPIO_IXP4XX 392 select GPIOLIB 393 select HAVE_PCI 394 select IXP4XX_IRQ 395 select IXP4XX_TIMER 396 select NEED_MACH_IO_H 397 select USB_EHCI_BIG_ENDIAN_DESC 398 select USB_EHCI_BIG_ENDIAN_MMIO 399 help 400 Support for Intel's IXP4XX (XScale) family of processors. 401 402config ARCH_DOVE 403 bool "Marvell Dove" 404 select CPU_PJ4 405 select GENERIC_IRQ_MULTI_HANDLER 406 select GPIOLIB 407 select HAVE_PCI 408 select MVEBU_MBUS 409 select PINCTRL 410 select PINCTRL_DOVE 411 select PLAT_ORION_LEGACY 412 select SPARSE_IRQ 413 select PM_GENERIC_DOMAINS if PM 414 help 415 Support for the Marvell Dove SoC 88AP510 416 417config ARCH_PXA 418 bool "PXA2xx/PXA3xx-based" 419 depends on MMU 420 select ARCH_MTD_XIP 421 select ARM_CPU_SUSPEND if PM 422 select AUTO_ZRELADDR 423 select COMMON_CLK 424 select CLKSRC_PXA 425 select CLKSRC_MMIO 426 select TIMER_OF 427 select CPU_XSCALE if !CPU_XSC3 428 select GENERIC_IRQ_MULTI_HANDLER 429 select GPIO_PXA 430 select GPIOLIB 431 select HAVE_IDE 432 select IRQ_DOMAIN 433 select PLAT_PXA 434 select SPARSE_IRQ 435 help 436 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 437 438config ARCH_RPC 439 bool "RiscPC" 440 depends on MMU 441 select ARCH_ACORN 442 select ARCH_MAY_HAVE_PC_FDC 443 select ARCH_SPARSEMEM_ENABLE 444 select ARM_HAS_SG_CHAIN 445 select CPU_SA110 446 select FIQ 447 select HAVE_IDE 448 select HAVE_PATA_PLATFORM 449 select ISA_DMA_API 450 select LEGACY_TIMER_TICK 451 select NEED_MACH_IO_H 452 select NEED_MACH_MEMORY_H 453 select NO_IOPORT_MAP 454 help 455 On the Acorn Risc-PC, Linux can support the internal IDE disk and 456 CD-ROM interface, serial and parallel port, and the floppy drive. 457 458config ARCH_SA1100 459 bool "SA1100-based" 460 select ARCH_MTD_XIP 461 select ARCH_SPARSEMEM_ENABLE 462 select CLKSRC_MMIO 463 select CLKSRC_PXA 464 select TIMER_OF if OF 465 select COMMON_CLK 466 select CPU_FREQ 467 select CPU_SA1100 468 select GENERIC_IRQ_MULTI_HANDLER 469 select GPIOLIB 470 select HAVE_IDE 471 select IRQ_DOMAIN 472 select ISA 473 select NEED_MACH_MEMORY_H 474 select SPARSE_IRQ 475 help 476 Support for StrongARM 11x0 based boards. 477 478config ARCH_S3C24XX 479 bool "Samsung S3C24XX SoCs" 480 select ATAGS 481 select CLKSRC_SAMSUNG_PWM 482 select GPIO_SAMSUNG 483 select GPIOLIB 484 select GENERIC_IRQ_MULTI_HANDLER 485 select HAVE_S3C2410_I2C if I2C 486 select HAVE_S3C_RTC if RTC_CLASS 487 select NEED_MACH_IO_H 488 select S3C2410_WATCHDOG 489 select SAMSUNG_ATAGS 490 select USE_OF 491 select WATCHDOG 492 help 493 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 494 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 495 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 496 Samsung SMDK2410 development board (and derivatives). 497 498config ARCH_OMAP1 499 bool "TI OMAP1" 500 depends on MMU 501 select ARCH_OMAP 502 select CLKDEV_LOOKUP 503 select CLKSRC_MMIO 504 select GENERIC_IRQ_CHIP 505 select GENERIC_IRQ_MULTI_HANDLER 506 select GPIOLIB 507 select HAVE_IDE 508 select HAVE_LEGACY_CLK 509 select IRQ_DOMAIN 510 select NEED_MACH_IO_H if PCCARD 511 select NEED_MACH_MEMORY_H 512 select SPARSE_IRQ 513 help 514 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 515 516endchoice 517 518menu "Multiple platform selection" 519 depends on ARCH_MULTIPLATFORM 520 521comment "CPU Core family selection" 522 523config ARCH_MULTI_V4 524 bool "ARMv4 based platforms (FA526)" 525 depends on !ARCH_MULTI_V6_V7 526 select ARCH_MULTI_V4_V5 527 select CPU_FA526 528 529config ARCH_MULTI_V4T 530 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 531 depends on !ARCH_MULTI_V6_V7 532 select ARCH_MULTI_V4_V5 533 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 534 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 535 CPU_ARM925T || CPU_ARM940T) 536 537config ARCH_MULTI_V5 538 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 539 depends on !ARCH_MULTI_V6_V7 540 select ARCH_MULTI_V4_V5 541 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 542 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 543 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 544 545config ARCH_MULTI_V4_V5 546 bool 547 548config ARCH_MULTI_V6 549 bool "ARMv6 based platforms (ARM11)" 550 select ARCH_MULTI_V6_V7 551 select CPU_V6K 552 553config ARCH_MULTI_V7 554 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 555 default y 556 select ARCH_MULTI_V6_V7 557 select CPU_V7 558 select HAVE_SMP 559 560config ARCH_MULTI_V6_V7 561 bool 562 select MIGHT_HAVE_CACHE_L2X0 563 564config ARCH_MULTI_CPU_AUTO 565 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 566 select ARCH_MULTI_V5 567 568endmenu 569 570config ARCH_VIRT 571 bool "Dummy Virtual Machine" 572 depends on ARCH_MULTI_V7 573 select ARM_AMBA 574 select ARM_GIC 575 select ARM_GIC_V2M if PCI 576 select ARM_GIC_V3 577 select ARM_GIC_V3_ITS if PCI 578 select ARM_PSCI 579 select HAVE_ARM_ARCH_TIMER 580 select ARCH_SUPPORTS_BIG_ENDIAN 581 582# 583# This is sorted alphabetically by mach-* pathname. However, plat-* 584# Kconfigs may be included either alphabetically (according to the 585# plat- suffix) or along side the corresponding mach-* source. 586# 587source "arch/arm/mach-actions/Kconfig" 588 589source "arch/arm/mach-alpine/Kconfig" 590 591source "arch/arm/mach-artpec/Kconfig" 592 593source "arch/arm/mach-asm9260/Kconfig" 594 595source "arch/arm/mach-aspeed/Kconfig" 596 597source "arch/arm/mach-at91/Kconfig" 598 599source "arch/arm/mach-axxia/Kconfig" 600 601source "arch/arm/mach-bcm/Kconfig" 602 603source "arch/arm/mach-berlin/Kconfig" 604 605source "arch/arm/mach-clps711x/Kconfig" 606 607source "arch/arm/mach-cns3xxx/Kconfig" 608 609source "arch/arm/mach-davinci/Kconfig" 610 611source "arch/arm/mach-digicolor/Kconfig" 612 613source "arch/arm/mach-dove/Kconfig" 614 615source "arch/arm/mach-ep93xx/Kconfig" 616 617source "arch/arm/mach-exynos/Kconfig" 618 619source "arch/arm/mach-footbridge/Kconfig" 620 621source "arch/arm/mach-gemini/Kconfig" 622 623source "arch/arm/mach-highbank/Kconfig" 624 625source "arch/arm/mach-hisi/Kconfig" 626 627source "arch/arm/mach-imx/Kconfig" 628 629source "arch/arm/mach-integrator/Kconfig" 630 631source "arch/arm/mach-iop32x/Kconfig" 632 633source "arch/arm/mach-ixp4xx/Kconfig" 634 635source "arch/arm/mach-keystone/Kconfig" 636 637source "arch/arm/mach-lpc32xx/Kconfig" 638 639source "arch/arm/mach-mediatek/Kconfig" 640 641source "arch/arm/mach-meson/Kconfig" 642 643source "arch/arm/mach-milbeaut/Kconfig" 644 645source "arch/arm/mach-mmp/Kconfig" 646 647source "arch/arm/mach-moxart/Kconfig" 648 649source "arch/arm/mach-mstar/Kconfig" 650 651source "arch/arm/mach-mv78xx0/Kconfig" 652 653source "arch/arm/mach-mvebu/Kconfig" 654 655source "arch/arm/mach-mxs/Kconfig" 656 657source "arch/arm/mach-nomadik/Kconfig" 658 659source "arch/arm/mach-npcm/Kconfig" 660 661source "arch/arm/mach-nspire/Kconfig" 662 663source "arch/arm/plat-omap/Kconfig" 664 665source "arch/arm/mach-omap1/Kconfig" 666 667source "arch/arm/mach-omap2/Kconfig" 668 669source "arch/arm/mach-orion5x/Kconfig" 670 671source "arch/arm/mach-oxnas/Kconfig" 672 673source "arch/arm/mach-pxa/Kconfig" 674source "arch/arm/plat-pxa/Kconfig" 675 676source "arch/arm/mach-qcom/Kconfig" 677 678source "arch/arm/mach-rda/Kconfig" 679 680source "arch/arm/mach-realtek/Kconfig" 681 682source "arch/arm/mach-realview/Kconfig" 683 684source "arch/arm/mach-rockchip/Kconfig" 685 686source "arch/arm/mach-s3c/Kconfig" 687 688source "arch/arm/mach-s5pv210/Kconfig" 689 690source "arch/arm/mach-sa1100/Kconfig" 691 692source "arch/arm/mach-shmobile/Kconfig" 693 694source "arch/arm/mach-socfpga/Kconfig" 695 696source "arch/arm/mach-spear/Kconfig" 697 698source "arch/arm/mach-sti/Kconfig" 699 700source "arch/arm/mach-stm32/Kconfig" 701 702source "arch/arm/mach-sunxi/Kconfig" 703 704source "arch/arm/mach-tegra/Kconfig" 705 706source "arch/arm/mach-uniphier/Kconfig" 707 708source "arch/arm/mach-ux500/Kconfig" 709 710source "arch/arm/mach-versatile/Kconfig" 711 712source "arch/arm/mach-vexpress/Kconfig" 713 714source "arch/arm/mach-vt8500/Kconfig" 715 716source "arch/arm/mach-zynq/Kconfig" 717 718# ARMv7-M architecture 719config ARCH_LPC18XX 720 bool "NXP LPC18xx/LPC43xx" 721 depends on ARM_SINGLE_ARMV7M 722 select ARCH_HAS_RESET_CONTROLLER 723 select ARM_AMBA 724 select CLKSRC_LPC32XX 725 select PINCTRL 726 help 727 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 728 high performance microcontrollers. 729 730config ARCH_MPS2 731 bool "ARM MPS2 platform" 732 depends on ARM_SINGLE_ARMV7M 733 select ARM_AMBA 734 select CLKSRC_MPS2 735 help 736 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 737 with a range of available cores like Cortex-M3/M4/M7. 738 739 Please, note that depends which Application Note is used memory map 740 for the platform may vary, so adjustment of RAM base might be needed. 741 742# Definitions to make life easier 743config ARCH_ACORN 744 bool 745 746config PLAT_IOP 747 bool 748 749config PLAT_ORION 750 bool 751 select CLKSRC_MMIO 752 select COMMON_CLK 753 select GENERIC_IRQ_CHIP 754 select IRQ_DOMAIN 755 756config PLAT_ORION_LEGACY 757 bool 758 select PLAT_ORION 759 760config PLAT_PXA 761 bool 762 763config PLAT_VERSATILE 764 bool 765 766source "arch/arm/mm/Kconfig" 767 768config IWMMXT 769 bool "Enable iWMMXt support" 770 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 771 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 772 help 773 Enable support for iWMMXt context switching at run time if 774 running on a CPU that supports it. 775 776if !MMU 777source "arch/arm/Kconfig-nommu" 778endif 779 780config PJ4B_ERRATA_4742 781 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 782 depends on CPU_PJ4B && MACH_ARMADA_370 783 default y 784 help 785 When coming out of either a Wait for Interrupt (WFI) or a Wait for 786 Event (WFE) IDLE states, a specific timing sensitivity exists between 787 the retiring WFI/WFE instructions and the newly issued subsequent 788 instructions. This sensitivity can result in a CPU hang scenario. 789 Workaround: 790 The software must insert either a Data Synchronization Barrier (DSB) 791 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 792 instruction 793 794config ARM_ERRATA_326103 795 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 796 depends on CPU_V6 797 help 798 Executing a SWP instruction to read-only memory does not set bit 11 799 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 800 treat the access as a read, preventing a COW from occurring and 801 causing the faulting task to livelock. 802 803config ARM_ERRATA_411920 804 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 805 depends on CPU_V6 || CPU_V6K 806 help 807 Invalidation of the Instruction Cache operation can 808 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 809 It does not affect the MPCore. This option enables the ARM Ltd. 810 recommended workaround. 811 812config ARM_ERRATA_430973 813 bool "ARM errata: Stale prediction on replaced interworking branch" 814 depends on CPU_V7 815 help 816 This option enables the workaround for the 430973 Cortex-A8 817 r1p* erratum. If a code sequence containing an ARM/Thumb 818 interworking branch is replaced with another code sequence at the 819 same virtual address, whether due to self-modifying code or virtual 820 to physical address re-mapping, Cortex-A8 does not recover from the 821 stale interworking branch prediction. This results in Cortex-A8 822 executing the new code sequence in the incorrect ARM or Thumb state. 823 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 824 and also flushes the branch target cache at every context switch. 825 Note that setting specific bits in the ACTLR register may not be 826 available in non-secure mode. 827 828config ARM_ERRATA_458693 829 bool "ARM errata: Processor deadlock when a false hazard is created" 830 depends on CPU_V7 831 depends on !ARCH_MULTIPLATFORM 832 help 833 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 834 erratum. For very specific sequences of memory operations, it is 835 possible for a hazard condition intended for a cache line to instead 836 be incorrectly associated with a different cache line. This false 837 hazard might then cause a processor deadlock. The workaround enables 838 the L1 caching of the NEON accesses and disables the PLD instruction 839 in the ACTLR register. Note that setting specific bits in the ACTLR 840 register may not be available in non-secure mode. 841 842config ARM_ERRATA_460075 843 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 844 depends on CPU_V7 845 depends on !ARCH_MULTIPLATFORM 846 help 847 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 848 erratum. Any asynchronous access to the L2 cache may encounter a 849 situation in which recent store transactions to the L2 cache are lost 850 and overwritten with stale memory contents from external memory. The 851 workaround disables the write-allocate mode for the L2 cache via the 852 ACTLR register. Note that setting specific bits in the ACTLR register 853 may not be available in non-secure mode. 854 855config ARM_ERRATA_742230 856 bool "ARM errata: DMB operation may be faulty" 857 depends on CPU_V7 && SMP 858 depends on !ARCH_MULTIPLATFORM 859 help 860 This option enables the workaround for the 742230 Cortex-A9 861 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 862 between two write operations may not ensure the correct visibility 863 ordering of the two writes. This workaround sets a specific bit in 864 the diagnostic register of the Cortex-A9 which causes the DMB 865 instruction to behave as a DSB, ensuring the correct behaviour of 866 the two writes. 867 868config ARM_ERRATA_742231 869 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 870 depends on CPU_V7 && SMP 871 depends on !ARCH_MULTIPLATFORM 872 help 873 This option enables the workaround for the 742231 Cortex-A9 874 (r2p0..r2p2) erratum. Under certain conditions, specific to the 875 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 876 accessing some data located in the same cache line, may get corrupted 877 data due to bad handling of the address hazard when the line gets 878 replaced from one of the CPUs at the same time as another CPU is 879 accessing it. This workaround sets specific bits in the diagnostic 880 register of the Cortex-A9 which reduces the linefill issuing 881 capabilities of the processor. 882 883config ARM_ERRATA_643719 884 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 885 depends on CPU_V7 && SMP 886 default y 887 help 888 This option enables the workaround for the 643719 Cortex-A9 (prior to 889 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 890 register returns zero when it should return one. The workaround 891 corrects this value, ensuring cache maintenance operations which use 892 it behave as intended and avoiding data corruption. 893 894config ARM_ERRATA_720789 895 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 896 depends on CPU_V7 897 help 898 This option enables the workaround for the 720789 Cortex-A9 (prior to 899 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 900 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 901 As a consequence of this erratum, some TLB entries which should be 902 invalidated are not, resulting in an incoherency in the system page 903 tables. The workaround changes the TLB flushing routines to invalidate 904 entries regardless of the ASID. 905 906config ARM_ERRATA_743622 907 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 908 depends on CPU_V7 909 depends on !ARCH_MULTIPLATFORM 910 help 911 This option enables the workaround for the 743622 Cortex-A9 912 (r2p*) erratum. Under very rare conditions, a faulty 913 optimisation in the Cortex-A9 Store Buffer may lead to data 914 corruption. This workaround sets a specific bit in the diagnostic 915 register of the Cortex-A9 which disables the Store Buffer 916 optimisation, preventing the defect from occurring. This has no 917 visible impact on the overall performance or power consumption of the 918 processor. 919 920config ARM_ERRATA_751472 921 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 922 depends on CPU_V7 923 depends on !ARCH_MULTIPLATFORM 924 help 925 This option enables the workaround for the 751472 Cortex-A9 (prior 926 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 927 completion of a following broadcasted operation if the second 928 operation is received by a CPU before the ICIALLUIS has completed, 929 potentially leading to corrupted entries in the cache or TLB. 930 931config ARM_ERRATA_754322 932 bool "ARM errata: possible faulty MMU translations following an ASID switch" 933 depends on CPU_V7 934 help 935 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 936 r3p*) erratum. A speculative memory access may cause a page table walk 937 which starts prior to an ASID switch but completes afterwards. This 938 can populate the micro-TLB with a stale entry which may be hit with 939 the new ASID. This workaround places two dsb instructions in the mm 940 switching code so that no page table walks can cross the ASID switch. 941 942config ARM_ERRATA_754327 943 bool "ARM errata: no automatic Store Buffer drain" 944 depends on CPU_V7 && SMP 945 help 946 This option enables the workaround for the 754327 Cortex-A9 (prior to 947 r2p0) erratum. The Store Buffer does not have any automatic draining 948 mechanism and therefore a livelock may occur if an external agent 949 continuously polls a memory location waiting to observe an update. 950 This workaround defines cpu_relax() as smp_mb(), preventing correctly 951 written polling loops from denying visibility of updates to memory. 952 953config ARM_ERRATA_364296 954 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 955 depends on CPU_V6 956 help 957 This options enables the workaround for the 364296 ARM1136 958 r0p2 erratum (possible cache data corruption with 959 hit-under-miss enabled). It sets the undocumented bit 31 in 960 the auxiliary control register and the FI bit in the control 961 register, thus disabling hit-under-miss without putting the 962 processor into full low interrupt latency mode. ARM11MPCore 963 is not affected. 964 965config ARM_ERRATA_764369 966 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 967 depends on CPU_V7 && SMP 968 help 969 This option enables the workaround for erratum 764369 970 affecting Cortex-A9 MPCore with two or more processors (all 971 current revisions). Under certain timing circumstances, a data 972 cache line maintenance operation by MVA targeting an Inner 973 Shareable memory region may fail to proceed up to either the 974 Point of Coherency or to the Point of Unification of the 975 system. This workaround adds a DSB instruction before the 976 relevant cache maintenance functions and sets a specific bit 977 in the diagnostic control register of the SCU. 978 979config ARM_ERRATA_775420 980 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 981 depends on CPU_V7 982 help 983 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 984 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 985 operation aborts with MMU exception, it might cause the processor 986 to deadlock. This workaround puts DSB before executing ISB if 987 an abort may occur on cache maintenance. 988 989config ARM_ERRATA_798181 990 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 991 depends on CPU_V7 && SMP 992 help 993 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 994 adequately shooting down all use of the old entries. This 995 option enables the Linux kernel workaround for this erratum 996 which sends an IPI to the CPUs that are running the same ASID 997 as the one being invalidated. 998 999config ARM_ERRATA_773022 1000 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1001 depends on CPU_V7 1002 help 1003 This option enables the workaround for the 773022 Cortex-A15 1004 (up to r0p4) erratum. In certain rare sequences of code, the 1005 loop buffer may deliver incorrect instructions. This 1006 workaround disables the loop buffer to avoid the erratum. 1007 1008config ARM_ERRATA_818325_852422 1009 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1010 depends on CPU_V7 1011 help 1012 This option enables the workaround for: 1013 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1014 instruction might deadlock. Fixed in r0p1. 1015 - Cortex-A12 852422: Execution of a sequence of instructions might 1016 lead to either a data corruption or a CPU deadlock. Not fixed in 1017 any Cortex-A12 cores yet. 1018 This workaround for all both errata involves setting bit[12] of the 1019 Feature Register. This bit disables an optimisation applied to a 1020 sequence of 2 instructions that use opposing condition codes. 1021 1022config ARM_ERRATA_821420 1023 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1024 depends on CPU_V7 1025 help 1026 This option enables the workaround for the 821420 Cortex-A12 1027 (all revs) erratum. In very rare timing conditions, a sequence 1028 of VMOV to Core registers instructions, for which the second 1029 one is in the shadow of a branch or abort, can lead to a 1030 deadlock when the VMOV instructions are issued out-of-order. 1031 1032config ARM_ERRATA_825619 1033 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1034 depends on CPU_V7 1035 help 1036 This option enables the workaround for the 825619 Cortex-A12 1037 (all revs) erratum. Within rare timing constraints, executing a 1038 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1039 and Device/Strongly-Ordered loads and stores might cause deadlock 1040 1041config ARM_ERRATA_857271 1042 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1043 depends on CPU_V7 1044 help 1045 This option enables the workaround for the 857271 Cortex-A12 1046 (all revs) erratum. Under very rare timing conditions, the CPU might 1047 hang. The workaround is expected to have a < 1% performance impact. 1048 1049config ARM_ERRATA_852421 1050 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1051 depends on CPU_V7 1052 help 1053 This option enables the workaround for the 852421 Cortex-A17 1054 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1055 execution of a DMB ST instruction might fail to properly order 1056 stores from GroupA and stores from GroupB. 1057 1058config ARM_ERRATA_852423 1059 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1060 depends on CPU_V7 1061 help 1062 This option enables the workaround for: 1063 - Cortex-A17 852423: Execution of a sequence of instructions might 1064 lead to either a data corruption or a CPU deadlock. Not fixed in 1065 any Cortex-A17 cores yet. 1066 This is identical to Cortex-A12 erratum 852422. It is a separate 1067 config option from the A12 erratum due to the way errata are checked 1068 for and handled. 1069 1070config ARM_ERRATA_857272 1071 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1072 depends on CPU_V7 1073 help 1074 This option enables the workaround for the 857272 Cortex-A17 erratum. 1075 This erratum is not known to be fixed in any A17 revision. 1076 This is identical to Cortex-A12 erratum 857271. It is a separate 1077 config option from the A12 erratum due to the way errata are checked 1078 for and handled. 1079 1080endmenu 1081 1082source "arch/arm/common/Kconfig" 1083 1084menu "Bus support" 1085 1086config ISA 1087 bool 1088 help 1089 Find out whether you have ISA slots on your motherboard. ISA is the 1090 name of a bus system, i.e. the way the CPU talks to the other stuff 1091 inside your box. Other bus systems are PCI, EISA, MicroChannel 1092 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1093 newer boards don't support it. If you have ISA, say Y, otherwise N. 1094 1095# Select ISA DMA controller support 1096config ISA_DMA 1097 bool 1098 select ISA_DMA_API 1099 1100# Select ISA DMA interface 1101config ISA_DMA_API 1102 bool 1103 1104config PCI_NANOENGINE 1105 bool "BSE nanoEngine PCI support" 1106 depends on SA1100_NANOENGINE 1107 help 1108 Enable PCI on the BSE nanoEngine board. 1109 1110config ARM_ERRATA_814220 1111 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1112 depends on CPU_V7 1113 help 1114 The v7 ARM states that all cache and branch predictor maintenance 1115 operations that do not specify an address execute, relative to 1116 each other, in program order. 1117 However, because of this erratum, an L2 set/way cache maintenance 1118 operation can overtake an L1 set/way cache maintenance operation. 1119 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1120 r0p4, r0p5. 1121 1122endmenu 1123 1124menu "Kernel Features" 1125 1126config HAVE_SMP 1127 bool 1128 help 1129 This option should be selected by machines which have an SMP- 1130 capable CPU. 1131 1132 The only effect of this option is to make the SMP-related 1133 options available to the user for configuration. 1134 1135config SMP 1136 bool "Symmetric Multi-Processing" 1137 depends on CPU_V6K || CPU_V7 1138 depends on HAVE_SMP 1139 depends on MMU || ARM_MPU 1140 select IRQ_WORK 1141 help 1142 This enables support for systems with more than one CPU. If you have 1143 a system with only one CPU, say N. If you have a system with more 1144 than one CPU, say Y. 1145 1146 If you say N here, the kernel will run on uni- and multiprocessor 1147 machines, but will use only one CPU of a multiprocessor machine. If 1148 you say Y here, the kernel will run on many, but not all, 1149 uniprocessor machines. On a uniprocessor machine, the kernel 1150 will run faster if you say N here. 1151 1152 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1153 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1154 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1155 1156 If you don't know what to do here, say N. 1157 1158config SMP_ON_UP 1159 bool "Allow booting SMP kernel on uniprocessor systems" 1160 depends on SMP && !XIP_KERNEL && MMU 1161 default y 1162 help 1163 SMP kernels contain instructions which fail on non-SMP processors. 1164 Enabling this option allows the kernel to modify itself to make 1165 these instructions safe. Disabling it allows about 1K of space 1166 savings. 1167 1168 If you don't know what to do here, say Y. 1169 1170config ARM_CPU_TOPOLOGY 1171 bool "Support cpu topology definition" 1172 depends on SMP && CPU_V7 1173 default y 1174 help 1175 Support ARM cpu topology definition. The MPIDR register defines 1176 affinity between processors which is then used to describe the cpu 1177 topology of an ARM System. 1178 1179config SCHED_MC 1180 bool "Multi-core scheduler support" 1181 depends on ARM_CPU_TOPOLOGY 1182 help 1183 Multi-core scheduler support improves the CPU scheduler's decision 1184 making when dealing with multi-core CPU chips at a cost of slightly 1185 increased overhead in some places. If unsure say N here. 1186 1187config SCHED_SMT 1188 bool "SMT scheduler support" 1189 depends on ARM_CPU_TOPOLOGY 1190 help 1191 Improves the CPU scheduler's decision making when dealing with 1192 MultiThreading at a cost of slightly increased overhead in some 1193 places. If unsure say N here. 1194 1195config HAVE_ARM_SCU 1196 bool 1197 help 1198 This option enables support for the ARM snoop control unit 1199 1200config HAVE_ARM_ARCH_TIMER 1201 bool "Architected timer support" 1202 depends on CPU_V7 1203 select ARM_ARCH_TIMER 1204 help 1205 This option enables support for the ARM architected timer 1206 1207config HAVE_ARM_TWD 1208 bool 1209 help 1210 This options enables support for the ARM timer and watchdog unit 1211 1212config MCPM 1213 bool "Multi-Cluster Power Management" 1214 depends on CPU_V7 && SMP 1215 help 1216 This option provides the common power management infrastructure 1217 for (multi-)cluster based systems, such as big.LITTLE based 1218 systems. 1219 1220config MCPM_QUAD_CLUSTER 1221 bool 1222 depends on MCPM 1223 help 1224 To avoid wasting resources unnecessarily, MCPM only supports up 1225 to 2 clusters by default. 1226 Platforms with 3 or 4 clusters that use MCPM must select this 1227 option to allow the additional clusters to be managed. 1228 1229config BIG_LITTLE 1230 bool "big.LITTLE support (Experimental)" 1231 depends on CPU_V7 && SMP 1232 select MCPM 1233 help 1234 This option enables support selections for the big.LITTLE 1235 system architecture. 1236 1237config BL_SWITCHER 1238 bool "big.LITTLE switcher support" 1239 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1240 select CPU_PM 1241 help 1242 The big.LITTLE "switcher" provides the core functionality to 1243 transparently handle transition between a cluster of A15's 1244 and a cluster of A7's in a big.LITTLE system. 1245 1246config BL_SWITCHER_DUMMY_IF 1247 tristate "Simple big.LITTLE switcher user interface" 1248 depends on BL_SWITCHER && DEBUG_KERNEL 1249 help 1250 This is a simple and dummy char dev interface to control 1251 the big.LITTLE switcher core code. It is meant for 1252 debugging purposes only. 1253 1254choice 1255 prompt "Memory split" 1256 depends on MMU 1257 default VMSPLIT_3G 1258 help 1259 Select the desired split between kernel and user memory. 1260 1261 If you are not absolutely sure what you are doing, leave this 1262 option alone! 1263 1264 config VMSPLIT_3G 1265 bool "3G/1G user/kernel split" 1266 config VMSPLIT_3G_OPT 1267 depends on !ARM_LPAE 1268 bool "3G/1G user/kernel split (for full 1G low memory)" 1269 config VMSPLIT_2G 1270 bool "2G/2G user/kernel split" 1271 config VMSPLIT_1G 1272 bool "1G/3G user/kernel split" 1273endchoice 1274 1275config PAGE_OFFSET 1276 hex 1277 default PHYS_OFFSET if !MMU 1278 default 0x40000000 if VMSPLIT_1G 1279 default 0x80000000 if VMSPLIT_2G 1280 default 0xB0000000 if VMSPLIT_3G_OPT 1281 default 0xC0000000 1282 1283config KASAN_SHADOW_OFFSET 1284 hex 1285 depends on KASAN 1286 default 0x1f000000 if PAGE_OFFSET=0x40000000 1287 default 0x5f000000 if PAGE_OFFSET=0x80000000 1288 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1289 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1290 default 0xffffffff 1291 1292config NR_CPUS 1293 int "Maximum number of CPUs (2-32)" 1294 range 2 32 1295 depends on SMP 1296 default "4" 1297 1298config HOTPLUG_CPU 1299 bool "Support for hot-pluggable CPUs" 1300 depends on SMP 1301 select GENERIC_IRQ_MIGRATION 1302 help 1303 Say Y here to experiment with turning CPUs off and on. CPUs 1304 can be controlled through /sys/devices/system/cpu. 1305 1306config ARM_PSCI 1307 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1308 depends on HAVE_ARM_SMCCC 1309 select ARM_PSCI_FW 1310 help 1311 Say Y here if you want Linux to communicate with system firmware 1312 implementing the PSCI specification for CPU-centric power 1313 management operations described in ARM document number ARM DEN 1314 0022A ("Power State Coordination Interface System Software on 1315 ARM processors"). 1316 1317# The GPIO number here must be sorted by descending number. In case of 1318# a multiplatform kernel, we just want the highest value required by the 1319# selected platforms. 1320config ARCH_NR_GPIO 1321 int 1322 default 2048 if ARCH_SOCFPGA 1323 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1324 ARCH_ZYNQ || ARCH_ASPEED 1325 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1326 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1327 default 416 if ARCH_SUNXI 1328 default 392 if ARCH_U8500 1329 default 352 if ARCH_VT8500 1330 default 288 if ARCH_ROCKCHIP 1331 default 264 if MACH_H4700 1332 default 0 1333 help 1334 Maximum number of GPIOs in the system. 1335 1336 If unsure, leave the default value. 1337 1338config HZ_FIXED 1339 int 1340 default 128 if SOC_AT91RM9200 1341 default 0 1342 1343choice 1344 depends on HZ_FIXED = 0 1345 prompt "Timer frequency" 1346 1347config HZ_100 1348 bool "100 Hz" 1349 1350config HZ_200 1351 bool "200 Hz" 1352 1353config HZ_250 1354 bool "250 Hz" 1355 1356config HZ_300 1357 bool "300 Hz" 1358 1359config HZ_500 1360 bool "500 Hz" 1361 1362config HZ_1000 1363 bool "1000 Hz" 1364 1365endchoice 1366 1367config HZ 1368 int 1369 default HZ_FIXED if HZ_FIXED != 0 1370 default 100 if HZ_100 1371 default 200 if HZ_200 1372 default 250 if HZ_250 1373 default 300 if HZ_300 1374 default 500 if HZ_500 1375 default 1000 1376 1377config SCHED_HRTICK 1378 def_bool HIGH_RES_TIMERS 1379 1380config THUMB2_KERNEL 1381 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1382 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1383 default y if CPU_THUMBONLY 1384 select ARM_UNWIND 1385 help 1386 By enabling this option, the kernel will be compiled in 1387 Thumb-2 mode. 1388 1389 If unsure, say N. 1390 1391config ARM_PATCH_IDIV 1392 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1393 depends on CPU_32v7 && !XIP_KERNEL 1394 default y 1395 help 1396 The ARM compiler inserts calls to __aeabi_idiv() and 1397 __aeabi_uidiv() when it needs to perform division on signed 1398 and unsigned integers. Some v7 CPUs have support for the sdiv 1399 and udiv instructions that can be used to implement those 1400 functions. 1401 1402 Enabling this option allows the kernel to modify itself to 1403 replace the first two instructions of these library functions 1404 with the sdiv or udiv plus "bx lr" instructions when the CPU 1405 it is running on supports them. Typically this will be faster 1406 and less power intensive than running the original library 1407 code to do integer division. 1408 1409config AEABI 1410 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1411 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1412 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1413 help 1414 This option allows for the kernel to be compiled using the latest 1415 ARM ABI (aka EABI). This is only useful if you are using a user 1416 space environment that is also compiled with EABI. 1417 1418 Since there are major incompatibilities between the legacy ABI and 1419 EABI, especially with regard to structure member alignment, this 1420 option also changes the kernel syscall calling convention to 1421 disambiguate both ABIs and allow for backward compatibility support 1422 (selected with CONFIG_OABI_COMPAT). 1423 1424 To use this you need GCC version 4.0.0 or later. 1425 1426config OABI_COMPAT 1427 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1428 depends on AEABI && !THUMB2_KERNEL 1429 help 1430 This option preserves the old syscall interface along with the 1431 new (ARM EABI) one. It also provides a compatibility layer to 1432 intercept syscalls that have structure arguments which layout 1433 in memory differs between the legacy ABI and the new ARM EABI 1434 (only for non "thumb" binaries). This option adds a tiny 1435 overhead to all syscalls and produces a slightly larger kernel. 1436 1437 The seccomp filter system will not be available when this is 1438 selected, since there is no way yet to sensibly distinguish 1439 between calling conventions during filtering. 1440 1441 If you know you'll be using only pure EABI user space then you 1442 can say N here. If this option is not selected and you attempt 1443 to execute a legacy ABI binary then the result will be 1444 UNPREDICTABLE (in fact it can be predicted that it won't work 1445 at all). If in doubt say N. 1446 1447config ARCH_SELECT_MEMORY_MODEL 1448 bool 1449 1450config ARCH_FLATMEM_ENABLE 1451 bool 1452 1453config ARCH_SPARSEMEM_ENABLE 1454 bool 1455 select SPARSEMEM_STATIC if SPARSEMEM 1456 1457config HIGHMEM 1458 bool "High Memory Support" 1459 depends on MMU 1460 select KMAP_LOCAL 1461 help 1462 The address space of ARM processors is only 4 Gigabytes large 1463 and it has to accommodate user address space, kernel address 1464 space as well as some memory mapped IO. That means that, if you 1465 have a large amount of physical memory and/or IO, not all of the 1466 memory can be "permanently mapped" by the kernel. The physical 1467 memory that is not permanently mapped is called "high memory". 1468 1469 Depending on the selected kernel/user memory split, minimum 1470 vmalloc space and actual amount of RAM, you may not need this 1471 option which should result in a slightly faster kernel. 1472 1473 If unsure, say n. 1474 1475config HIGHPTE 1476 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1477 depends on HIGHMEM 1478 default y 1479 help 1480 The VM uses one page of physical memory for each page table. 1481 For systems with a lot of processes, this can use a lot of 1482 precious low memory, eventually leading to low memory being 1483 consumed by page tables. Setting this option will allow 1484 user-space 2nd level page tables to reside in high memory. 1485 1486config CPU_SW_DOMAIN_PAN 1487 bool "Enable use of CPU domains to implement privileged no-access" 1488 depends on MMU && !ARM_LPAE 1489 default y 1490 help 1491 Increase kernel security by ensuring that normal kernel accesses 1492 are unable to access userspace addresses. This can help prevent 1493 use-after-free bugs becoming an exploitable privilege escalation 1494 by ensuring that magic values (such as LIST_POISON) will always 1495 fault when dereferenced. 1496 1497 CPUs with low-vector mappings use a best-efforts implementation. 1498 Their lower 1MB needs to remain accessible for the vectors, but 1499 the remainder of userspace will become appropriately inaccessible. 1500 1501config HW_PERF_EVENTS 1502 def_bool y 1503 depends on ARM_PMU 1504 1505config SYS_SUPPORTS_HUGETLBFS 1506 def_bool y 1507 depends on ARM_LPAE 1508 1509config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1510 def_bool y 1511 depends on ARM_LPAE 1512 1513config ARCH_WANT_GENERAL_HUGETLB 1514 def_bool y 1515 1516config ARM_MODULE_PLTS 1517 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1518 depends on MODULES 1519 default y 1520 help 1521 Allocate PLTs when loading modules so that jumps and calls whose 1522 targets are too far away for their relative offsets to be encoded 1523 in the instructions themselves can be bounced via veneers in the 1524 module's PLT. This allows modules to be allocated in the generic 1525 vmalloc area after the dedicated module memory area has been 1526 exhausted. The modules will use slightly more memory, but after 1527 rounding up to page size, the actual memory footprint is usually 1528 the same. 1529 1530 Disabling this is usually safe for small single-platform 1531 configurations. If unsure, say y. 1532 1533config FORCE_MAX_ZONEORDER 1534 int "Maximum zone order" 1535 default "12" if SOC_AM33XX 1536 default "9" if SA1111 1537 default "11" 1538 help 1539 The kernel memory allocator divides physically contiguous memory 1540 blocks into "zones", where each zone is a power of two number of 1541 pages. This option selects the largest power of two that the kernel 1542 keeps in the memory allocator. If you need to allocate very large 1543 blocks of physically contiguous memory, then you may need to 1544 increase this value. 1545 1546 This config option is actually maximum order plus one. For example, 1547 a value of 11 means that the largest free memory block is 2^10 pages. 1548 1549config ALIGNMENT_TRAP 1550 def_bool CPU_CP15_MMU 1551 select HAVE_PROC_CPU if PROC_FS 1552 help 1553 ARM processors cannot fetch/store information which is not 1554 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1555 address divisible by 4. On 32-bit ARM processors, these non-aligned 1556 fetch/store instructions will be emulated in software if you say 1557 here, which has a severe performance impact. This is necessary for 1558 correct operation of some network protocols. With an IP-only 1559 configuration it is safe to say N, otherwise say Y. 1560 1561config UACCESS_WITH_MEMCPY 1562 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1563 depends on MMU 1564 default y if CPU_FEROCEON 1565 help 1566 Implement faster copy_to_user and clear_user methods for CPU 1567 cores where a 8-word STM instruction give significantly higher 1568 memory write throughput than a sequence of individual 32bit stores. 1569 1570 A possible side effect is a slight increase in scheduling latency 1571 between threads sharing the same address space if they invoke 1572 such copy operations with large buffers. 1573 1574 However, if the CPU data cache is using a write-allocate mode, 1575 this option is unlikely to provide any performance gain. 1576 1577config PARAVIRT 1578 bool "Enable paravirtualization code" 1579 help 1580 This changes the kernel so it can modify itself when it is run 1581 under a hypervisor, potentially improving performance significantly 1582 over full virtualization. 1583 1584config PARAVIRT_TIME_ACCOUNTING 1585 bool "Paravirtual steal time accounting" 1586 select PARAVIRT 1587 help 1588 Select this option to enable fine granularity task steal time 1589 accounting. Time spent executing other tasks in parallel with 1590 the current vCPU is discounted from the vCPU power. To account for 1591 that, there can be a small performance impact. 1592 1593 If in doubt, say N here. 1594 1595config XEN_DOM0 1596 def_bool y 1597 depends on XEN 1598 1599config XEN 1600 bool "Xen guest support on ARM" 1601 depends on ARM && AEABI && OF 1602 depends on CPU_V7 && !CPU_V6 1603 depends on !GENERIC_ATOMIC64 1604 depends on MMU 1605 select ARCH_DMA_ADDR_T_64BIT 1606 select ARM_PSCI 1607 select SWIOTLB 1608 select SWIOTLB_XEN 1609 select PARAVIRT 1610 help 1611 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1612 1613config STACKPROTECTOR_PER_TASK 1614 bool "Use a unique stack canary value for each task" 1615 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1616 select GCC_PLUGIN_ARM_SSP_PER_TASK 1617 default y 1618 help 1619 Due to the fact that GCC uses an ordinary symbol reference from 1620 which to load the value of the stack canary, this value can only 1621 change at reboot time on SMP systems, and all tasks running in the 1622 kernel's address space are forced to use the same canary value for 1623 the entire duration that the system is up. 1624 1625 Enable this option to switch to a different method that uses a 1626 different canary value for each task. 1627 1628endmenu 1629 1630menu "Boot options" 1631 1632config USE_OF 1633 bool "Flattened Device Tree support" 1634 select IRQ_DOMAIN 1635 select OF 1636 help 1637 Include support for flattened device tree machine descriptions. 1638 1639config ATAGS 1640 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1641 default y 1642 help 1643 This is the traditional way of passing data to the kernel at boot 1644 time. If you are solely relying on the flattened device tree (or 1645 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1646 to remove ATAGS support from your kernel binary. If unsure, 1647 leave this to y. 1648 1649config DEPRECATED_PARAM_STRUCT 1650 bool "Provide old way to pass kernel parameters" 1651 depends on ATAGS 1652 help 1653 This was deprecated in 2001 and announced to live on for 5 years. 1654 Some old boot loaders still use this way. 1655 1656# Compressed boot loader in ROM. Yes, we really want to ask about 1657# TEXT and BSS so we preserve their values in the config files. 1658config ZBOOT_ROM_TEXT 1659 hex "Compressed ROM boot loader base address" 1660 default 0x0 1661 help 1662 The physical address at which the ROM-able zImage is to be 1663 placed in the target. Platforms which normally make use of 1664 ROM-able zImage formats normally set this to a suitable 1665 value in their defconfig file. 1666 1667 If ZBOOT_ROM is not enabled, this has no effect. 1668 1669config ZBOOT_ROM_BSS 1670 hex "Compressed ROM boot loader BSS address" 1671 default 0x0 1672 help 1673 The base address of an area of read/write memory in the target 1674 for the ROM-able zImage which must be available while the 1675 decompressor is running. It must be large enough to hold the 1676 entire decompressed kernel plus an additional 128 KiB. 1677 Platforms which normally make use of ROM-able zImage formats 1678 normally set this to a suitable value in their defconfig file. 1679 1680 If ZBOOT_ROM is not enabled, this has no effect. 1681 1682config ZBOOT_ROM 1683 bool "Compressed boot loader in ROM/flash" 1684 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1685 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1686 help 1687 Say Y here if you intend to execute your compressed kernel image 1688 (zImage) directly from ROM or flash. If unsure, say N. 1689 1690config ARM_APPENDED_DTB 1691 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1692 depends on OF 1693 help 1694 With this option, the boot code will look for a device tree binary 1695 (DTB) appended to zImage 1696 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1697 1698 This is meant as a backward compatibility convenience for those 1699 systems with a bootloader that can't be upgraded to accommodate 1700 the documented boot protocol using a device tree. 1701 1702 Beware that there is very little in terms of protection against 1703 this option being confused by leftover garbage in memory that might 1704 look like a DTB header after a reboot if no actual DTB is appended 1705 to zImage. Do not leave this option active in a production kernel 1706 if you don't intend to always append a DTB. Proper passing of the 1707 location into r2 of a bootloader provided DTB is always preferable 1708 to this option. 1709 1710config ARM_ATAG_DTB_COMPAT 1711 bool "Supplement the appended DTB with traditional ATAG information" 1712 depends on ARM_APPENDED_DTB 1713 help 1714 Some old bootloaders can't be updated to a DTB capable one, yet 1715 they provide ATAGs with memory configuration, the ramdisk address, 1716 the kernel cmdline string, etc. Such information is dynamically 1717 provided by the bootloader and can't always be stored in a static 1718 DTB. To allow a device tree enabled kernel to be used with such 1719 bootloaders, this option allows zImage to extract the information 1720 from the ATAG list and store it at run time into the appended DTB. 1721 1722choice 1723 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1724 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1725 1726config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1727 bool "Use bootloader kernel arguments if available" 1728 help 1729 Uses the command-line options passed by the boot loader instead of 1730 the device tree bootargs property. If the boot loader doesn't provide 1731 any, the device tree bootargs property will be used. 1732 1733config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1734 bool "Extend with bootloader kernel arguments" 1735 help 1736 The command-line arguments provided by the boot loader will be 1737 appended to the the device tree bootargs property. 1738 1739endchoice 1740 1741config CMDLINE 1742 string "Default kernel command string" 1743 default "" 1744 help 1745 On some architectures (e.g. CATS), there is currently no way 1746 for the boot loader to pass arguments to the kernel. For these 1747 architectures, you should supply some command-line options at build 1748 time by entering them here. As a minimum, you should specify the 1749 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1750 1751choice 1752 prompt "Kernel command line type" if CMDLINE != "" 1753 default CMDLINE_FROM_BOOTLOADER 1754 depends on ATAGS 1755 1756config CMDLINE_FROM_BOOTLOADER 1757 bool "Use bootloader kernel arguments if available" 1758 help 1759 Uses the command-line options passed by the boot loader. If 1760 the boot loader doesn't provide any, the default kernel command 1761 string provided in CMDLINE will be used. 1762 1763config CMDLINE_EXTEND 1764 bool "Extend bootloader kernel arguments" 1765 help 1766 The command-line arguments provided by the boot loader will be 1767 appended to the default kernel command string. 1768 1769config CMDLINE_FORCE 1770 bool "Always use the default kernel command string" 1771 help 1772 Always use the default kernel command string, even if the boot 1773 loader passes other arguments to the kernel. 1774 This is useful if you cannot or don't want to change the 1775 command-line options your boot loader passes to the kernel. 1776endchoice 1777 1778config XIP_KERNEL 1779 bool "Kernel Execute-In-Place from ROM" 1780 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1781 help 1782 Execute-In-Place allows the kernel to run from non-volatile storage 1783 directly addressable by the CPU, such as NOR flash. This saves RAM 1784 space since the text section of the kernel is not loaded from flash 1785 to RAM. Read-write sections, such as the data section and stack, 1786 are still copied to RAM. The XIP kernel is not compressed since 1787 it has to run directly from flash, so it will take more space to 1788 store it. The flash address used to link the kernel object files, 1789 and for storing it, is configuration dependent. Therefore, if you 1790 say Y here, you must know the proper physical address where to 1791 store the kernel image depending on your own flash memory usage. 1792 1793 Also note that the make target becomes "make xipImage" rather than 1794 "make zImage" or "make Image". The final kernel binary to put in 1795 ROM memory will be arch/arm/boot/xipImage. 1796 1797 If unsure, say N. 1798 1799config XIP_PHYS_ADDR 1800 hex "XIP Kernel Physical Location" 1801 depends on XIP_KERNEL 1802 default "0x00080000" 1803 help 1804 This is the physical address in your flash memory the kernel will 1805 be linked for and stored to. This address is dependent on your 1806 own flash usage. 1807 1808config XIP_DEFLATED_DATA 1809 bool "Store kernel .data section compressed in ROM" 1810 depends on XIP_KERNEL 1811 select ZLIB_INFLATE 1812 help 1813 Before the kernel is actually executed, its .data section has to be 1814 copied to RAM from ROM. This option allows for storing that data 1815 in compressed form and decompressed to RAM rather than merely being 1816 copied, saving some precious ROM space. A possible drawback is a 1817 slightly longer boot delay. 1818 1819config KEXEC 1820 bool "Kexec system call (EXPERIMENTAL)" 1821 depends on (!SMP || PM_SLEEP_SMP) 1822 depends on MMU 1823 select KEXEC_CORE 1824 help 1825 kexec is a system call that implements the ability to shutdown your 1826 current kernel, and to start another kernel. It is like a reboot 1827 but it is independent of the system firmware. And like a reboot 1828 you can start any kernel with it, not just Linux. 1829 1830 It is an ongoing process to be certain the hardware in a machine 1831 is properly shutdown, so do not be surprised if this code does not 1832 initially work for you. 1833 1834config ATAGS_PROC 1835 bool "Export atags in procfs" 1836 depends on ATAGS && KEXEC 1837 default y 1838 help 1839 Should the atags used to boot the kernel be exported in an "atags" 1840 file in procfs. Useful with kexec. 1841 1842config CRASH_DUMP 1843 bool "Build kdump crash kernel (EXPERIMENTAL)" 1844 help 1845 Generate crash dump after being started by kexec. This should 1846 be normally only set in special crash dump kernels which are 1847 loaded in the main kernel with kexec-tools into a specially 1848 reserved region and then later executed after a crash by 1849 kdump/kexec. The crash dump kernel must be compiled to a 1850 memory address not used by the main kernel 1851 1852 For more details see Documentation/admin-guide/kdump/kdump.rst 1853 1854config AUTO_ZRELADDR 1855 bool "Auto calculation of the decompressed kernel image address" 1856 help 1857 ZRELADDR is the physical address where the decompressed kernel 1858 image will be placed. If AUTO_ZRELADDR is selected, the address 1859 will be determined at run-time by masking the current IP with 1860 0xf8000000. This assumes the zImage being placed in the first 128MB 1861 from start of memory. 1862 1863config EFI_STUB 1864 bool 1865 1866config EFI 1867 bool "UEFI runtime support" 1868 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1869 select UCS2_STRING 1870 select EFI_PARAMS_FROM_FDT 1871 select EFI_STUB 1872 select EFI_GENERIC_STUB 1873 select EFI_RUNTIME_WRAPPERS 1874 help 1875 This option provides support for runtime services provided 1876 by UEFI firmware (such as non-volatile variables, realtime 1877 clock, and platform reset). A UEFI stub is also provided to 1878 allow the kernel to be booted as an EFI application. This 1879 is only useful for kernels that may run on systems that have 1880 UEFI firmware. 1881 1882config DMI 1883 bool "Enable support for SMBIOS (DMI) tables" 1884 depends on EFI 1885 default y 1886 help 1887 This enables SMBIOS/DMI feature for systems. 1888 1889 This option is only useful on systems that have UEFI firmware. 1890 However, even with this option, the resultant kernel should 1891 continue to boot on existing non-UEFI platforms. 1892 1893 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1894 i.e., the the practice of identifying the platform via DMI to 1895 decide whether certain workarounds for buggy hardware and/or 1896 firmware need to be enabled. This would require the DMI subsystem 1897 to be enabled much earlier than we do on ARM, which is non-trivial. 1898 1899endmenu 1900 1901menu "CPU Power Management" 1902 1903source "drivers/cpufreq/Kconfig" 1904 1905source "drivers/cpuidle/Kconfig" 1906 1907endmenu 1908 1909menu "Floating point emulation" 1910 1911comment "At least one emulation must be selected" 1912 1913config FPE_NWFPE 1914 bool "NWFPE math emulation" 1915 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1916 help 1917 Say Y to include the NWFPE floating point emulator in the kernel. 1918 This is necessary to run most binaries. Linux does not currently 1919 support floating point hardware so you need to say Y here even if 1920 your machine has an FPA or floating point co-processor podule. 1921 1922 You may say N here if you are going to load the Acorn FPEmulator 1923 early in the bootup. 1924 1925config FPE_NWFPE_XP 1926 bool "Support extended precision" 1927 depends on FPE_NWFPE 1928 help 1929 Say Y to include 80-bit support in the kernel floating-point 1930 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1931 Note that gcc does not generate 80-bit operations by default, 1932 so in most cases this option only enlarges the size of the 1933 floating point emulator without any good reason. 1934 1935 You almost surely want to say N here. 1936 1937config FPE_FASTFPE 1938 bool "FastFPE math emulation (EXPERIMENTAL)" 1939 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1940 help 1941 Say Y here to include the FAST floating point emulator in the kernel. 1942 This is an experimental much faster emulator which now also has full 1943 precision for the mantissa. It does not support any exceptions. 1944 It is very simple, and approximately 3-6 times faster than NWFPE. 1945 1946 It should be sufficient for most programs. It may be not suitable 1947 for scientific calculations, but you have to check this for yourself. 1948 If you do not feel you need a faster FP emulation you should better 1949 choose NWFPE. 1950 1951config VFP 1952 bool "VFP-format floating point maths" 1953 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1954 help 1955 Say Y to include VFP support code in the kernel. This is needed 1956 if your hardware includes a VFP unit. 1957 1958 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1959 release notes and additional status information. 1960 1961 Say N if your target does not have VFP hardware. 1962 1963config VFPv3 1964 bool 1965 depends on VFP 1966 default y if CPU_V7 1967 1968config NEON 1969 bool "Advanced SIMD (NEON) Extension support" 1970 depends on VFPv3 && CPU_V7 1971 help 1972 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1973 Extension. 1974 1975config KERNEL_MODE_NEON 1976 bool "Support for NEON in kernel mode" 1977 depends on NEON && AEABI 1978 help 1979 Say Y to include support for NEON in kernel mode. 1980 1981endmenu 1982 1983menu "Power management options" 1984 1985source "kernel/power/Kconfig" 1986 1987config ARCH_SUSPEND_POSSIBLE 1988 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1989 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1990 def_bool y 1991 1992config ARM_CPU_SUSPEND 1993 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1994 depends on ARCH_SUSPEND_POSSIBLE 1995 1996config ARCH_HIBERNATION_POSSIBLE 1997 bool 1998 depends on MMU 1999 default y if ARCH_SUSPEND_POSSIBLE 2000 2001endmenu 2002 2003source "drivers/firmware/Kconfig" 2004 2005if CRYPTO 2006source "arch/arm/crypto/Kconfig" 2007endif 2008 2009source "arch/arm/Kconfig.assembler" 2010