1c121c506SVineet Gupta/* 2c121c506SVineet Gupta * ARC CPU startup Code 3c121c506SVineet Gupta * 4c121c506SVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 5c121c506SVineet Gupta * 6c121c506SVineet Gupta * This program is free software; you can redistribute it and/or modify 7c121c506SVineet Gupta * it under the terms of the GNU General Public License version 2 as 8c121c506SVineet Gupta * published by the Free Software Foundation. 9c121c506SVineet Gupta * 10c121c506SVineet Gupta * Vineetg: Dec 2007 11c121c506SVineet Gupta * -Check if we are running on Simulator or on real hardware 12c121c506SVineet Gupta * to skip certain things during boot on simulator 13c121c506SVineet Gupta */ 14c121c506SVineet Gupta 15c121c506SVineet Gupta#include <asm/asm-offsets.h> 16c121c506SVineet Gupta#include <asm/entry.h> 17c121c506SVineet Gupta#include <linux/linkage.h> 18c121c506SVineet Gupta#include <asm/arcregs.h> 19c121c506SVineet Gupta 20c121c506SVineet Gupta .cpu A7 21c121c506SVineet Gupta 22c121c506SVineet Gupta .section .init.text, "ax",@progbits 23c121c506SVineet Gupta .type stext, @function 24c121c506SVineet Gupta .globl stext 25c121c506SVineet Guptastext: 26c121c506SVineet Gupta ;------------------------------------------------------------------- 27c121c506SVineet Gupta ; Don't clobber r0-r4 yet. It might have bootloader provided info 28c121c506SVineet Gupta ;------------------------------------------------------------------- 29c121c506SVineet Gupta 3005b016ecSVineet Gupta sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] 3105b016ecSVineet Gupta 3241195d23SVineet Gupta#ifdef CONFIG_SMP 3341195d23SVineet Gupta ; Only Boot (Master) proceeds. Others wait in platform dependent way 3441195d23SVineet Gupta ; IDENTITY Reg [ 3 2 1 0 ] 3541195d23SVineet Gupta ; (cpu-id) ^^^ => Zero for UP ARC700 3641195d23SVineet Gupta ; => #Core-ID if SMP (Master 0) 37c3567f8aSNoam Camus ; Note that non-boot CPUs might not land here if halt-on-reset and 38c3567f8aSNoam Camus ; instead breath life from @first_lines_of_secondary, but we still 39c3567f8aSNoam Camus ; need to make sure only boot cpu takes this path. 4041195d23SVineet Gupta GET_CPU_ID r5 4141195d23SVineet Gupta cmp r5, 0 4241195d23SVineet Gupta jnz arc_platform_smp_wait_to_boot 4341195d23SVineet Gupta#endif 44c121c506SVineet Gupta ; Clear BSS before updating any globals 45c121c506SVineet Gupta ; XXX: use ZOL here 46c121c506SVineet Gupta mov r5, __bss_start 47c121c506SVineet Gupta mov r6, __bss_stop 48c121c506SVineet Gupta1: 49c121c506SVineet Gupta st.ab 0, [r5,4] 50c121c506SVineet Gupta brlt r5, r6, 1b 51c121c506SVineet Gupta 52*59ed9413SVineet Gupta ; Uboot - kernel ABI 53*59ed9413SVineet Gupta ; r0 = [0] No uboot interaction, [1] cmdline in r2, [2] DTB in r2 54*59ed9413SVineet Gupta ; r1 = magic number (board identity, unused as of now 55*59ed9413SVineet Gupta ; r2 = pointer to uboot provided cmdline or external DTB in mem 56*59ed9413SVineet Gupta ; These are handled later in setup_arch() 57*59ed9413SVineet Gupta st r0, [@uboot_tag] 58*59ed9413SVineet Gupta st r2, [@uboot_arg] 59c121c506SVineet Gupta 60c121c506SVineet Gupta ; Identify if running on ISS vs Silicon 61c121c506SVineet Gupta ; IDENTITY Reg [ 3 2 1 0 ] 62c121c506SVineet Gupta ; (chip-id) ^^^^^ ==> 0xffff for ISS 63c121c506SVineet Gupta lr r0, [identity] 64c121c506SVineet Gupta lsr r3, r0, 16 65c121c506SVineet Gupta cmp r3, 0xffff 66c121c506SVineet Gupta mov.z r4, 0 67c121c506SVineet Gupta mov.nz r4, 1 68c121c506SVineet Gupta st r4, [@running_on_hw] 69c121c506SVineet Gupta 70c121c506SVineet Gupta ; setup "current" tsk and optionally cache it in dedicated r25 71c121c506SVineet Gupta mov r9, @init_task 72c121c506SVineet Gupta SET_CURR_TASK_ON_CPU r9, r0 ; r9 = tsk, r0 = scratch 73c121c506SVineet Gupta 74c121c506SVineet Gupta ; setup stack (fp, sp) 75c121c506SVineet Gupta mov fp, 0 76c121c506SVineet Gupta 77c121c506SVineet Gupta ; tsk->thread_info is really a PAGE, whose bottom hoists stack 78c121c506SVineet Gupta GET_TSK_STACK_BASE r9, sp ; r9 = tsk, sp = stack base(output) 79c121c506SVineet Gupta 80c121c506SVineet Gupta j start_kernel ; "C" entry point 8141195d23SVineet Gupta 8241195d23SVineet Gupta#ifdef CONFIG_SMP 8341195d23SVineet Gupta;---------------------------------------------------------------- 8441195d23SVineet Gupta; First lines of code run by secondary before jumping to 'C' 8541195d23SVineet Gupta;---------------------------------------------------------------- 868f5d221bSChen Gang .section .text, "ax",@progbits 8741195d23SVineet Gupta .type first_lines_of_secondary, @function 8841195d23SVineet Gupta .globl first_lines_of_secondary 8941195d23SVineet Gupta 9041195d23SVineet Guptafirst_lines_of_secondary: 9141195d23SVineet Gupta 92c3567f8aSNoam Camus sr @_int_vec_base_lds, [AUX_INTR_VEC_BASE] 93c3567f8aSNoam Camus 9441195d23SVineet Gupta ; setup per-cpu idle task as "current" on this CPU 9541195d23SVineet Gupta ld r0, [@secondary_idle_tsk] 9641195d23SVineet Gupta SET_CURR_TASK_ON_CPU r0, r1 9741195d23SVineet Gupta 9841195d23SVineet Gupta ; setup stack (fp, sp) 9941195d23SVineet Gupta mov fp, 0 10041195d23SVineet Gupta 10141195d23SVineet Gupta ; set it's stack base to tsk->thread_info bottom 10241195d23SVineet Gupta GET_TSK_STACK_BASE r0, sp 10341195d23SVineet Gupta 10441195d23SVineet Gupta j start_kernel_secondary 10541195d23SVineet Gupta 10641195d23SVineet Gupta#endif 107