1fe6cb7b0SVineet Gupta /* SPDX-License-Identifier: GPL-2.0-only */ 2fe6cb7b0SVineet Gupta /* 3fe6cb7b0SVineet Gupta * Copyright (C) 2020 Synopsys, Inc. (www.synopsys.com) 4fe6cb7b0SVineet Gupta */ 5fe6cb7b0SVineet Gupta 6fe6cb7b0SVineet Gupta /* 7fe6cb7b0SVineet Gupta * Helpers for implemenintg paging levels 8fe6cb7b0SVineet Gupta */ 9fe6cb7b0SVineet Gupta 10fe6cb7b0SVineet Gupta #ifndef _ASM_ARC_PGTABLE_LEVELS_H 11fe6cb7b0SVineet Gupta #define _ASM_ARC_PGTABLE_LEVELS_H 12fe6cb7b0SVineet Gupta 13*2dde02abSVineet Gupta #if CONFIG_PGTABLE_LEVELS == 2 14*2dde02abSVineet Gupta 15fe6cb7b0SVineet Gupta /* 16fe6cb7b0SVineet Gupta * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS) 17fe6cb7b0SVineet Gupta * 18fe6cb7b0SVineet Gupta * [31] 32 bit virtual address [0] 19fe6cb7b0SVineet Gupta * ------------------------------------------------------- 20fe6cb7b0SVineet Gupta * | | <---------- PGDIR_SHIFT ----------> | 21fe6cb7b0SVineet Gupta * | | | <-- PAGE_SHIFT --> | 22fe6cb7b0SVineet Gupta * ------------------------------------------------------- 23fe6cb7b0SVineet Gupta * | | | 24fe6cb7b0SVineet Gupta * | | --> off in page frame 25fe6cb7b0SVineet Gupta * | ---> index into Page Table 26fe6cb7b0SVineet Gupta * ----> index into Page Directory 27fe6cb7b0SVineet Gupta * 28fe6cb7b0SVineet Gupta * Given software walk, the vaddr split is arbitrary set to 11:8:13 29fe6cb7b0SVineet Gupta * However enabling of super page in a 2 level regime pegs PGDIR_SHIFT to 30fe6cb7b0SVineet Gupta * super page size. 31fe6cb7b0SVineet Gupta */ 32fe6cb7b0SVineet Gupta 33fe6cb7b0SVineet Gupta #if defined(CONFIG_ARC_HUGEPAGE_16M) 34fe6cb7b0SVineet Gupta #define PGDIR_SHIFT 24 35fe6cb7b0SVineet Gupta #elif defined(CONFIG_ARC_HUGEPAGE_2M) 36fe6cb7b0SVineet Gupta #define PGDIR_SHIFT 21 37fe6cb7b0SVineet Gupta #else 38fe6cb7b0SVineet Gupta /* 39fe6cb7b0SVineet Gupta * No Super page case 40d9820ff7SVineet Gupta * Default value provides 11:8:13 (8K), 10:10:12 (4K) 41d9820ff7SVineet Gupta * Limits imposed by pgtable_t only PAGE_SIZE long 42d9820ff7SVineet Gupta * (so 4K page can only have 1K entries: or 10 bits) 43fe6cb7b0SVineet Gupta */ 44d9820ff7SVineet Gupta #ifdef CONFIG_ARC_PAGE_SIZE_4K 45d9820ff7SVineet Gupta #define PGDIR_SHIFT 22 46d9820ff7SVineet Gupta #else 47fe6cb7b0SVineet Gupta #define PGDIR_SHIFT 21 48d9820ff7SVineet Gupta #endif 49fe6cb7b0SVineet Gupta 50fe6cb7b0SVineet Gupta #endif 51fe6cb7b0SVineet Gupta 52*2dde02abSVineet Gupta #else /* CONFIG_PGTABLE_LEVELS != 2 */ 53fe6cb7b0SVineet Gupta 54*2dde02abSVineet Gupta /* 55*2dde02abSVineet Gupta * A default 3 level paging testing setup in software walked MMU 56*2dde02abSVineet Gupta * MMUv4 (8K page): <4> : <7> : <8> : <13> 57*2dde02abSVineet Gupta */ 58*2dde02abSVineet Gupta #define PGDIR_SHIFT 28 59*2dde02abSVineet Gupta #if CONFIG_PGTABLE_LEVELS > 2 60*2dde02abSVineet Gupta #define PMD_SHIFT 21 61*2dde02abSVineet Gupta #endif 62*2dde02abSVineet Gupta 63*2dde02abSVineet Gupta #endif /* CONFIG_PGTABLE_LEVELS */ 64*2dde02abSVineet Gupta 65*2dde02abSVineet Gupta #define PGDIR_SIZE BIT(PGDIR_SHIFT) 66*2dde02abSVineet Gupta #define PGDIR_MASK (~(PGDIR_SIZE - 1)) 67fe6cb7b0SVineet Gupta #define PTRS_PER_PGD BIT(32 - PGDIR_SHIFT) 68fe6cb7b0SVineet Gupta 69*2dde02abSVineet Gupta #if CONFIG_PGTABLE_LEVELS > 2 70*2dde02abSVineet Gupta #define PMD_SIZE BIT(PMD_SHIFT) 71*2dde02abSVineet Gupta #define PMD_MASK (~(PMD_SIZE - 1)) 72*2dde02abSVineet Gupta #define PTRS_PER_PMD BIT(PGDIR_SHIFT - PMD_SHIFT) 73*2dde02abSVineet Gupta #endif 74*2dde02abSVineet Gupta 75*2dde02abSVineet Gupta #define PTRS_PER_PTE BIT(PMD_SHIFT - PAGE_SHIFT) 76fe6cb7b0SVineet Gupta 77fe6cb7b0SVineet Gupta #ifndef __ASSEMBLY__ 78fe6cb7b0SVineet Gupta 79*2dde02abSVineet Gupta #if CONFIG_PGTABLE_LEVELS > 2 80*2dde02abSVineet Gupta #include <asm-generic/pgtable-nopud.h> 81*2dde02abSVineet Gupta #else 82fe6cb7b0SVineet Gupta #include <asm-generic/pgtable-nopmd.h> 83*2dde02abSVineet Gupta #endif 84fe6cb7b0SVineet Gupta 85fe6cb7b0SVineet Gupta /* 86fe6cb7b0SVineet Gupta * 1st level paging: pgd 87fe6cb7b0SVineet Gupta */ 88fe6cb7b0SVineet Gupta #define pgd_index(addr) ((addr) >> PGDIR_SHIFT) 89fe6cb7b0SVineet Gupta #define pgd_offset(mm, addr) (((mm)->pgd) + pgd_index(addr)) 90fe6cb7b0SVineet Gupta #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) 91fe6cb7b0SVineet Gupta #define pgd_ERROR(e) \ 92fe6cb7b0SVineet Gupta pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 93fe6cb7b0SVineet Gupta 94*2dde02abSVineet Gupta #if CONFIG_PGTABLE_LEVELS > 2 95*2dde02abSVineet Gupta 96*2dde02abSVineet Gupta /* In 3 level paging, pud_* macros work on pgd */ 97*2dde02abSVineet Gupta #define pud_none(x) (!pud_val(x)) 98*2dde02abSVineet Gupta #define pud_bad(x) ((pud_val(x) & ~PAGE_MASK)) 99*2dde02abSVineet Gupta #define pud_present(x) (pud_val(x)) 100*2dde02abSVineet Gupta #define pud_clear(xp) do { pud_val(*(xp)) = 0; } while (0) 101*2dde02abSVineet Gupta #define pud_pgtable(pud) ((pmd_t *)(pud_val(pud) & PAGE_MASK)) 102*2dde02abSVineet Gupta #define pud_page(pud) virt_to_page(pud_pgtable(pud)) 103*2dde02abSVineet Gupta #define set_pud(pudp, pud) (*(pudp) = pud) 104*2dde02abSVineet Gupta 105fe6cb7b0SVineet Gupta /* 106*2dde02abSVineet Gupta * 2nd level paging: pmd 107*2dde02abSVineet Gupta */ 108*2dde02abSVineet Gupta #define pmd_ERROR(e) \ 109*2dde02abSVineet Gupta pr_crit("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) 110*2dde02abSVineet Gupta 111*2dde02abSVineet Gupta #define pmd_pfn(pmd) ((pmd_val(pmd) & PMD_MASK) >> PAGE_SHIFT) 112*2dde02abSVineet Gupta #define pfn_pmd(pfn,prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 113*2dde02abSVineet Gupta #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) 114*2dde02abSVineet Gupta 115*2dde02abSVineet Gupta #endif 116*2dde02abSVineet Gupta 117*2dde02abSVineet Gupta /* 118*2dde02abSVineet Gupta * Due to the strange way generic pgtable level folding works, the pmd_* macros 119*2dde02abSVineet Gupta * - are valid even for 2 levels (which supposedly only has pgd - pte) 120*2dde02abSVineet Gupta * - behave differently for 2 vs. 3 121*2dde02abSVineet Gupta * In 2 level paging (pgd -> pte), pmd_* macros work on pgd 122*2dde02abSVineet Gupta * In 3+ level paging (pgd -> pmd -> pte), pmd_* macros work on pmd 123fe6cb7b0SVineet Gupta */ 124fe6cb7b0SVineet Gupta #define pmd_none(x) (!pmd_val(x)) 125fe6cb7b0SVineet Gupta #define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK)) 126fe6cb7b0SVineet Gupta #define pmd_present(x) (pmd_val(x)) 127fe6cb7b0SVineet Gupta #define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0) 128fe6cb7b0SVineet Gupta #define pmd_page_vaddr(pmd) (pmd_val(pmd) & PAGE_MASK) 129fe6cb7b0SVineet Gupta #define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd)) 130fe6cb7b0SVineet Gupta #define set_pmd(pmdp, pmd) (*(pmdp) = pmd) 131fe6cb7b0SVineet Gupta #define pmd_pgtable(pmd) ((pgtable_t) pmd_page_vaddr(pmd)) 132fe6cb7b0SVineet Gupta 133*2dde02abSVineet Gupta /* 134*2dde02abSVineet Gupta * 3rd level paging: pte 135*2dde02abSVineet Gupta */ 136fe6cb7b0SVineet Gupta #define pte_ERROR(e) \ 137fe6cb7b0SVineet Gupta pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 138fe6cb7b0SVineet Gupta 139fe6cb7b0SVineet Gupta #define pte_none(x) (!pte_val(x)) 140fe6cb7b0SVineet Gupta #define pte_present(x) (pte_val(x) & _PAGE_PRESENT) 141fe6cb7b0SVineet Gupta #define pte_clear(mm,addr,ptep) set_pte_at(mm, addr, ptep, __pte(0)) 142fe6cb7b0SVineet Gupta #define pte_page(pte) pfn_to_page(pte_pfn(pte)) 143fe6cb7b0SVineet Gupta #define set_pte(ptep, pte) ((*(ptep)) = (pte)) 144fe6cb7b0SVineet Gupta #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 145fe6cb7b0SVineet Gupta #define pfn_pte(pfn, prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot)) 146fe6cb7b0SVineet Gupta #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 147fe6cb7b0SVineet Gupta 148fe6cb7b0SVineet Gupta #ifdef CONFIG_ISA_ARCV2 149fe6cb7b0SVineet Gupta #define pmd_leaf(x) (pmd_val(x) & _PAGE_HW_SZ) 150fe6cb7b0SVineet Gupta #endif 151fe6cb7b0SVineet Gupta 152fe6cb7b0SVineet Gupta #endif /* !__ASSEMBLY__ */ 153fe6cb7b0SVineet Gupta 154fe6cb7b0SVineet Gupta #endif 155