1 /* 2 * linux/arch/alpha/kernel/sys_eb64p.c 3 * 4 * Copyright (C) 1995 David A Rusling 5 * Copyright (C) 1996 Jay A Estabrook 6 * Copyright (C) 1998, 1999 Richard Henderson 7 * 8 * Code supporting the EB64+ and EB66. 9 */ 10 11 #include <linux/config.h> 12 #include <linux/kernel.h> 13 #include <linux/types.h> 14 #include <linux/mm.h> 15 #include <linux/sched.h> 16 #include <linux/pci.h> 17 #include <linux/init.h> 18 #include <linux/bitops.h> 19 20 #include <asm/ptrace.h> 21 #include <asm/system.h> 22 #include <asm/dma.h> 23 #include <asm/irq.h> 24 #include <asm/mmu_context.h> 25 #include <asm/io.h> 26 #include <asm/pgtable.h> 27 #include <asm/core_apecs.h> 28 #include <asm/core_lca.h> 29 #include <asm/hwrpb.h> 30 #include <asm/tlbflush.h> 31 32 #include "proto.h" 33 #include "irq_impl.h" 34 #include "pci_impl.h" 35 #include "machvec_impl.h" 36 37 38 /* Note mask bit is true for DISABLED irqs. */ 39 static unsigned int cached_irq_mask = -1; 40 41 static inline void 42 eb64p_update_irq_hw(unsigned int irq, unsigned long mask) 43 { 44 outb(mask >> (irq >= 24 ? 24 : 16), (irq >= 24 ? 0x27 : 0x26)); 45 } 46 47 static inline void 48 eb64p_enable_irq(unsigned int irq) 49 { 50 eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq)); 51 } 52 53 static void 54 eb64p_disable_irq(unsigned int irq) 55 { 56 eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq); 57 } 58 59 static unsigned int 60 eb64p_startup_irq(unsigned int irq) 61 { 62 eb64p_enable_irq(irq); 63 return 0; /* never anything pending */ 64 } 65 66 static void 67 eb64p_end_irq(unsigned int irq) 68 { 69 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 70 eb64p_enable_irq(irq); 71 } 72 73 static struct hw_interrupt_type eb64p_irq_type = { 74 .typename = "EB64P", 75 .startup = eb64p_startup_irq, 76 .shutdown = eb64p_disable_irq, 77 .enable = eb64p_enable_irq, 78 .disable = eb64p_disable_irq, 79 .ack = eb64p_disable_irq, 80 .end = eb64p_end_irq, 81 }; 82 83 static void 84 eb64p_device_interrupt(unsigned long vector, struct pt_regs *regs) 85 { 86 unsigned long pld; 87 unsigned int i; 88 89 /* Read the interrupt summary registers */ 90 pld = inb(0x26) | (inb(0x27) << 8); 91 92 /* 93 * Now, for every possible bit set, work through 94 * them and call the appropriate interrupt handler. 95 */ 96 while (pld) { 97 i = ffz(~pld); 98 pld &= pld - 1; /* clear least bit set */ 99 100 if (i == 5) { 101 isa_device_interrupt(vector, regs); 102 } else { 103 handle_irq(16 + i, regs); 104 } 105 } 106 } 107 108 static void __init 109 eb64p_init_irq(void) 110 { 111 long i; 112 113 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_CABRIOLET) 114 /* 115 * CABRIO SRM may not set variation correctly, so here we test 116 * the high word of the interrupt summary register for the RAZ 117 * bits, and hope that a true EB64+ would read all ones... 118 */ 119 if (inw(0x806) != 0xffff) { 120 extern struct alpha_machine_vector cabriolet_mv; 121 122 printk("Detected Cabriolet: correcting HWRPB.\n"); 123 124 hwrpb->sys_variation |= 2L << 10; 125 hwrpb_update_checksum(hwrpb); 126 127 alpha_mv = cabriolet_mv; 128 alpha_mv.init_irq(); 129 return; 130 } 131 #endif /* GENERIC */ 132 133 outb(0xff, 0x26); 134 outb(0xff, 0x27); 135 136 init_i8259a_irqs(); 137 138 for (i = 16; i < 32; ++i) { 139 irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL; 140 irq_desc[i].handler = &eb64p_irq_type; 141 } 142 143 common_init_isa_dma(); 144 setup_irq(16+5, &isa_cascade_irqaction); 145 } 146 147 /* 148 * PCI Fixup configuration. 149 * 150 * There are two 8 bit external summary registers as follows: 151 * 152 * Summary @ 0x26: 153 * Bit Meaning 154 * 0 Interrupt Line A from slot 0 155 * 1 Interrupt Line A from slot 1 156 * 2 Interrupt Line B from slot 0 157 * 3 Interrupt Line B from slot 1 158 * 4 Interrupt Line C from slot 0 159 * 5 Interrupt line from the two ISA PICs 160 * 6 Tulip 161 * 7 NCR SCSI 162 * 163 * Summary @ 0x27 164 * Bit Meaning 165 * 0 Interrupt Line C from slot 1 166 * 1 Interrupt Line D from slot 0 167 * 2 Interrupt Line D from slot 1 168 * 3 RAZ 169 * 4 RAZ 170 * 5 RAZ 171 * 6 RAZ 172 * 7 RAZ 173 * 174 * The device to slot mapping looks like: 175 * 176 * Slot Device 177 * 5 NCR SCSI controller 178 * 6 PCI on board slot 0 179 * 7 PCI on board slot 1 180 * 8 Intel SIO PCI-ISA bridge chip 181 * 9 Tulip - DECchip 21040 Ethernet controller 182 * 183 * 184 * This two layered interrupt approach means that we allocate IRQ 16 and 185 * above for PCI interrupts. The IRQ relates to which bit the interrupt 186 * comes in on. This makes interrupt processing much easier. 187 */ 188 189 static int __init 190 eb64p_map_irq(struct pci_dev *dev, u8 slot, u8 pin) 191 { 192 static char irq_tab[5][5] __initdata = { 193 /*INT INTA INTB INTC INTD */ 194 {16+7, 16+7, 16+7, 16+7, 16+7}, /* IdSel 5, slot ?, ?? */ 195 {16+0, 16+0, 16+2, 16+4, 16+9}, /* IdSel 6, slot ?, ?? */ 196 {16+1, 16+1, 16+3, 16+8, 16+10}, /* IdSel 7, slot ?, ?? */ 197 { -1, -1, -1, -1, -1}, /* IdSel 8, SIO */ 198 {16+6, 16+6, 16+6, 16+6, 16+6}, /* IdSel 9, TULIP */ 199 }; 200 const long min_idsel = 5, max_idsel = 9, irqs_per_slot = 5; 201 return COMMON_TABLE_LOOKUP; 202 } 203 204 205 /* 206 * The System Vector 207 */ 208 209 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB64P) 210 struct alpha_machine_vector eb64p_mv __initmv = { 211 .vector_name = "EB64+", 212 DO_EV4_MMU, 213 DO_DEFAULT_RTC, 214 DO_APECS_IO, 215 .machine_check = apecs_machine_check, 216 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 217 .min_io_address = DEFAULT_IO_BASE, 218 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, 219 220 .nr_irqs = 32, 221 .device_interrupt = eb64p_device_interrupt, 222 223 .init_arch = apecs_init_arch, 224 .init_irq = eb64p_init_irq, 225 .init_rtc = common_init_rtc, 226 .init_pci = common_init_pci, 227 .kill_arch = NULL, 228 .pci_map_irq = eb64p_map_irq, 229 .pci_swizzle = common_swizzle, 230 }; 231 ALIAS_MV(eb64p) 232 #endif 233 234 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EB66) 235 struct alpha_machine_vector eb66_mv __initmv = { 236 .vector_name = "EB66", 237 DO_EV4_MMU, 238 DO_DEFAULT_RTC, 239 DO_LCA_IO, 240 .machine_check = lca_machine_check, 241 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS, 242 .min_io_address = DEFAULT_IO_BASE, 243 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE, 244 245 .nr_irqs = 32, 246 .device_interrupt = eb64p_device_interrupt, 247 248 .init_arch = lca_init_arch, 249 .init_irq = eb64p_init_irq, 250 .init_rtc = common_init_rtc, 251 .init_pci = common_init_pci, 252 .pci_map_irq = eb64p_map_irq, 253 .pci_swizzle = common_swizzle, 254 }; 255 ALIAS_MV(eb66) 256 #endif 257