1*b2441318SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0 21da177e4SLinus Torvalds /* 31da177e4SLinus Torvalds * linux/arch/alpha/kernel/es1888.c 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * Init the built-in ES1888 sound chip (SB16 compatible) 61da177e4SLinus Torvalds */ 71da177e4SLinus Torvalds 81da177e4SLinus Torvalds #include <linux/init.h> 91da177e4SLinus Torvalds #include <asm/io.h> 101da177e4SLinus Torvalds #include "proto.h" 111da177e4SLinus Torvalds 121da177e4SLinus Torvalds void __init es1888_init(void)131da177e4SLinus Torvaldses1888_init(void) 141da177e4SLinus Torvalds { 151da177e4SLinus Torvalds /* Sequence of IO reads to init the audio controller */ 161da177e4SLinus Torvalds inb(0x0229); 171da177e4SLinus Torvalds inb(0x0229); 181da177e4SLinus Torvalds inb(0x0229); 191da177e4SLinus Torvalds inb(0x022b); 201da177e4SLinus Torvalds inb(0x0229); 211da177e4SLinus Torvalds inb(0x022b); 221da177e4SLinus Torvalds inb(0x0229); 231da177e4SLinus Torvalds inb(0x0229); 241da177e4SLinus Torvalds inb(0x022b); 251da177e4SLinus Torvalds inb(0x0229); 261da177e4SLinus Torvalds inb(0x0220); /* This sets the base address to 0x220 */ 271da177e4SLinus Torvalds 281da177e4SLinus Torvalds /* Sequence to set DMA channels */ 291da177e4SLinus Torvalds outb(0x01, 0x0226); /* reset */ 301da177e4SLinus Torvalds inb(0x0226); /* pause */ 311da177e4SLinus Torvalds outb(0x00, 0x0226); /* release reset */ 321da177e4SLinus Torvalds while (!(inb(0x022e) & 0x80)) /* wait for bit 7 to assert*/ 331da177e4SLinus Torvalds continue; 341da177e4SLinus Torvalds inb(0x022a); /* pause */ 351da177e4SLinus Torvalds outb(0xc6, 0x022c); /* enable extended mode */ 361da177e4SLinus Torvalds inb(0x022a); /* pause, also forces the write */ 371da177e4SLinus Torvalds while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ 381da177e4SLinus Torvalds continue; 391da177e4SLinus Torvalds outb(0xb1, 0x022c); /* setup for write to Interrupt CR */ 401da177e4SLinus Torvalds while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ 411da177e4SLinus Torvalds continue; 421da177e4SLinus Torvalds outb(0x14, 0x022c); /* set IRQ 5 */ 431da177e4SLinus Torvalds while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ 441da177e4SLinus Torvalds continue; 451da177e4SLinus Torvalds outb(0xb2, 0x022c); /* setup for write to DMA CR */ 461da177e4SLinus Torvalds while (inb(0x022c) & 0x80) /* wait for bit 7 to deassert */ 471da177e4SLinus Torvalds continue; 481da177e4SLinus Torvalds outb(0x18, 0x022c); /* set DMA channel 1 */ 491da177e4SLinus Torvalds inb(0x022c); /* force the write */ 501da177e4SLinus Torvalds } 51