xref: /openbmc/linux/Documentation/scsi/aic79xx.rst (revision ead5d1f4d877e92c051e1a1ade623d0d30e71619)
1*520a44d4SMauro Carvalho Chehab.. SPDX-License-Identifier: GPL-2.0
2*520a44d4SMauro Carvalho Chehab.. include:: <isonum.txt>
3*520a44d4SMauro Carvalho Chehab
4*520a44d4SMauro Carvalho Chehab===================================
5*520a44d4SMauro Carvalho ChehabAdaptec Ultra320 Family Manager Set
6*520a44d4SMauro Carvalho Chehab===================================
7*520a44d4SMauro Carvalho Chehab
8*520a44d4SMauro Carvalho ChehabREADME for The Linux Operating System
9*520a44d4SMauro Carvalho Chehab
10*520a44d4SMauro Carvalho Chehab.. The following information is available in this file:
11*520a44d4SMauro Carvalho Chehab
12*520a44d4SMauro Carvalho Chehab  1. Supported Hardware
13*520a44d4SMauro Carvalho Chehab  2. Version History
14*520a44d4SMauro Carvalho Chehab  3. Command Line Options
15*520a44d4SMauro Carvalho Chehab  4. Additional Notes
16*520a44d4SMauro Carvalho Chehab  5. Contacting Adaptec
17*520a44d4SMauro Carvalho Chehab
18*520a44d4SMauro Carvalho Chehab
19*520a44d4SMauro Carvalho Chehab1. Supported Hardware
20*520a44d4SMauro Carvalho Chehab=====================
21*520a44d4SMauro Carvalho Chehab
22*520a44d4SMauro Carvalho Chehab   The following Adaptec SCSI Host Adapters are supported by this
23*520a44d4SMauro Carvalho Chehab   driver set.
24*520a44d4SMauro Carvalho Chehab
25*520a44d4SMauro Carvalho Chehab   =============              =========================================
26*520a44d4SMauro Carvalho Chehab   Ultra320 ASIC              Description
27*520a44d4SMauro Carvalho Chehab   =============              =========================================
28*520a44d4SMauro Carvalho Chehab   AIC-7901A                  Single Channel 64-bit PCI-X 133MHz to
29*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI ASIC
30*520a44d4SMauro Carvalho Chehab   AIC-7901B                  Single Channel 64-bit PCI-X 133MHz to
31*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI ASIC with Retained Training
32*520a44d4SMauro Carvalho Chehab   AIC-7902A4                 Dual Channel 64-bit PCI-X 133MHz to
33*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI ASIC
34*520a44d4SMauro Carvalho Chehab   AIC-7902B                  Dual Channel 64-bit PCI-X 133MHz to
35*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI ASIC with Retained Training
36*520a44d4SMauro Carvalho Chehab   =============              =========================================
37*520a44d4SMauro Carvalho Chehab
38*520a44d4SMauro Carvalho Chehab   ========================== ===================================== ============
39*520a44d4SMauro Carvalho Chehab   Ultra320 Adapters          Description                              ASIC
40*520a44d4SMauro Carvalho Chehab   ========================== ===================================== ============
41*520a44d4SMauro Carvalho Chehab   Adaptec SCSI Card 39320    Dual Channel 64-bit PCI-X 133MHz to   7902A4/7902B
42*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI Card (one external
43*520a44d4SMauro Carvalho Chehab                              68-pin, two internal 68-pin)
44*520a44d4SMauro Carvalho Chehab   Adaptec SCSI Card 39320A   Dual Channel 64-bit PCI-X 133MHz to      7902B
45*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI Card (one external
46*520a44d4SMauro Carvalho Chehab                              68-pin, two internal 68-pin)
47*520a44d4SMauro Carvalho Chehab   Adaptec SCSI Card 39320D   Dual Channel 64-bit PCI-X 133MHz to      7902A4
48*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI Card (two external VHDC
49*520a44d4SMauro Carvalho Chehab                              and one internal 68-pin)
50*520a44d4SMauro Carvalho Chehab   Adaptec SCSI Card 39320D   Dual Channel 64-bit PCI-X 133MHz to      7902A4
51*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI Card (two external VHDC
52*520a44d4SMauro Carvalho Chehab                              and one internal 68-pin) based on the
53*520a44d4SMauro Carvalho Chehab                              AIC-7902B ASIC
54*520a44d4SMauro Carvalho Chehab   Adaptec SCSI Card 29320    Single Channel 64-bit PCI-X 133MHz to    7901A
55*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI Card (one external
56*520a44d4SMauro Carvalho Chehab                              68-pin, two internal 68-pin, one
57*520a44d4SMauro Carvalho Chehab                              internal 50-pin)
58*520a44d4SMauro Carvalho Chehab   Adaptec SCSI Card 29320A   Single Channel 64-bit PCI-X 133MHz to    7901B
59*520a44d4SMauro Carvalho Chehab                              Ultra320 SCSI Card (one external
60*520a44d4SMauro Carvalho Chehab                              68-pin, two internal 68-pin, one
61*520a44d4SMauro Carvalho Chehab                              internal 50-pin)
62*520a44d4SMauro Carvalho Chehab   Adaptec SCSI Card 29320LP  Single Channel 64-bit Low Profile        7901A
63*520a44d4SMauro Carvalho Chehab                              PCI-X 133MHz to Ultra320 SCSI Card
64*520a44d4SMauro Carvalho Chehab                              (One external VHDC, one internal
65*520a44d4SMauro Carvalho Chehab                              68-pin)
66*520a44d4SMauro Carvalho Chehab   Adaptec SCSI Card 29320ALP Single Channel 64-bit Low Profile        7901B
67*520a44d4SMauro Carvalho Chehab                              PCI-X 133MHz to Ultra320 SCSI Card
68*520a44d4SMauro Carvalho Chehab                              (One external VHDC, one internal
69*520a44d4SMauro Carvalho Chehab                              68-pin)
70*520a44d4SMauro Carvalho Chehab   ========================== ===================================== ============
71*520a44d4SMauro Carvalho Chehab
72*520a44d4SMauro Carvalho Chehab2. Version History
73*520a44d4SMauro Carvalho Chehab==================
74*520a44d4SMauro Carvalho Chehab
75*520a44d4SMauro Carvalho Chehab
76*520a44d4SMauro Carvalho Chehab * 3.0	  (December 1st, 2005)
77*520a44d4SMauro Carvalho Chehab	- Updated driver to use SCSI transport class infrastructure
78*520a44d4SMauro Carvalho Chehab	- Upported sequencer and core fixes from adaptec released
79*520a44d4SMauro Carvalho Chehab	  version 2.0.15 of the driver.
80*520a44d4SMauro Carvalho Chehab
81*520a44d4SMauro Carvalho Chehab * 1.3.11 (July 11, 2003)
82*520a44d4SMauro Carvalho Chehab        - Fix several deadlock issues.
83*520a44d4SMauro Carvalho Chehab        - Add 29320ALP and 39320B Id's.
84*520a44d4SMauro Carvalho Chehab
85*520a44d4SMauro Carvalho Chehab * 1.3.10 (June 3rd, 2003)
86*520a44d4SMauro Carvalho Chehab        - Align the SCB_TAG field on a 16byte boundary.  This avoids
87*520a44d4SMauro Carvalho Chehab          SCB corruption on some PCI-33 busses.
88*520a44d4SMauro Carvalho Chehab        - Correct non-zero luns on Rev B. hardware.
89*520a44d4SMauro Carvalho Chehab        - Update for change in 2.5.X SCSI proc FS interface.
90*520a44d4SMauro Carvalho Chehab        - When negotiation async via an 8bit WDTR message, send
91*520a44d4SMauro Carvalho Chehab          an SDTR with an offset of 0 to be sure the target
92*520a44d4SMauro Carvalho Chehab          knows we are async.  This works around a firmware defect
93*520a44d4SMauro Carvalho Chehab          in the Quantum Atlas 10K.
94*520a44d4SMauro Carvalho Chehab        - Implement controller suspend and resume.
95*520a44d4SMauro Carvalho Chehab        - Clear PCI error state during driver attach so that we
96*520a44d4SMauro Carvalho Chehab          don't disable memory mapped I/O due to a stray write
97*520a44d4SMauro Carvalho Chehab          by some other driver probe that occurred before we
98*520a44d4SMauro Carvalho Chehab          claimed the controller.
99*520a44d4SMauro Carvalho Chehab
100*520a44d4SMauro Carvalho Chehab * 1.3.9 (May 22nd, 2003)
101*520a44d4SMauro Carvalho Chehab        - Fix compiler errors.
102*520a44d4SMauro Carvalho Chehab        - Remove S/G splitting for segments that cross a 4GB boundary.
103*520a44d4SMauro Carvalho Chehab          This is guaranteed not to happen in Linux.
104*520a44d4SMauro Carvalho Chehab        - Add support for scsi_report_device_reset() found in
105*520a44d4SMauro Carvalho Chehab          2.5.X kernels.
106*520a44d4SMauro Carvalho Chehab        - Add 7901B support.
107*520a44d4SMauro Carvalho Chehab        - Simplify handling of the packetized lun Rev A workaround.
108*520a44d4SMauro Carvalho Chehab        - Correct and simplify handling of the ignore wide residue
109*520a44d4SMauro Carvalho Chehab          message.  The previous code would fail to report a residual
110*520a44d4SMauro Carvalho Chehab          if the transaction data length was even and we received
111*520a44d4SMauro Carvalho Chehab          an IWR message.
112*520a44d4SMauro Carvalho Chehab
113*520a44d4SMauro Carvalho Chehab * 1.3.8 (April 29th, 2003)
114*520a44d4SMauro Carvalho Chehab        - Fix types accessed via the command line interface code.
115*520a44d4SMauro Carvalho Chehab        - Perform a few firmware optimizations.
116*520a44d4SMauro Carvalho Chehab        - Fix "Unexpected PKT busfree" errors.
117*520a44d4SMauro Carvalho Chehab        - Use a sequencer interrupt to notify the host of
118*520a44d4SMauro Carvalho Chehab          commands with bad status.  We defer the notification
119*520a44d4SMauro Carvalho Chehab          until there are no outstanding selections to ensure
120*520a44d4SMauro Carvalho Chehab          that the host is interrupted for as short a time as
121*520a44d4SMauro Carvalho Chehab          possible.
122*520a44d4SMauro Carvalho Chehab        - Remove pre-2.2.X support.
123*520a44d4SMauro Carvalho Chehab        - Add support for new 2.5.X interrupt API.
124*520a44d4SMauro Carvalho Chehab        - Correct big-endian architecture support.
125*520a44d4SMauro Carvalho Chehab
126*520a44d4SMauro Carvalho Chehab * 1.3.7 (April 16th, 2003)
127*520a44d4SMauro Carvalho Chehab        - Use del_timer_sync() to ensure that no timeouts
128*520a44d4SMauro Carvalho Chehab          are pending during controller shutdown.
129*520a44d4SMauro Carvalho Chehab        - For pre-2.5.X kernels, carefully adjust our segment
130*520a44d4SMauro Carvalho Chehab          list size to avoid SCSI malloc pool fragmentation.
131*520a44d4SMauro Carvalho Chehab        - Cleanup channel display in our /proc output.
132*520a44d4SMauro Carvalho Chehab        - Workaround duplicate device entries in the mid-layer
133*520a44d4SMauro Carvalho Chehab          device list during add-single-device.
134*520a44d4SMauro Carvalho Chehab
135*520a44d4SMauro Carvalho Chehab * 1.3.6 (March 28th, 2003)
136*520a44d4SMauro Carvalho Chehab        - Correct a double free in the Domain Validation code.
137*520a44d4SMauro Carvalho Chehab        - Correct a reference to free'ed memory during controller
138*520a44d4SMauro Carvalho Chehab          shutdown.
139*520a44d4SMauro Carvalho Chehab        - Reset the bus on an SE->LVD change.  This is required
140*520a44d4SMauro Carvalho Chehab          to reset our transceivers.
141*520a44d4SMauro Carvalho Chehab
142*520a44d4SMauro Carvalho Chehab * 1.3.5 (March 24th, 2003)
143*520a44d4SMauro Carvalho Chehab        - Fix a few register window mode bugs.
144*520a44d4SMauro Carvalho Chehab        - Include read streaming in the PPR flags we display in
145*520a44d4SMauro Carvalho Chehab          diagnostics as well as /proc.
146*520a44d4SMauro Carvalho Chehab        - Add PCI hot plug support for 2.5.X kernels.
147*520a44d4SMauro Carvalho Chehab        - Correct default precompensation value for RevA hardware.
148*520a44d4SMauro Carvalho Chehab        - Fix Domain Validation thread shutdown.
149*520a44d4SMauro Carvalho Chehab        - Add a firmware workaround to make the LED blink
150*520a44d4SMauro Carvalho Chehab          brighter during packetized operations on the H2A4.
151*520a44d4SMauro Carvalho Chehab        - Correct /proc display of user read streaming settings.
152*520a44d4SMauro Carvalho Chehab        - Simplify driver locking by releasing the io_request_lock
153*520a44d4SMauro Carvalho Chehab          upon driver entry from the mid-layer.
154*520a44d4SMauro Carvalho Chehab        - Cleanup command line parsing and move much of this code
155*520a44d4SMauro Carvalho Chehab          to aiclib.
156*520a44d4SMauro Carvalho Chehab
157*520a44d4SMauro Carvalho Chehab * 1.3.4 (February 28th, 2003)
158*520a44d4SMauro Carvalho Chehab        - Correct a race condition in our error recovery handler.
159*520a44d4SMauro Carvalho Chehab        - Allow Test Unit Ready commands to take a full 5 seconds
160*520a44d4SMauro Carvalho Chehab          during Domain Validation.
161*520a44d4SMauro Carvalho Chehab
162*520a44d4SMauro Carvalho Chehab * 1.3.2 (February 19th, 2003)
163*520a44d4SMauro Carvalho Chehab        - Correct a Rev B. regression due to the GEM318
164*520a44d4SMauro Carvalho Chehab          compatibility fix included in 1.3.1.
165*520a44d4SMauro Carvalho Chehab
166*520a44d4SMauro Carvalho Chehab * 1.3.1 (February 11th, 2003)
167*520a44d4SMauro Carvalho Chehab        - Add support for the 39320A.
168*520a44d4SMauro Carvalho Chehab        - Improve recovery for certain PCI-X errors.
169*520a44d4SMauro Carvalho Chehab        - Fix handling of LQ/DATA/LQ/DATA for the
170*520a44d4SMauro Carvalho Chehab          same write transaction that can occur without
171*520a44d4SMauro Carvalho Chehab          interveining training.
172*520a44d4SMauro Carvalho Chehab        - Correct compatibility issues with the GEM318
173*520a44d4SMauro Carvalho Chehab          enclosure services device.
174*520a44d4SMauro Carvalho Chehab        - Correct data corruption issue that occurred under
175*520a44d4SMauro Carvalho Chehab          high tag depth write loads.
176*520a44d4SMauro Carvalho Chehab        - Adapt to a change in the 2.5.X daemonize() API.
177*520a44d4SMauro Carvalho Chehab        - Correct a "Missing case in ahd_handle_scsiint" panic.
178*520a44d4SMauro Carvalho Chehab
179*520a44d4SMauro Carvalho Chehab * 1.3.0 (January 21st, 2003)
180*520a44d4SMauro Carvalho Chehab        - Full regression testing for all U320 products completed.
181*520a44d4SMauro Carvalho Chehab        - Added abort and target/lun reset error recovery handler and
182*520a44d4SMauro Carvalho Chehab          interrupt coalescing.
183*520a44d4SMauro Carvalho Chehab
184*520a44d4SMauro Carvalho Chehab * 1.2.0 (November 14th, 2002)
185*520a44d4SMauro Carvalho Chehab        - Added support for Domain Validation
186*520a44d4SMauro Carvalho Chehab        - Add support for the Hewlett-Packard version of the 39320D
187*520a44d4SMauro Carvalho Chehab          and AIC-7902 adapters.
188*520a44d4SMauro Carvalho Chehab
189*520a44d4SMauro Carvalho Chehab        Support for previous adapters has not been fully tested and should
190*520a44d4SMauro Carvalho Chehab        only be used at the customer's own risk.
191*520a44d4SMauro Carvalho Chehab
192*520a44d4SMauro Carvalho Chehab * 1.1.1 (September 24th, 2002)
193*520a44d4SMauro Carvalho Chehab        - Added support for the Linux 2.5.X kernel series
194*520a44d4SMauro Carvalho Chehab
195*520a44d4SMauro Carvalho Chehab * 1.1.0 (September 17th, 2002)
196*520a44d4SMauro Carvalho Chehab        - Added support for four additional SCSI products:
197*520a44d4SMauro Carvalho Chehab          ASC-39320, ASC-29320, ASC-29320LP, AIC-7901.
198*520a44d4SMauro Carvalho Chehab
199*520a44d4SMauro Carvalho Chehab * 1.0.0 (May 30th, 2002)
200*520a44d4SMauro Carvalho Chehab        - Initial driver release.
201*520a44d4SMauro Carvalho Chehab
202*520a44d4SMauro Carvalho Chehab * 2.1. Software/Hardware Features
203*520a44d4SMauro Carvalho Chehab        - Support for the SPI-4 "Ultra320" standard:
204*520a44d4SMauro Carvalho Chehab          - 320MB/s transfer rates
205*520a44d4SMauro Carvalho Chehab          - Packetized SCSI Protocol at 160MB/s and 320MB/s
206*520a44d4SMauro Carvalho Chehab          - Quick Arbitration Selection (QAS)
207*520a44d4SMauro Carvalho Chehab          - Retained Training Information (Rev B. ASIC only)
208*520a44d4SMauro Carvalho Chehab        - Interrupt Coalescing
209*520a44d4SMauro Carvalho Chehab        - Initiator Mode (target mode not currently
210*520a44d4SMauro Carvalho Chehab          supported)
211*520a44d4SMauro Carvalho Chehab        - Support for the PCI-X standard up to 133MHz
212*520a44d4SMauro Carvalho Chehab        - Support for the PCI v2.2 standard
213*520a44d4SMauro Carvalho Chehab        - Domain Validation
214*520a44d4SMauro Carvalho Chehab
215*520a44d4SMauro Carvalho Chehab * 2.2. Operating System Support:
216*520a44d4SMauro Carvalho Chehab        - Redhat Linux 7.2, 7.3, 8.0, Advanced Server 2.1
217*520a44d4SMauro Carvalho Chehab        - SuSE Linux 7.3, 8.0, 8.1, Enterprise Server 7
218*520a44d4SMauro Carvalho Chehab        - only Intel and AMD x86 supported at this time
219*520a44d4SMauro Carvalho Chehab        - >4GB memory configurations supported.
220*520a44d4SMauro Carvalho Chehab
221*520a44d4SMauro Carvalho Chehab     Refer to the User's Guide for more details on this.
222*520a44d4SMauro Carvalho Chehab
223*520a44d4SMauro Carvalho Chehab3. Command Line Options
224*520a44d4SMauro Carvalho Chehab=======================
225*520a44d4SMauro Carvalho Chehab
226*520a44d4SMauro Carvalho Chehab    .. Warning::
227*520a44d4SMauro Carvalho Chehab
228*520a44d4SMauro Carvalho Chehab	         ALTERING OR ADDING THESE DRIVER PARAMETERS
229*520a44d4SMauro Carvalho Chehab                 INCORRECTLY CAN RENDER YOUR SYSTEM INOPERABLE.
230*520a44d4SMauro Carvalho Chehab                 USE THEM WITH CAUTION.
231*520a44d4SMauro Carvalho Chehab
232*520a44d4SMauro Carvalho Chehab   Put a .conf file in the /etc/modprobe.d/ directory and add/edit a
233*520a44d4SMauro Carvalho Chehab   line containing ``options aic79xx aic79xx=[command[,command...]]`` where
234*520a44d4SMauro Carvalho Chehab   ``command`` is one or more of the following:
235*520a44d4SMauro Carvalho Chehab
236*520a44d4SMauro Carvalho Chehab
237*520a44d4SMauro Carvalho Chehabverbose
238*520a44d4SMauro Carvalho Chehab    :Definition: enable additional informative messages during driver operation.
239*520a44d4SMauro Carvalho Chehab    :Possible Values: This option is a flag
240*520a44d4SMauro Carvalho Chehab    :Default Value: disabled
241*520a44d4SMauro Carvalho Chehab
242*520a44d4SMauro Carvalho Chehabdebug:[value]
243*520a44d4SMauro Carvalho Chehab    :Definition: Enables various levels of debugging information
244*520a44d4SMauro Carvalho Chehab                 The bit definitions for the debugging mask can
245*520a44d4SMauro Carvalho Chehab                 be found in drivers/scsi/aic7xxx/aic79xx.h under
246*520a44d4SMauro Carvalho Chehab                 the "Debug" heading.
247*520a44d4SMauro Carvalho Chehab    :Possible Values: 0x0000 = no debugging, 0xffff = full debugging
248*520a44d4SMauro Carvalho Chehab    :Default Value: 0x0000
249*520a44d4SMauro Carvalho Chehab
250*520a44d4SMauro Carvalho Chehabno_reset
251*520a44d4SMauro Carvalho Chehab    :Definition: Do not reset the bus during the initial probe
252*520a44d4SMauro Carvalho Chehab                 phase
253*520a44d4SMauro Carvalho Chehab    :Possible Values: This option is a flag
254*520a44d4SMauro Carvalho Chehab    :Default Value: disabled
255*520a44d4SMauro Carvalho Chehab
256*520a44d4SMauro Carvalho Chehabextended
257*520a44d4SMauro Carvalho Chehab    :Definition: Force extended translation on the controller
258*520a44d4SMauro Carvalho Chehab    :Possible Values: This option is a flag
259*520a44d4SMauro Carvalho Chehab    :Default Value: disabled
260*520a44d4SMauro Carvalho Chehab
261*520a44d4SMauro Carvalho Chehabperiodic_otag
262*520a44d4SMauro Carvalho Chehab    :Definition: Send an ordered tag periodically to prevent
263*520a44d4SMauro Carvalho Chehab                 tag starvation.  Needed for some older devices
264*520a44d4SMauro Carvalho Chehab    :Possible Values: This option is a flag
265*520a44d4SMauro Carvalho Chehab    :Default Value: disabled
266*520a44d4SMauro Carvalho Chehab
267*520a44d4SMauro Carvalho Chehabreverse_scan
268*520a44d4SMauro Carvalho Chehab    :Definition: Probe the scsi bus in reverse order, starting with target 15
269*520a44d4SMauro Carvalho Chehab    :Possible Values: This option is a flag
270*520a44d4SMauro Carvalho Chehab    :Default Value: disabled
271*520a44d4SMauro Carvalho Chehab
272*520a44d4SMauro Carvalho Chehabglobal_tag_depth
273*520a44d4SMauro Carvalho Chehab    :Definition: Global tag depth for all targets on all busses.
274*520a44d4SMauro Carvalho Chehab		 This option sets the default tag depth which
275*520a44d4SMauro Carvalho Chehab		 may be selectively overridden vi the tag_info
276*520a44d4SMauro Carvalho Chehab		 option.
277*520a44d4SMauro Carvalho Chehab
278*520a44d4SMauro Carvalho Chehab    :Possible Values: 1 - 253
279*520a44d4SMauro Carvalho Chehab    :Default Value: 32
280*520a44d4SMauro Carvalho Chehab
281*520a44d4SMauro Carvalho Chehabtag_info:{{value[,value...]}[,{value[,value...]}...]}
282*520a44d4SMauro Carvalho Chehab    :Definition: Set the per-target tagged queue depth on a
283*520a44d4SMauro Carvalho Chehab                 per controller basis.  Both controllers and targets
284*520a44d4SMauro Carvalho Chehab                 may be omitted indicating that they should retain
285*520a44d4SMauro Carvalho Chehab                 the default tag depth.
286*520a44d4SMauro Carvalho Chehab
287*520a44d4SMauro Carvalho Chehab    :Possible Values: 1 - 253
288*520a44d4SMauro Carvalho Chehab    :Default Value: 32
289*520a44d4SMauro Carvalho Chehab
290*520a44d4SMauro Carvalho Chehab    Examples:
291*520a44d4SMauro Carvalho Chehab
292*520a44d4SMauro Carvalho Chehab
293*520a44d4SMauro Carvalho Chehab	::
294*520a44d4SMauro Carvalho Chehab
295*520a44d4SMauro Carvalho Chehab	    tag_info:{{16,32,32,64,8,8,,32,32,32,32,32,32,32,32,32}
296*520a44d4SMauro Carvalho Chehab
297*520a44d4SMauro Carvalho Chehab	On Controller 0
298*520a44d4SMauro Carvalho Chehab
299*520a44d4SMauro Carvalho Chehab	    - specifies a tag depth of 16 for target 0
300*520a44d4SMauro Carvalho Chehab	    - specifies a tag depth of 64 for target 3
301*520a44d4SMauro Carvalho Chehab	    - specifies a tag depth of 8 for targets 4 and 5
302*520a44d4SMauro Carvalho Chehab	    - leaves target 6 at the default
303*520a44d4SMauro Carvalho Chehab	    - specifies a tag depth of 32 for targets 1,2,7-15
304*520a44d4SMauro Carvalho Chehab
305*520a44d4SMauro Carvalho Chehab	All other targets retain the default depth.
306*520a44d4SMauro Carvalho Chehab
307*520a44d4SMauro Carvalho Chehab	::
308*520a44d4SMauro Carvalho Chehab
309*520a44d4SMauro Carvalho Chehab	    tag_info:{{},{32,,32}}
310*520a44d4SMauro Carvalho Chehab
311*520a44d4SMauro Carvalho Chehab	On Controller 1
312*520a44d4SMauro Carvalho Chehab
313*520a44d4SMauro Carvalho Chehab	    - specifies a tag depth of 32 for targets 0 and 2
314*520a44d4SMauro Carvalho Chehab
315*520a44d4SMauro Carvalho Chehab	All other targets retain the default depth.
316*520a44d4SMauro Carvalho Chehab
317*520a44d4SMauro Carvalho Chehab
318*520a44d4SMauro Carvalho Chehabrd_strm: {rd_strm_bitmask[,rd_strm_bitmask...]}
319*520a44d4SMauro Carvalho Chehab    :Definition: Enable read streaming on a per target basis.
320*520a44d4SMauro Carvalho Chehab		 The rd_strm_bitmask is a 16 bit hex value in which
321*520a44d4SMauro Carvalho Chehab		 each bit represents a target.  Setting the target's
322*520a44d4SMauro Carvalho Chehab		 bit to '1' enables read streaming for that
323*520a44d4SMauro Carvalho Chehab		 target.  Controllers may be omitted indicating that
324*520a44d4SMauro Carvalho Chehab		 they should retain the default read streaming setting.
325*520a44d4SMauro Carvalho Chehab
326*520a44d4SMauro Carvalho Chehab    Examples:
327*520a44d4SMauro Carvalho Chehab
328*520a44d4SMauro Carvalho Chehab	    ::
329*520a44d4SMauro Carvalho Chehab
330*520a44d4SMauro Carvalho Chehab		rd_strm:{0x0041}
331*520a44d4SMauro Carvalho Chehab
332*520a44d4SMauro Carvalho Chehab	    On Controller 0
333*520a44d4SMauro Carvalho Chehab
334*520a44d4SMauro Carvalho Chehab		- enables read streaming for targets 0 and 6.
335*520a44d4SMauro Carvalho Chehab		- disables read streaming for targets 1-5,7-15.
336*520a44d4SMauro Carvalho Chehab
337*520a44d4SMauro Carvalho Chehab	    All other targets retain the default read
338*520a44d4SMauro Carvalho Chehab	    streaming setting.
339*520a44d4SMauro Carvalho Chehab
340*520a44d4SMauro Carvalho Chehab	    ::
341*520a44d4SMauro Carvalho Chehab
342*520a44d4SMauro Carvalho Chehab		rd_strm:{0x0023,,0xFFFF}
343*520a44d4SMauro Carvalho Chehab
344*520a44d4SMauro Carvalho Chehab	    On Controller 0
345*520a44d4SMauro Carvalho Chehab
346*520a44d4SMauro Carvalho Chehab		- enables read streaming for targets 1,2, and 5.
347*520a44d4SMauro Carvalho Chehab		- disables read streaming for targets 3,4,6-15.
348*520a44d4SMauro Carvalho Chehab
349*520a44d4SMauro Carvalho Chehab	    On Controller 2
350*520a44d4SMauro Carvalho Chehab
351*520a44d4SMauro Carvalho Chehab		- enables read streaming for all targets.
352*520a44d4SMauro Carvalho Chehab
353*520a44d4SMauro Carvalho Chehab	    All other targets retain the default read
354*520a44d4SMauro Carvalho Chehab	    streaming setting.
355*520a44d4SMauro Carvalho Chehab
356*520a44d4SMauro Carvalho Chehab    :Possible Values: 0x0000 - 0xffff
357*520a44d4SMauro Carvalho Chehab    :Default Value: 0x0000
358*520a44d4SMauro Carvalho Chehab
359*520a44d4SMauro Carvalho Chehabdv: {value[,value...]}
360*520a44d4SMauro Carvalho Chehab    :Definition: Set Domain Validation Policy on a per-controller basis.
361*520a44d4SMauro Carvalho Chehab                 Controllers may be omitted indicating that
362*520a44d4SMauro Carvalho Chehab                 they should retain the default read streaming setting.
363*520a44d4SMauro Carvalho Chehab
364*520a44d4SMauro Carvalho Chehab     :Possible Values:
365*520a44d4SMauro Carvalho Chehab
366*520a44d4SMauro Carvalho Chehab		      ==== ===============================
367*520a44d4SMauro Carvalho Chehab		       < 0 Use setting from serial EEPROM.
368*520a44d4SMauro Carvalho Chehab                         0 Disable DV
369*520a44d4SMauro Carvalho Chehab		       > 0 Enable DV
370*520a44d4SMauro Carvalho Chehab		      ==== ===============================
371*520a44d4SMauro Carvalho Chehab
372*520a44d4SMauro Carvalho Chehab    :Default Value: DV Serial EEPROM configuration setting.
373*520a44d4SMauro Carvalho Chehab
374*520a44d4SMauro Carvalho Chehab    Example:
375*520a44d4SMauro Carvalho Chehab
376*520a44d4SMauro Carvalho Chehab	::
377*520a44d4SMauro Carvalho Chehab
378*520a44d4SMauro Carvalho Chehab	    dv:{-1,0,,1,1,0}
379*520a44d4SMauro Carvalho Chehab
380*520a44d4SMauro Carvalho Chehab	- On Controller 0 leave DV at its default setting.
381*520a44d4SMauro Carvalho Chehab	- On Controller 1 disable DV.
382*520a44d4SMauro Carvalho Chehab	- Skip configuration on Controller 2.
383*520a44d4SMauro Carvalho Chehab	- On Controllers 3 and 4 enable DV.
384*520a44d4SMauro Carvalho Chehab	- On Controller 5 disable DV.
385*520a44d4SMauro Carvalho Chehab
386*520a44d4SMauro Carvalho Chehabseltime:[value]
387*520a44d4SMauro Carvalho Chehab    :Definition: Specifies the selection timeout value
388*520a44d4SMauro Carvalho Chehab    :Possible Values: 0 = 256ms, 1 = 128ms, 2 = 64ms, 3 = 32ms
389*520a44d4SMauro Carvalho Chehab    :Default Value: 0
390*520a44d4SMauro Carvalho Chehab
391*520a44d4SMauro Carvalho Chehab.. Warning:
392*520a44d4SMauro Carvalho Chehab
393*520a44d4SMauro Carvalho Chehab    The following three options should only be changed at
394*520a44d4SMauro Carvalho Chehab    the direction of a technical support representative.
395*520a44d4SMauro Carvalho Chehab
396*520a44d4SMauro Carvalho Chehab
397*520a44d4SMauro Carvalho Chehabprecomp: {value[,value...]}
398*520a44d4SMauro Carvalho Chehab    :Definition: Set IO Cell precompensation value on a per-controller basis.
399*520a44d4SMauro Carvalho Chehab                 Controllers may be omitted indicating that
400*520a44d4SMauro Carvalho Chehab                 they should retain the default precompensation setting.
401*520a44d4SMauro Carvalho Chehab
402*520a44d4SMauro Carvalho Chehab    :Possible Values: 0 - 7
403*520a44d4SMauro Carvalho Chehab    :Default Value: Varies based on chip revision
404*520a44d4SMauro Carvalho Chehab
405*520a44d4SMauro Carvalho Chehab    Examples:
406*520a44d4SMauro Carvalho Chehab
407*520a44d4SMauro Carvalho Chehab	::
408*520a44d4SMauro Carvalho Chehab
409*520a44d4SMauro Carvalho Chehab	    precomp:{0x1}
410*520a44d4SMauro Carvalho Chehab
411*520a44d4SMauro Carvalho Chehab	On Controller 0 set precompensation to 1.
412*520a44d4SMauro Carvalho Chehab
413*520a44d4SMauro Carvalho Chehab	::
414*520a44d4SMauro Carvalho Chehab
415*520a44d4SMauro Carvalho Chehab	    precomp:{1,,7}
416*520a44d4SMauro Carvalho Chehab
417*520a44d4SMauro Carvalho Chehab	- On Controller 0 set precompensation to 1.
418*520a44d4SMauro Carvalho Chehab	- On Controller 2 set precompensation to 8.
419*520a44d4SMauro Carvalho Chehab
420*520a44d4SMauro Carvalho Chehabslewrate: {value[,value...]}
421*520a44d4SMauro Carvalho Chehab    :Definition: Set IO Cell slew rate on a per-controller basis.
422*520a44d4SMauro Carvalho Chehab                      Controllers may be omitted indicating that
423*520a44d4SMauro Carvalho Chehab                      they should retain the default slew rate setting.
424*520a44d4SMauro Carvalho Chehab
425*520a44d4SMauro Carvalho Chehab    :Possible Values: 0 - 15
426*520a44d4SMauro Carvalho Chehab    :Default Value: Varies based on chip revision
427*520a44d4SMauro Carvalho Chehab
428*520a44d4SMauro Carvalho Chehab    Examples:
429*520a44d4SMauro Carvalho Chehab
430*520a44d4SMauro Carvalho Chehab	::
431*520a44d4SMauro Carvalho Chehab
432*520a44d4SMauro Carvalho Chehab	    slewrate:{0x1}
433*520a44d4SMauro Carvalho Chehab
434*520a44d4SMauro Carvalho Chehab	- On Controller 0 set slew rate to 1.
435*520a44d4SMauro Carvalho Chehab
436*520a44d4SMauro Carvalho Chehab	::
437*520a44d4SMauro Carvalho Chehab
438*520a44d4SMauro Carvalho Chehab	    slewrate :{1,,8}
439*520a44d4SMauro Carvalho Chehab
440*520a44d4SMauro Carvalho Chehab	- On Controller 0 set slew rate to 1.
441*520a44d4SMauro Carvalho Chehab	- On Controller 2 set slew rate to 8.
442*520a44d4SMauro Carvalho Chehab
443*520a44d4SMauro Carvalho Chehabamplitude: {value[,value...]}
444*520a44d4SMauro Carvalho Chehab    :Definition: Set IO Cell signal amplitude on a per-controller basis.
445*520a44d4SMauro Carvalho Chehab                 Controllers may be omitted indicating that
446*520a44d4SMauro Carvalho Chehab                 they should retain the default read streaming setting.
447*520a44d4SMauro Carvalho Chehab
448*520a44d4SMauro Carvalho Chehab    :Possible Values: 1 - 7
449*520a44d4SMauro Carvalho Chehab    :Default Value: Varies based on chip revision
450*520a44d4SMauro Carvalho Chehab
451*520a44d4SMauro Carvalho Chehab    Examples:
452*520a44d4SMauro Carvalho Chehab
453*520a44d4SMauro Carvalho Chehab    ::
454*520a44d4SMauro Carvalho Chehab
455*520a44d4SMauro Carvalho Chehab	amplitude:{0x1}
456*520a44d4SMauro Carvalho Chehab
457*520a44d4SMauro Carvalho Chehab    On Controller 0 set amplitude to 1.
458*520a44d4SMauro Carvalho Chehab
459*520a44d4SMauro Carvalho Chehab    ::
460*520a44d4SMauro Carvalho Chehab
461*520a44d4SMauro Carvalho Chehab	amplitude :{1,,7}
462*520a44d4SMauro Carvalho Chehab
463*520a44d4SMauro Carvalho Chehab    - On Controller 0 set amplitude to 1.
464*520a44d4SMauro Carvalho Chehab    - On Controller 2 set amplitude to 7.
465*520a44d4SMauro Carvalho Chehab
466*520a44d4SMauro Carvalho ChehabExample::
467*520a44d4SMauro Carvalho Chehab
468*520a44d4SMauro Carvalho Chehab    options aic79xx aic79xx=verbose,rd_strm:{{0x0041}}
469*520a44d4SMauro Carvalho Chehab
470*520a44d4SMauro Carvalho Chehabenables verbose output in the driver and turns read streaming on
471*520a44d4SMauro Carvalho Chehabfor targets 0 and 6 of Controller 0.
472*520a44d4SMauro Carvalho Chehab
473*520a44d4SMauro Carvalho Chehab4. Additional Notes
474*520a44d4SMauro Carvalho Chehab===================
475*520a44d4SMauro Carvalho Chehab
476*520a44d4SMauro Carvalho Chehab4.1. Known/Unresolved or FYI Issues
477*520a44d4SMauro Carvalho Chehab-----------------------------------
478*520a44d4SMauro Carvalho Chehab
479*520a44d4SMauro Carvalho Chehab        * Under SuSE Linux Enterprise 7, the driver may fail to operate
480*520a44d4SMauro Carvalho Chehab          correctly due to a problem with PCI interrupt routing in the
481*520a44d4SMauro Carvalho Chehab          Linux kernel.  Please contact SuSE for an updated Linux
482*520a44d4SMauro Carvalho Chehab          kernel.
483*520a44d4SMauro Carvalho Chehab
484*520a44d4SMauro Carvalho Chehab4.2. Third-Party Compatibility Issues
485*520a44d4SMauro Carvalho Chehab-------------------------------------
486*520a44d4SMauro Carvalho Chehab
487*520a44d4SMauro Carvalho Chehab        * Adaptec only supports Ultra320 hard drives running
488*520a44d4SMauro Carvalho Chehab          the latest firmware available. Please check with
489*520a44d4SMauro Carvalho Chehab          your hard drive manufacturer to ensure you have the
490*520a44d4SMauro Carvalho Chehab          latest version.
491*520a44d4SMauro Carvalho Chehab
492*520a44d4SMauro Carvalho Chehab4.3. Operating System or Technology Limitations
493*520a44d4SMauro Carvalho Chehab-----------------------------------------------
494*520a44d4SMauro Carvalho Chehab
495*520a44d4SMauro Carvalho Chehab        * PCI Hot Plug is untested and may cause the operating system
496*520a44d4SMauro Carvalho Chehab          to stop responding.
497*520a44d4SMauro Carvalho Chehab        * Luns that are not numbered contiguously starting with 0 might not
498*520a44d4SMauro Carvalho Chehab          be automatically probed during system startup.  This is a limitation
499*520a44d4SMauro Carvalho Chehab          of the OS.  Please contact your Linux vendor for instructions on
500*520a44d4SMauro Carvalho Chehab          manually probing non-contiguous luns.
501*520a44d4SMauro Carvalho Chehab        * Using the Driver Update Disk version of this package during OS
502*520a44d4SMauro Carvalho Chehab          installation under RedHat might result in two versions of this
503*520a44d4SMauro Carvalho Chehab          driver being installed into the system module directory.  This
504*520a44d4SMauro Carvalho Chehab          might cause problems with the /sbin/mkinitrd program and/or
505*520a44d4SMauro Carvalho Chehab          other RPM packages that try to install system modules.  The best
506*520a44d4SMauro Carvalho Chehab          way to correct this once the system is running is to install
507*520a44d4SMauro Carvalho Chehab          the latest RPM package version of this driver, available from
508*520a44d4SMauro Carvalho Chehab          http://www.adaptec.com.
509*520a44d4SMauro Carvalho Chehab
510*520a44d4SMauro Carvalho Chehab
511*520a44d4SMauro Carvalho Chehab5. Adaptec Customer Support
512*520a44d4SMauro Carvalho Chehab===========================
513*520a44d4SMauro Carvalho Chehab
514*520a44d4SMauro Carvalho Chehab   A Technical Support Identification (TSID) Number is required for
515*520a44d4SMauro Carvalho Chehab   Adaptec technical support.
516*520a44d4SMauro Carvalho Chehab
517*520a44d4SMauro Carvalho Chehab    - The 12-digit TSID can be found on the white barcode-type label
518*520a44d4SMauro Carvalho Chehab      included inside the box with your product.  The TSID helps us
519*520a44d4SMauro Carvalho Chehab      provide more efficient service by accurately identifying your
520*520a44d4SMauro Carvalho Chehab      product and support status.
521*520a44d4SMauro Carvalho Chehab
522*520a44d4SMauro Carvalho Chehab   Support Options
523*520a44d4SMauro Carvalho Chehab    - Search the Adaptec Support Knowledgebase (ASK) at
524*520a44d4SMauro Carvalho Chehab      http://ask.adaptec.com for articles, troubleshooting tips, and
525*520a44d4SMauro Carvalho Chehab      frequently asked questions about your product.
526*520a44d4SMauro Carvalho Chehab    - For support via Email, submit your question to Adaptec's
527*520a44d4SMauro Carvalho Chehab      Technical Support Specialists at http://ask.adaptec.com/.
528*520a44d4SMauro Carvalho Chehab
529*520a44d4SMauro Carvalho Chehab   North America
530*520a44d4SMauro Carvalho Chehab    - Visit our Web site at http://www.adaptec.com/.
531*520a44d4SMauro Carvalho Chehab    - For information about Adaptec's support options, call
532*520a44d4SMauro Carvalho Chehab      408-957-2550, 24 hours a day, 7 days a week.
533*520a44d4SMauro Carvalho Chehab    - To speak with a Technical Support Specialist,
534*520a44d4SMauro Carvalho Chehab
535*520a44d4SMauro Carvalho Chehab      * For hardware products, call 408-934-7274,
536*520a44d4SMauro Carvalho Chehab        Monday to Friday, 3:00 am to 5:00 pm, PDT.
537*520a44d4SMauro Carvalho Chehab      * For RAID and Fibre Channel products, call 321-207-2000,
538*520a44d4SMauro Carvalho Chehab        Monday to Friday, 3:00 am to 5:00 pm, PDT.
539*520a44d4SMauro Carvalho Chehab
540*520a44d4SMauro Carvalho Chehab      To expedite your service, have your computer with you.
541*520a44d4SMauro Carvalho Chehab    - To order Adaptec products, including accessories and cables,
542*520a44d4SMauro Carvalho Chehab      call 408-957-7274.  To order cables online go to
543*520a44d4SMauro Carvalho Chehab      http://www.adaptec.com/buy-cables/.
544*520a44d4SMauro Carvalho Chehab
545*520a44d4SMauro Carvalho Chehab   Europe
546*520a44d4SMauro Carvalho Chehab    - Visit our Web site at http://www.adaptec.com/en-US/_common/world_index.
547*520a44d4SMauro Carvalho Chehab    - To speak with a Technical Support Specialist, call, or email,
548*520a44d4SMauro Carvalho Chehab
549*520a44d4SMauro Carvalho Chehab      * German:  +49 89 4366 5522, Monday-Friday, 9:00-17:00 CET,
550*520a44d4SMauro Carvalho Chehab        http://ask-de.adaptec.com/.
551*520a44d4SMauro Carvalho Chehab      * French:  +49 89 4366 5533, Monday-Friday, 9:00-17:00 CET,
552*520a44d4SMauro Carvalho Chehab	http://ask-fr.adaptec.com/.
553*520a44d4SMauro Carvalho Chehab      * English: +49 89 4366 5544, Monday-Friday, 9:00-17:00 GMT,
554*520a44d4SMauro Carvalho Chehab	http://ask.adaptec.com/.
555*520a44d4SMauro Carvalho Chehab
556*520a44d4SMauro Carvalho Chehab    - You can order Adaptec cables online at
557*520a44d4SMauro Carvalho Chehab      http://www.adaptec.com/buy-cables/.
558*520a44d4SMauro Carvalho Chehab
559*520a44d4SMauro Carvalho Chehab   Japan
560*520a44d4SMauro Carvalho Chehab    - Visit our web site at http://www.adaptec.co.jp/.
561*520a44d4SMauro Carvalho Chehab    - To speak with a Technical Support Specialist, call
562*520a44d4SMauro Carvalho Chehab      +81 3 5308 6120, Monday-Friday, 9:00 a.m. to 12:00 p.m.,
563*520a44d4SMauro Carvalho Chehab      1:00 p.m. to 6:00 p.m.
564*520a44d4SMauro Carvalho Chehab
565*520a44d4SMauro Carvalho ChehabCopyright |copy| 2003 Adaptec Inc. 691 S. Milpitas Blvd., Milpitas CA 95035 USA.
566*520a44d4SMauro Carvalho ChehabAll rights reserved.
567*520a44d4SMauro Carvalho Chehab
568*520a44d4SMauro Carvalho ChehabYou are permitted to redistribute, use and modify this README file in whole
569*520a44d4SMauro Carvalho Chehabor in part in conjunction with redistribution of software governed by the
570*520a44d4SMauro Carvalho ChehabGeneral Public License, provided that the following conditions are met:
571*520a44d4SMauro Carvalho Chehab
572*520a44d4SMauro Carvalho Chehab1. Redistributions of README file must retain the above copyright
573*520a44d4SMauro Carvalho Chehab   notice, this list of conditions, and the following disclaimer,
574*520a44d4SMauro Carvalho Chehab   without modification.
575*520a44d4SMauro Carvalho Chehab2. The name of the author may not be used to endorse or promote products
576*520a44d4SMauro Carvalho Chehab   derived from this software without specific prior written permission.
577*520a44d4SMauro Carvalho Chehab3. Modifications or new contributions must be attributed in a copyright
578*520a44d4SMauro Carvalho Chehab   notice identifying the author ("Contributor") and added below the
579*520a44d4SMauro Carvalho Chehab   original copyright notice. The copyright notice is for purposes of
580*520a44d4SMauro Carvalho Chehab   identifying contributors and should not be deemed as permission to alter
581*520a44d4SMauro Carvalho Chehab   the permissions given by Adaptec.
582*520a44d4SMauro Carvalho Chehab
583*520a44d4SMauro Carvalho ChehabTHIS README FILE IS PROVIDED BY ADAPTEC AND CONTRIBUTORS ``AS IS`` AND
584*520a44d4SMauro Carvalho ChehabANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ANY
585*520a44d4SMauro Carvalho ChehabWARRANTIES OF NON-INFRINGEMENT OR THE IMPLIED WARRANTIES OF MERCHANTABILITY
586*520a44d4SMauro Carvalho ChehabAND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
587*520a44d4SMauro Carvalho ChehabADAPTEC OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
588*520a44d4SMauro Carvalho ChehabSPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
589*520a44d4SMauro Carvalho ChehabTO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
590*520a44d4SMauro Carvalho ChehabPROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
591*520a44d4SMauro Carvalho ChehabLIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
592*520a44d4SMauro Carvalho ChehabNEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS README
593*520a44d4SMauro Carvalho ChehabFILE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
594