xref: /openbmc/linux/Documentation/networking/device_drivers/can/ctu/ctucanfd-driver.rst (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1c3a0addeSPavel Pisa.. SPDX-License-Identifier: GPL-2.0-or-later
2c3a0addeSPavel Pisa
3c3a0addeSPavel PisaCTU CAN FD Driver
4c3a0addeSPavel Pisa=================
5c3a0addeSPavel Pisa
6c3a0addeSPavel PisaAuthor: Martin Jerabek <martin.jerabek01@gmail.com>
7c3a0addeSPavel Pisa
8c3a0addeSPavel Pisa
9c3a0addeSPavel PisaAbout CTU CAN FD IP Core
10c3a0addeSPavel Pisa------------------------
11c3a0addeSPavel Pisa
12c3a0addeSPavel Pisa`CTU CAN FD <https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core>`_
13c3a0addeSPavel Pisais an open source soft core written in VHDL.
14c3a0addeSPavel PisaIt originated in 2015 as Ondrej Ille's project
15c3a0addeSPavel Pisaat the `Department of Measurement <https://meas.fel.cvut.cz/>`_
16c3a0addeSPavel Pisaof `FEE <http://www.fel.cvut.cz/en/>`_ at `CTU <https://www.cvut.cz/en>`_.
17c3a0addeSPavel Pisa
18c3a0addeSPavel PisaThe SocketCAN driver for Xilinx Zynq SoC based MicroZed board
19c3a0addeSPavel Pisa`Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20c3a0addeSPavel Pisaand Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21c3a0addeSPavel Pisa`QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
22c3a0addeSPavel Pisahas been developed as well as support for
23c3a0addeSPavel Pisa`PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
24c3a0addeSPavel Pisa
25c3a0addeSPavel PisaIn the case of Zynq, the core is connected via the APB system bus, which does
26c3a0addeSPavel Pisanot have enumeration support, and the device must be specified in Device Tree.
27c3a0addeSPavel PisaThis kind of devices is called platform device in the kernel and is
28c3a0addeSPavel Pisahandled by a platform device driver.
29c3a0addeSPavel Pisa
30c3a0addeSPavel PisaThe basic functional model of the CTU CAN FD peripheral has been
31c3a0addeSPavel Pisaaccepted into QEMU mainline. See QEMU `CAN emulation support <https://www.qemu.org/docs/master/system/devices/can.html>`_
32c3a0addeSPavel Pisafor CAN FD buses, host connection and CTU CAN FD core emulation. The development
33c3a0addeSPavel Pisaversion of emulation support can be cloned from ctu-canfd branch of QEMU local
34c3a0addeSPavel Pisadevelopment `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
35c3a0addeSPavel Pisa
36c3a0addeSPavel Pisa
37c3a0addeSPavel PisaAbout SocketCAN
38c3a0addeSPavel Pisa---------------
39c3a0addeSPavel Pisa
40c3a0addeSPavel PisaSocketCAN is a standard common interface for CAN devices in the Linux
41c3a0addeSPavel Pisakernel. As the name suggests, the bus is accessed via sockets, similarly
42c3a0addeSPavel Pisato common network devices. The reasoning behind this is in depth
43c3a0addeSPavel Pisadescribed in `Linux SocketCAN <https://www.kernel.org/doc/html/latest/networking/can.html>`_.
44c3a0addeSPavel PisaIn short, it offers a
45c3a0addeSPavel Pisanatural way to implement and work with higher layer protocols over CAN,
46c3a0addeSPavel Pisain the same way as, e.g., UDP/IP over Ethernet.
47c3a0addeSPavel Pisa
48c3a0addeSPavel PisaDevice probe
49c3a0addeSPavel Pisa~~~~~~~~~~~~
50c3a0addeSPavel Pisa
51c3a0addeSPavel PisaBefore going into detail about the structure of a CAN bus device driver,
52c3a0addeSPavel Pisalet's reiterate how the kernel gets to know about the device at all.
53c3a0addeSPavel PisaSome buses, like PCI or PCIe, support device enumeration. That is, when
54c3a0addeSPavel Pisathe system boots, it discovers all the devices on the bus and reads
55c3a0addeSPavel Pisatheir configuration. The kernel identifies the device via its vendor ID
56c3a0addeSPavel Pisaand device ID, and if there is a driver registered for this identifier
57c3a0addeSPavel Pisacombination, its probe method is invoked to populate the driver's
58c3a0addeSPavel Pisainstance for the given hardware. A similar situation goes with USB, only
59c3a0addeSPavel Pisait allows for device hot-plug.
60c3a0addeSPavel Pisa
61c3a0addeSPavel PisaThe situation is different for peripherals which are directly embedded
62c3a0addeSPavel Pisain the SoC and connected to an internal system bus (AXI, APB, Avalon,
63c3a0addeSPavel Pisaand others). These buses do not support enumeration, and thus the kernel
64c3a0addeSPavel Pisahas to learn about the devices from elsewhere. This is exactly what the
65c3a0addeSPavel PisaDevice Tree was made for.
66c3a0addeSPavel Pisa
67c3a0addeSPavel PisaDevice tree
68c3a0addeSPavel Pisa~~~~~~~~~~~
69c3a0addeSPavel Pisa
70c3a0addeSPavel PisaAn entry in device tree states that a device exists in the system, how
71c3a0addeSPavel Pisait is reachable (on which bus it resides) and its configuration –
72c3a0addeSPavel Pisaregisters address, interrupts and so on. An example of such a device
73c3a0addeSPavel Pisatree is given in .
74c3a0addeSPavel Pisa
75ba3e2eaeSAkira Yokosawa::
76c3a0addeSPavel Pisa
77c3a0addeSPavel Pisa           / {
78c3a0addeSPavel Pisa               /* ... */
79c3a0addeSPavel Pisa               amba: amba {
80c3a0addeSPavel Pisa                   #address-cells = <1>;
81c3a0addeSPavel Pisa                   #size-cells = <1>;
82c3a0addeSPavel Pisa                   compatible = "simple-bus";
83c3a0addeSPavel Pisa
84c3a0addeSPavel Pisa                   CTU_CAN_FD_0: CTU_CAN_FD@43c30000 {
85c3a0addeSPavel Pisa                       compatible = "ctu,ctucanfd";
86c3a0addeSPavel Pisa                       interrupt-parent = <&intc>;
87c3a0addeSPavel Pisa                       interrupts = <0 30 4>;
88c3a0addeSPavel Pisa                       clocks = <&clkc 15>;
89c3a0addeSPavel Pisa                       reg = <0x43c30000 0x10000>;
90c3a0addeSPavel Pisa                   };
91c3a0addeSPavel Pisa               };
92c3a0addeSPavel Pisa           };
93c3a0addeSPavel Pisa
94c3a0addeSPavel Pisa
95c3a0addeSPavel Pisa.. _sec:socketcan:drv:
96c3a0addeSPavel Pisa
97c3a0addeSPavel PisaDriver structure
98c3a0addeSPavel Pisa~~~~~~~~~~~~~~~~
99c3a0addeSPavel Pisa
100c3a0addeSPavel PisaThe driver can be divided into two parts – platform-dependent device
101c3a0addeSPavel Pisadiscovery and set up, and platform-independent CAN network device
102c3a0addeSPavel Pisaimplementation.
103c3a0addeSPavel Pisa
104c3a0addeSPavel Pisa.. _sec:socketcan:platdev:
105c3a0addeSPavel Pisa
106c3a0addeSPavel PisaPlatform device driver
107c3a0addeSPavel Pisa^^^^^^^^^^^^^^^^^^^^^^
108c3a0addeSPavel Pisa
109c3a0addeSPavel PisaIn the case of Zynq, the core is connected via the AXI system bus, which
110c3a0addeSPavel Pisadoes not have enumeration support, and the device must be specified in
111c3a0addeSPavel PisaDevice Tree. This kind of devices is called *platform device* in the
112c3a0addeSPavel Pisakernel and is handled by a *platform device driver*\  [1]_.
113c3a0addeSPavel Pisa
114c3a0addeSPavel PisaA platform device driver provides the following things:
115c3a0addeSPavel Pisa
116c3a0addeSPavel Pisa-  A *probe* function
117c3a0addeSPavel Pisa
118c3a0addeSPavel Pisa-  A *remove* function
119c3a0addeSPavel Pisa
120c3a0addeSPavel Pisa-  A table of *compatible* devices that the driver can handle
121c3a0addeSPavel Pisa
122c3a0addeSPavel PisaThe *probe* function is called exactly once when the device appears (or
123c3a0addeSPavel Pisathe driver is loaded, whichever happens later). If there are more
124c3a0addeSPavel Pisadevices handled by the same driver, the *probe* function is called for
125c3a0addeSPavel Pisaeach one of them. Its role is to allocate and initialize resources
126c3a0addeSPavel Pisarequired for handling the device, as well as set up low-level functions
127c3a0addeSPavel Pisafor the platform-independent layer, e.g., *read_reg* and *write_reg*.
128c3a0addeSPavel PisaAfter that, the driver registers the device to a higher layer, in our
129c3a0addeSPavel Pisacase as a *network device*.
130c3a0addeSPavel Pisa
131c3a0addeSPavel PisaThe *remove* function is called when the device disappears, or the
132c3a0addeSPavel Pisadriver is about to be unloaded. It serves to free the resources
133c3a0addeSPavel Pisaallocated in *probe* and to unregister the device from higher layers.
134c3a0addeSPavel Pisa
135c3a0addeSPavel PisaFinally, the table of *compatible* devices states which devices the
136c3a0addeSPavel Pisadriver can handle. The Device Tree entry ``compatible`` is matched
137c3a0addeSPavel Pisaagainst the tables of all *platform drivers*.
138c3a0addeSPavel Pisa
139c3a0addeSPavel Pisa.. code:: c
140c3a0addeSPavel Pisa
141c3a0addeSPavel Pisa           /* Match table for OF platform binding */
142c3a0addeSPavel Pisa           static const struct of_device_id ctucan_of_match[] = {
143c3a0addeSPavel Pisa               { .compatible = "ctu,canfd-2", },
144c3a0addeSPavel Pisa               { .compatible = "ctu,ctucanfd", },
145c3a0addeSPavel Pisa               { /* end of list */ },
146c3a0addeSPavel Pisa           };
147c3a0addeSPavel Pisa           MODULE_DEVICE_TABLE(of, ctucan_of_match);
148c3a0addeSPavel Pisa
149c3a0addeSPavel Pisa           static int ctucan_probe(struct platform_device *pdev);
150c3a0addeSPavel Pisa           static int ctucan_remove(struct platform_device *pdev);
151c3a0addeSPavel Pisa
152c3a0addeSPavel Pisa           static struct platform_driver ctucanfd_driver = {
153c3a0addeSPavel Pisa               .probe  = ctucan_probe,
154c3a0addeSPavel Pisa               .remove = ctucan_remove,
155c3a0addeSPavel Pisa               .driver = {
156c3a0addeSPavel Pisa                   .name = DRIVER_NAME,
157c3a0addeSPavel Pisa                   .of_match_table = ctucan_of_match,
158c3a0addeSPavel Pisa               },
159c3a0addeSPavel Pisa           };
160c3a0addeSPavel Pisa           module_platform_driver(ctucanfd_driver);
161c3a0addeSPavel Pisa
162c3a0addeSPavel Pisa
163c3a0addeSPavel Pisa.. _sec:socketcan:netdev:
164c3a0addeSPavel Pisa
165c3a0addeSPavel PisaNetwork device driver
166c3a0addeSPavel Pisa^^^^^^^^^^^^^^^^^^^^^
167c3a0addeSPavel Pisa
168c3a0addeSPavel PisaEach network device must support at least these operations:
169c3a0addeSPavel Pisa
170c3a0addeSPavel Pisa-  Bring the device up: ``ndo_open``
171c3a0addeSPavel Pisa
172c3a0addeSPavel Pisa-  Bring the device down: ``ndo_close``
173c3a0addeSPavel Pisa
174c3a0addeSPavel Pisa-  Submit TX frames to the device: ``ndo_start_xmit``
175c3a0addeSPavel Pisa
176c3a0addeSPavel Pisa-  Signal TX completion and errors to the network subsystem: ISR
177c3a0addeSPavel Pisa
178c3a0addeSPavel Pisa-  Submit RX frames to the network subsystem: ISR and NAPI
179c3a0addeSPavel Pisa
180c3a0addeSPavel PisaThere are two possible event sources: the device and the network
181c3a0addeSPavel Pisasubsystem. Device events are usually signaled via an interrupt, handled
182c3a0addeSPavel Pisain an Interrupt Service Routine (ISR). Handlers for the events
183c3a0addeSPavel Pisaoriginating in the network subsystem are then specified in
184c3a0addeSPavel Pisa``struct net_device_ops``.
185c3a0addeSPavel Pisa
186c3a0addeSPavel PisaWhen the device is brought up, e.g., by calling ``ip link set can0 up``,
187c3a0addeSPavel Pisathe driver’s function ``ndo_open`` is called. It should validate the
188c3a0addeSPavel Pisainterface configuration and configure and enable the device. The
189c3a0addeSPavel Pisaanalogous opposite is ``ndo_close``, called when the device is being
190c3a0addeSPavel Pisabrought down, be it explicitly or implicitly.
191c3a0addeSPavel Pisa
192c3a0addeSPavel PisaWhen the system should transmit a frame, it does so by calling
193c3a0addeSPavel Pisa``ndo_start_xmit``, which enqueues the frame into the device. If the
194c3a0addeSPavel Pisadevice HW queue (FIFO, mailboxes or whatever the implementation is)
195c3a0addeSPavel Pisabecomes full, the ``ndo_start_xmit`` implementation informs the network
196c3a0addeSPavel Pisasubsystem that it should stop the TX queue (via ``netif_stop_queue``).
197c3a0addeSPavel PisaIt is then re-enabled later in ISR when the device has some space
198c3a0addeSPavel Pisaavailable again and is able to enqueue another frame.
199c3a0addeSPavel Pisa
200c3a0addeSPavel PisaAll the device events are handled in ISR, namely:
201c3a0addeSPavel Pisa
202c3a0addeSPavel Pisa#. **TX completion**. When the device successfully finishes transmitting
203c3a0addeSPavel Pisa   a frame, the frame is echoed locally. On error, an informative error
204c3a0addeSPavel Pisa   frame [2]_ is sent to the network subsystem instead. In both cases,
205c3a0addeSPavel Pisa   the software TX queue is resumed so that more frames may be sent.
206c3a0addeSPavel Pisa
207c3a0addeSPavel Pisa#. **Error condition**. If something goes wrong (e.g., the device goes
208c3a0addeSPavel Pisa   bus-off or RX overrun happens), error counters are updated, and
209c3a0addeSPavel Pisa   informative error frames are enqueued to SW RX queue.
210c3a0addeSPavel Pisa
211c3a0addeSPavel Pisa#. **RX buffer not empty**. In this case, read the RX frames and enqueue
212c3a0addeSPavel Pisa   them to SW RX queue. Usually NAPI is used as a middle layer (see ).
213c3a0addeSPavel Pisa
214c3a0addeSPavel Pisa.. _sec:socketcan:napi:
215c3a0addeSPavel Pisa
216c3a0addeSPavel PisaNAPI
217c3a0addeSPavel Pisa~~~~
218c3a0addeSPavel Pisa
219c3a0addeSPavel PisaThe frequency of incoming frames can be high and the overhead to invoke
220c3a0addeSPavel Pisathe interrupt service routine for each frame can cause significant
221c3a0addeSPavel Pisasystem load. There are multiple mechanisms in the Linux kernel to deal
222c3a0addeSPavel Pisawith this situation. They evolved over the years of Linux kernel
223c3a0addeSPavel Pisadevelopment and enhancements. For network devices, the current standard
224c3a0addeSPavel Pisais NAPI – *the New API*. It is similar to classical top-half/bottom-half
225c3a0addeSPavel Pisainterrupt handling in that it only acknowledges the interrupt in the ISR
226c3a0addeSPavel Pisaand signals that the rest of the processing should be done in softirq
227c3a0addeSPavel Pisacontext. On top of that, it offers the possibility to *poll* for new
228c3a0addeSPavel Pisaframes for a while. This has a potential to avoid the costly round of
229c3a0addeSPavel Pisaenabling interrupts, handling an incoming IRQ in ISR, re-enabling the
230c3a0addeSPavel Pisasoftirq and switching context back to softirq.
231c3a0addeSPavel Pisa
232*3eb8eea2SJakub KicinskiSee :ref:`Documentation/networking/napi.rst <napi>` for more information.
233c3a0addeSPavel Pisa
234c3a0addeSPavel PisaIntegrating the core to Xilinx Zynq
235c3a0addeSPavel Pisa-----------------------------------
236c3a0addeSPavel Pisa
237c3a0addeSPavel PisaThe core interfaces a simple subset of the Avalon
238c3a0addeSPavel Pisa(search for Intel **Avalon Interface Specifications**)
239c3a0addeSPavel Pisabus as it was originally used on
240c3a0addeSPavel PisaAlterra FPGA chips, yet Xilinx natively interfaces with AXI
241c3a0addeSPavel Pisa(search for ARM **AMBA AXI and ACE Protocol Specification AXI3,
242c3a0addeSPavel PisaAXI4, and AXI4-Lite, ACE and ACE-Lite**).
243c3a0addeSPavel PisaThe most obvious solution would be to use
244c3a0addeSPavel Pisaan Avalon/AXI bridge or implement some simple conversion entity.
245c3a0addeSPavel PisaHowever, the core’s interface is half-duplex with no handshake
246c3a0addeSPavel Pisasignaling, whereas AXI is full duplex with two-way signaling. Moreover,
247c3a0addeSPavel Pisaeven AXI-Lite slave interface is quite resource-intensive, and the
248c3a0addeSPavel Pisaflexibility and speed of AXI are not required for a CAN core.
249c3a0addeSPavel Pisa
250c3a0addeSPavel PisaThus a much simpler bus was chosen – APB (Advanced Peripheral Bus)
251c3a0addeSPavel Pisa(search for ARM **AMBA APB Protocol Specification**).
252c3a0addeSPavel PisaAPB-AXI bridge is directly available in
253c3a0addeSPavel PisaXilinx Vivado, and the interface adaptor entity is just a few simple
254c3a0addeSPavel Pisacombinatorial assignments.
255c3a0addeSPavel Pisa
256c3a0addeSPavel PisaFinally, to be able to include the core in a block diagram as a custom
257c3a0addeSPavel PisaIP, the core, together with the APB interface, has been packaged as a
258c3a0addeSPavel PisaVivado component.
259c3a0addeSPavel Pisa
260c3a0addeSPavel PisaCTU CAN FD Driver design
261c3a0addeSPavel Pisa------------------------
262c3a0addeSPavel Pisa
263c3a0addeSPavel PisaThe general structure of a CAN device driver has already been examined
264c3a0addeSPavel Pisain . The next paragraphs provide a more detailed description of the CTU
265c3a0addeSPavel PisaCAN FD core driver in particular.
266c3a0addeSPavel Pisa
267c3a0addeSPavel PisaLow-level driver
268c3a0addeSPavel Pisa~~~~~~~~~~~~~~~~
269c3a0addeSPavel Pisa
270c3a0addeSPavel PisaThe core is not intended to be used solely with SocketCAN, and thus it
271c3a0addeSPavel Pisais desirable to have an OS-independent low-level driver. This low-level
272c3a0addeSPavel Pisadriver can then be used in implementations of OS driver or directly
273c3a0addeSPavel Pisaeither on bare metal or in a user-space application. Another advantage
274c3a0addeSPavel Pisais that if the hardware slightly changes, only the low-level driver
275c3a0addeSPavel Pisaneeds to be modified.
276c3a0addeSPavel Pisa
277c3a0addeSPavel PisaThe code [3]_ is in part automatically generated and in part written
278c3a0addeSPavel Pisamanually by the core author, with contributions of the thesis’ author.
279c3a0addeSPavel PisaThe low-level driver supports operations such as: set bit timing, set
280c3a0addeSPavel Pisacontroller mode, enable/disable, read RX frame, write TX frame, and so
281c3a0addeSPavel Pisaon.
282c3a0addeSPavel Pisa
283c3a0addeSPavel PisaConfiguring bit timing
284c3a0addeSPavel Pisa~~~~~~~~~~~~~~~~~~~~~~
285c3a0addeSPavel Pisa
286c3a0addeSPavel PisaOn CAN, each bit is divided into four segments: SYNC, PROP, PHASE1, and
287c3a0addeSPavel PisaPHASE2. Their duration is expressed in multiples of a Time Quantum
288c3a0addeSPavel Pisa(details in `CAN Specification, Version 2.0 <http://esd.cs.ucr.edu/webres/can20.pdf>`_, chapter 8).
289c3a0addeSPavel PisaWhen configuring
290c3a0addeSPavel Pisabitrate, the durations of all the segments (and time quantum) must be
291c3a0addeSPavel Pisacomputed from the bitrate and Sample Point. This is performed
292c3a0addeSPavel Pisaindependently for both the Nominal bitrate and Data bitrate for CAN FD.
293c3a0addeSPavel Pisa
294c3a0addeSPavel PisaSocketCAN is fairly flexible and offers either highly customized
295c3a0addeSPavel Pisaconfiguration by setting all the segment durations manually, or a
296c3a0addeSPavel Pisaconvenient configuration by setting just the bitrate and sample point
297c3a0addeSPavel Pisa(and even that is chosen automatically per Bosch recommendation if not
298c3a0addeSPavel Pisaspecified). However, each CAN controller may have different base clock
299c3a0addeSPavel Pisafrequency and different width of segment duration registers. The
300c3a0addeSPavel Pisaalgorithm thus needs the minimum and maximum values for the durations
301c3a0addeSPavel Pisa(and clock prescaler) and tries to optimize the numbers to fit both the
302c3a0addeSPavel Pisaconstraints and the requested parameters.
303c3a0addeSPavel Pisa
304c3a0addeSPavel Pisa.. code:: c
305c3a0addeSPavel Pisa
306c3a0addeSPavel Pisa           struct can_bittiming_const {
307c3a0addeSPavel Pisa               char name[16];      /* Name of the CAN controller hardware */
308c3a0addeSPavel Pisa               __u32 tseg1_min;    /* Time segment 1 = prop_seg + phase_seg1 */
309c3a0addeSPavel Pisa               __u32 tseg1_max;
310c3a0addeSPavel Pisa               __u32 tseg2_min;    /* Time segment 2 = phase_seg2 */
311c3a0addeSPavel Pisa               __u32 tseg2_max;
312c3a0addeSPavel Pisa               __u32 sjw_max;      /* Synchronisation jump width */
313c3a0addeSPavel Pisa               __u32 brp_min;      /* Bit-rate prescaler */
314c3a0addeSPavel Pisa               __u32 brp_max;
315c3a0addeSPavel Pisa               __u32 brp_inc;
316c3a0addeSPavel Pisa           };
317c3a0addeSPavel Pisa
318c3a0addeSPavel Pisa
319c3a0addeSPavel Pisa[lst:can_bittiming_const]
320c3a0addeSPavel Pisa
321c3a0addeSPavel PisaA curious reader will notice that the durations of the segments PROP_SEG
322c3a0addeSPavel Pisaand PHASE_SEG1 are not determined separately but rather combined and
323c3a0addeSPavel Pisathen, by default, the resulting TSEG1 is evenly divided between PROP_SEG
324c3a0addeSPavel Pisaand PHASE_SEG1. In practice, this has virtually no consequences as the
325c3a0addeSPavel Pisasample point is between PHASE_SEG1 and PHASE_SEG2. In CTU CAN FD,
326c3a0addeSPavel Pisahowever, the duration registers ``PROP`` and ``PH1`` have different
327c3a0addeSPavel Pisawidths (6 and 7 bits, respectively), so the auto-computed values might
328c3a0addeSPavel Pisaoverflow the shorter register and must thus be redistributed among the
329c3a0addeSPavel Pisatwo [4]_.
330c3a0addeSPavel Pisa
331c3a0addeSPavel PisaHandling RX
332c3a0addeSPavel Pisa~~~~~~~~~~~
333c3a0addeSPavel Pisa
334c3a0addeSPavel PisaFrame reception is handled in NAPI queue, which is enabled from ISR when
335c3a0addeSPavel Pisathe RXNE (RX FIFO Not Empty) bit is set. Frames are read one by one
336c3a0addeSPavel Pisauntil either no frame is left in the RX FIFO or the maximum work quota
337c3a0addeSPavel Pisahas been reached for the NAPI poll run (see ). Each frame is then passed
338c3a0addeSPavel Pisato the network interface RX queue.
339c3a0addeSPavel Pisa
340c3a0addeSPavel PisaAn incoming frame may be either a CAN 2.0 frame or a CAN FD frame. The
341c3a0addeSPavel Pisaway to distinguish between these two in the kernel is to allocate either
342c3a0addeSPavel Pisa``struct can_frame`` or ``struct canfd_frame``, the two having different
343c3a0addeSPavel Pisasizes. In the controller, the information about the frame type is stored
344c3a0addeSPavel Pisain the first word of RX FIFO.
345c3a0addeSPavel Pisa
346c3a0addeSPavel PisaThis brings us a chicken-egg problem: we want to allocate the ``skb``
347c3a0addeSPavel Pisafor the frame, and only if it succeeds, fetch the frame from FIFO;
348c3a0addeSPavel Pisaotherwise keep it there for later. But to be able to allocate the
349c3a0addeSPavel Pisacorrect ``skb``, we have to fetch the first work of FIFO. There are
350c3a0addeSPavel Pisaseveral possible solutions:
351c3a0addeSPavel Pisa
352c3a0addeSPavel Pisa#. Read the word, then allocate. If it fails, discard the rest of the
353c3a0addeSPavel Pisa   frame. When the system is low on memory, the situation is bad anyway.
354c3a0addeSPavel Pisa
355c3a0addeSPavel Pisa#. Always allocate ``skb`` big enough for an FD frame beforehand. Then
356c3a0addeSPavel Pisa   tweak the ``skb`` internals to look like it has been allocated for
357c3a0addeSPavel Pisa   the smaller CAN 2.0 frame.
358c3a0addeSPavel Pisa
359c3a0addeSPavel Pisa#. Add option to peek into the FIFO instead of consuming the word.
360c3a0addeSPavel Pisa
361c3a0addeSPavel Pisa#. If the allocation fails, store the read word into driver’s data. On
362c3a0addeSPavel Pisa   the next try, use the stored word instead of reading it again.
363c3a0addeSPavel Pisa
364c3a0addeSPavel PisaOption 1 is simple enough, but not very satisfying if we could do
365c3a0addeSPavel Pisabetter. Option 2 is not acceptable, as it would require modifying the
366c3a0addeSPavel Pisaprivate state of an integral kernel structure. The slightly higher
367c3a0addeSPavel Pisamemory consumption is just a virtual cherry on top of the “cake”. Option
368c3a0addeSPavel Pisa3 requires non-trivial HW changes and is not ideal from the HW point of
369c3a0addeSPavel Pisaview.
370c3a0addeSPavel Pisa
371c3a0addeSPavel PisaOption 4 seems like a good compromise, with its disadvantage being that
372c3a0addeSPavel Pisaa partial frame may stay in the FIFO for a prolonged time. Nonetheless,
373c3a0addeSPavel Pisathere may be just one owner of the RX FIFO, and thus no one else should
374c3a0addeSPavel Pisasee the partial frame (disregarding some exotic debugging scenarios).
375c3a0addeSPavel PisaBasides, the driver resets the core on its initialization, so the
376c3a0addeSPavel Pisapartial frame cannot be “adopted” either. In the end, option 4 was
377c3a0addeSPavel Pisaselected [5]_.
378c3a0addeSPavel Pisa
379c3a0addeSPavel Pisa.. _subsec:ctucanfd:rxtimestamp:
380c3a0addeSPavel Pisa
381c3a0addeSPavel PisaTimestamping RX frames
382c3a0addeSPavel Pisa^^^^^^^^^^^^^^^^^^^^^^
383c3a0addeSPavel Pisa
384c3a0addeSPavel PisaThe CTU CAN FD core reports the exact timestamp when the frame has been
385c3a0addeSPavel Pisareceived. The timestamp is by default captured at the sample point of
386c3a0addeSPavel Pisathe last bit of EOF but is configurable to be captured at the SOF bit.
387c3a0addeSPavel PisaThe timestamp source is external to the core and may be up to 64 bits
388c3a0addeSPavel Pisawide. At the time of writing, passing the timestamp from kernel to
389c3a0addeSPavel Pisauserspace is not yet implemented, but is planned in the future.
390c3a0addeSPavel Pisa
391c3a0addeSPavel PisaHandling TX
392c3a0addeSPavel Pisa~~~~~~~~~~~
393c3a0addeSPavel Pisa
394c3a0addeSPavel PisaThe CTU CAN FD core has 4 independent TX buffers, each with its own
395c3a0addeSPavel Pisastate and priority. When the core wants to transmit, a TX buffer in
396c3a0addeSPavel PisaReady state with the highest priority is selected.
397c3a0addeSPavel Pisa
398c3a0addeSPavel PisaThe priorities are 3bit numbers in register TX_PRIORITY
399c3a0addeSPavel Pisa(nibble-aligned). This should be flexible enough for most use cases.
400c3a0addeSPavel PisaSocketCAN, however, supports only one FIFO queue for outgoing
401c3a0addeSPavel Pisaframes [6]_. The buffer priorities may be used to simulate the FIFO
402c3a0addeSPavel Pisabehavior by assigning each buffer a distinct priority and *rotating* the
403c3a0addeSPavel Pisapriorities after a frame transmission is completed.
404c3a0addeSPavel Pisa
405c3a0addeSPavel PisaIn addition to priority rotation, the SW must maintain head and tail
406c3a0addeSPavel Pisapointers into the FIFO formed by the TX buffers to be able to determine
407c3a0addeSPavel Pisawhich buffer should be used for next frame (``txb_head``) and which
408c3a0addeSPavel Pisashould be the first completed one (``txb_tail``). The actual buffer
409c3a0addeSPavel Pisaindices are (obviously) modulo 4 (number of TX buffers), but the
410c3a0addeSPavel Pisapointers must be at least one bit wider to be able to distinguish
411c3a0addeSPavel Pisabetween FIFO full and FIFO empty – in this situation,
412c3a0addeSPavel Pisa:math:`txb\_head \equiv txb\_tail\ (\textrm{mod}\ 4)`. An example of how
413c3a0addeSPavel Pisathe FIFO is maintained, together with priority rotation, is depicted in
414c3a0addeSPavel Pisa
415c3a0addeSPavel Pisa|
416c3a0addeSPavel Pisa
417c3a0addeSPavel Pisa+------+---+---+---+---+
418c3a0addeSPavel Pisa| TXB# | 0 | 1 | 2 | 3 |
419c3a0addeSPavel Pisa+======+===+===+===+===+
420c3a0addeSPavel Pisa| Seq  | A | B | C |   |
421c3a0addeSPavel Pisa+------+---+---+---+---+
422c3a0addeSPavel Pisa| Prio | 7 | 6 | 5 | 4 |
423c3a0addeSPavel Pisa+------+---+---+---+---+
424c3a0addeSPavel Pisa|      |   | T |   | H |
425c3a0addeSPavel Pisa+------+---+---+---+---+
426c3a0addeSPavel Pisa
427c3a0addeSPavel Pisa|
428c3a0addeSPavel Pisa
429c3a0addeSPavel Pisa+------+---+---+---+---+
430c3a0addeSPavel Pisa| TXB# | 0 | 1 | 2 | 3 |
431c3a0addeSPavel Pisa+======+===+===+===+===+
432c3a0addeSPavel Pisa| Seq  |   | B | C |   |
433c3a0addeSPavel Pisa+------+---+---+---+---+
434c3a0addeSPavel Pisa| Prio | 4 | 7 | 6 | 5 |
435c3a0addeSPavel Pisa+------+---+---+---+---+
436c3a0addeSPavel Pisa|      |   | T |   | H |
437c3a0addeSPavel Pisa+------+---+---+---+---+
438c3a0addeSPavel Pisa
439c3a0addeSPavel Pisa|
440c3a0addeSPavel Pisa
441c3a0addeSPavel Pisa+------+---+---+---+---+----+
442c3a0addeSPavel Pisa| TXB# | 0 | 1 | 2 | 3 | 0’ |
443c3a0addeSPavel Pisa+======+===+===+===+===+====+
444c3a0addeSPavel Pisa| Seq  | E | B | C | D |    |
445c3a0addeSPavel Pisa+------+---+---+---+---+----+
446c3a0addeSPavel Pisa| Prio | 4 | 7 | 6 | 5 |    |
447c3a0addeSPavel Pisa+------+---+---+---+---+----+
448c3a0addeSPavel Pisa|      |   | T |   |   | H  |
449c3a0addeSPavel Pisa+------+---+---+---+---+----+
450c3a0addeSPavel Pisa
451c3a0addeSPavel Pisa|
452c3a0addeSPavel Pisa
453ba3e2eaeSAkira Yokosawa.. kernel-figure:: fsm_txt_buffer_user.svg
454c3a0addeSPavel Pisa
455c3a0addeSPavel Pisa   TX Buffer states with possible transitions
456c3a0addeSPavel Pisa
457c3a0addeSPavel Pisa.. _subsec:ctucanfd:txtimestamp:
458c3a0addeSPavel Pisa
459c3a0addeSPavel PisaTimestamping TX frames
460c3a0addeSPavel Pisa^^^^^^^^^^^^^^^^^^^^^^
461c3a0addeSPavel Pisa
462c3a0addeSPavel PisaWhen submitting a frame to a TX buffer, one may specify the timestamp at
463c3a0addeSPavel Pisawhich the frame should be transmitted. The frame transmission may start
464c3a0addeSPavel Pisalater, but not sooner. Note that the timestamp does not participate in
465c3a0addeSPavel Pisabuffer prioritization – that is decided solely by the mechanism
466c3a0addeSPavel Pisadescribed above.
467c3a0addeSPavel Pisa
468c3a0addeSPavel PisaSupport for time-based packet transmission was recently merged to Linux
469c3a0addeSPavel Pisav4.19 `Time-based packet transmission <https://lwn.net/Articles/748879/>`_,
470c3a0addeSPavel Pisabut it remains yet to be researched
471c3a0addeSPavel Pisawhether this functionality will be practical for CAN.
472c3a0addeSPavel Pisa
473c3a0addeSPavel PisaAlso similarly to retrieving the timestamp of RX frames, the core
474c3a0addeSPavel Pisasupports retrieving the timestamp of TX frames – that is the time when
475c3a0addeSPavel Pisathe frame was successfully delivered. The particulars are very similar
476c3a0addeSPavel Pisato timestamping RX frames and are described in .
477c3a0addeSPavel Pisa
478c3a0addeSPavel PisaHandling RX buffer overrun
479c3a0addeSPavel Pisa~~~~~~~~~~~~~~~~~~~~~~~~~~
480c3a0addeSPavel Pisa
481c3a0addeSPavel PisaWhen a received frame does no more fit into the hardware RX FIFO in its
482c3a0addeSPavel Pisaentirety, RX FIFO overrun flag (STATUS[DOR]) is set and Data Overrun
483c3a0addeSPavel PisaInterrupt (DOI) is triggered. When servicing the interrupt, care must be
484c3a0addeSPavel Pisataken first to clear the DOR flag (via COMMAND[CDO]) and after that
485c3a0addeSPavel Pisaclear the DOI interrupt flag. Otherwise, the interrupt would be
486c3a0addeSPavel Pisaimmediately [7]_ rearmed.
487c3a0addeSPavel Pisa
488c3a0addeSPavel Pisa**Note**: During development, it was discussed whether the internal HW
489c3a0addeSPavel Pisapipelining cannot disrupt this clear sequence and whether an additional
490c3a0addeSPavel Pisadummy cycle is necessary between clearing the flag and the interrupt. On
491c3a0addeSPavel Pisathe Avalon interface, it indeed proved to be the case, but APB being
492c3a0addeSPavel Pisasafe because it uses 2-cycle transactions. Essentially, the DOR flag
493c3a0addeSPavel Pisawould be cleared, but DOI register’s Preset input would still be high
494c3a0addeSPavel Pisathe cycle when the DOI clear request would also be applied (by setting
495c3a0addeSPavel Pisathe register’s Reset input high). As Set had higher priority than Reset,
496c3a0addeSPavel Pisathe DOI flag would not be reset. This has been already fixed by swapping
497c3a0addeSPavel Pisathe Set/Reset priority (see issue #187).
498c3a0addeSPavel Pisa
499c3a0addeSPavel PisaReporting Error Passive and Bus Off conditions
500c3a0addeSPavel Pisa~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
501c3a0addeSPavel Pisa
502c3a0addeSPavel PisaIt may be desirable to report when the node reaches *Error Passive*,
503c3a0addeSPavel Pisa*Error Warning*, and *Bus Off* conditions. The driver is notified about
504c3a0addeSPavel Pisaerror state change by an interrupt (EPI, EWLI), and then proceeds to
505c3a0addeSPavel Pisadetermine the core’s error state by reading its error counters.
506c3a0addeSPavel Pisa
507c3a0addeSPavel PisaThere is, however, a slight race condition here – there is a delay
508c3a0addeSPavel Pisabetween the time when the state transition occurs (and the interrupt is
509c3a0addeSPavel Pisatriggered) and when the error counters are read. When EPI is received,
510c3a0addeSPavel Pisathe node may be either *Error Passive* or *Bus Off*. If the node goes
511c3a0addeSPavel Pisa*Bus Off*, it obviously remains in the state until it is reset.
512c3a0addeSPavel PisaOtherwise, the node is *or was* *Error Passive*. However, it may happen
513c3a0addeSPavel Pisathat the read state is *Error Warning* or even *Error Active*. It may be
514c3a0addeSPavel Pisaunclear whether and what exactly to report in that case, but I
515c3a0addeSPavel Pisapersonally entertain the idea that the past error condition should still
516c3a0addeSPavel Pisabe reported. Similarly, when EWLI is received but the state is later
517c3a0addeSPavel Pisadetected to be *Error Passive*, *Error Passive* should be reported.
518c3a0addeSPavel Pisa
519c3a0addeSPavel Pisa
520c3a0addeSPavel PisaCTU CAN FD Driver Sources Reference
521c3a0addeSPavel Pisa-----------------------------------
522c3a0addeSPavel Pisa
523c3a0addeSPavel Pisa.. kernel-doc:: drivers/net/can/ctucanfd/ctucanfd.h
524c3a0addeSPavel Pisa   :internal:
525c3a0addeSPavel Pisa
526c3a0addeSPavel Pisa.. kernel-doc:: drivers/net/can/ctucanfd/ctucanfd_base.c
527c3a0addeSPavel Pisa   :internal:
528c3a0addeSPavel Pisa
529c3a0addeSPavel Pisa.. kernel-doc:: drivers/net/can/ctucanfd/ctucanfd_pci.c
530c3a0addeSPavel Pisa   :internal:
531c3a0addeSPavel Pisa
532c3a0addeSPavel Pisa.. kernel-doc:: drivers/net/can/ctucanfd/ctucanfd_platform.c
533c3a0addeSPavel Pisa   :internal:
534c3a0addeSPavel Pisa
535c3a0addeSPavel PisaCTU CAN FD IP Core and Driver Development Acknowledgment
536c3a0addeSPavel Pisa---------------------------------------------------------
537c3a0addeSPavel Pisa
53875790ef3SPavel Pisa* Odrej Ille <ondrej.ille@gmail.com>
539c3a0addeSPavel Pisa
540c3a0addeSPavel Pisa  * started the project as student at Department of Measurement, FEE, CTU
541c3a0addeSPavel Pisa  * invested great amount of personal time and enthusiasm to the project over years
542c3a0addeSPavel Pisa  * worked on more funded tasks
543c3a0addeSPavel Pisa
544c3a0addeSPavel Pisa* `Department of Measurement <https://meas.fel.cvut.cz/>`_,
545c3a0addeSPavel Pisa  `Faculty of Electrical Engineering <http://www.fel.cvut.cz/en/>`_,
546c3a0addeSPavel Pisa  `Czech Technical University <https://www.cvut.cz/en>`_
547c3a0addeSPavel Pisa
548c3a0addeSPavel Pisa  * is the main investor into the project over many years
549c3a0addeSPavel Pisa  * uses project in their CAN/CAN FD diagnostics framework for `Skoda Auto <https://www.skoda-auto.cz/>`_
550c3a0addeSPavel Pisa
551c3a0addeSPavel Pisa* `Digiteq Automotive <https://www.digiteqautomotive.com/en>`_
552c3a0addeSPavel Pisa
553c3a0addeSPavel Pisa  * funding of the project CAN FD Open Cores Support Linux Kernel Based Systems
554c3a0addeSPavel Pisa  * negotiated and paid CTU to allow public access to the project
555c3a0addeSPavel Pisa  * provided additional funding of the work
556c3a0addeSPavel Pisa
557c3a0addeSPavel Pisa* `Department of Control Engineering <https://control.fel.cvut.cz/en>`_,
558c3a0addeSPavel Pisa  `Faculty of Electrical Engineering <http://www.fel.cvut.cz/en/>`_,
559c3a0addeSPavel Pisa  `Czech Technical University <https://www.cvut.cz/en>`_
560c3a0addeSPavel Pisa
561c3a0addeSPavel Pisa  * solving the project CAN FD Open Cores Support Linux Kernel Based Systems
562c3a0addeSPavel Pisa  * providing GitLab management
563c3a0addeSPavel Pisa  * virtual servers and computational power for continuous integration
564c3a0addeSPavel Pisa  * providing hardware for HIL continuous integration tests
565c3a0addeSPavel Pisa
566c3a0addeSPavel Pisa* `PiKRON Ltd. <http://pikron.com/>`_
567c3a0addeSPavel Pisa
568c3a0addeSPavel Pisa  * minor funding to initiate preparation of the project open-sourcing
569c3a0addeSPavel Pisa
570c3a0addeSPavel Pisa* Petr Porazil <porazil@pikron.com>
571c3a0addeSPavel Pisa
572c3a0addeSPavel Pisa  * design of PCIe transceiver addon board and assembly of boards
573c3a0addeSPavel Pisa  * design and assembly of MZ_APO baseboard for MicroZed/Zynq based system
574c3a0addeSPavel Pisa
575c3a0addeSPavel Pisa* Martin Jerabek <martin.jerabek01@gmail.com>
576c3a0addeSPavel Pisa
577c3a0addeSPavel Pisa  * Linux driver development
578c3a0addeSPavel Pisa  * continuous integration platform architect and GHDL updates
579a266ef69SRandy Dunlap  * thesis `Open-source and Open-hardware CAN FD Protocol Support <https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-thesis-2019-canfd.pdf>`_
580c3a0addeSPavel Pisa
581c3a0addeSPavel Pisa* Jiri Novak <jnovak@fel.cvut.cz>
582c3a0addeSPavel Pisa
583c3a0addeSPavel Pisa  * project initiation, management and use at Department of Measurement, FEE, CTU
584c3a0addeSPavel Pisa
585c3a0addeSPavel Pisa* Pavel Pisa <pisa@cmp.felk.cvut.cz>
586c3a0addeSPavel Pisa
587c3a0addeSPavel Pisa  * initiate open-sourcing, project coordination, management at Department of Control Engineering, FEE, CTU
588c3a0addeSPavel Pisa
589c3a0addeSPavel Pisa* Jaroslav Beran<jara.beran@gmail.com>
590c3a0addeSPavel Pisa
591c3a0addeSPavel Pisa * system integration for Intel SoC, core and driver testing and updates
592c3a0addeSPavel Pisa
593c3a0addeSPavel Pisa* Carsten Emde (`OSADL <https://www.osadl.org/>`_)
594c3a0addeSPavel Pisa
595c3a0addeSPavel Pisa * provided OSADL expertise to discuss IP core licensing
596c3a0addeSPavel Pisa * pointed to possible deadlock for LGPL and CAN bus possible patent case which lead to relicense IP core design to BSD like license
597c3a0addeSPavel Pisa
598c3a0addeSPavel Pisa* Reiner Zitzmann and Holger Zeltwanger (`CAN in Automation <https://www.can-cia.org/>`_)
599c3a0addeSPavel Pisa
600c3a0addeSPavel Pisa * provided suggestions and help to inform community about the project and invited us to events focused on CAN bus future development directions
601c3a0addeSPavel Pisa
602c3a0addeSPavel Pisa* Jan Charvat
603c3a0addeSPavel Pisa
604c3a0addeSPavel Pisa * implemented CTU CAN FD functional model for QEMU which has been integrated into QEMU mainline (`docs/system/devices/can.rst <https://www.qemu.org/docs/master/system/devices/can.html>`_)
605a266ef69SRandy Dunlap * Bachelor thesis Model of CAN FD Communication Controller for QEMU Emulator
606c3a0addeSPavel Pisa
607c3a0addeSPavel PisaNotes
608c3a0addeSPavel Pisa-----
609c3a0addeSPavel Pisa
610c3a0addeSPavel Pisa
611c3a0addeSPavel Pisa.. [1]
612c3a0addeSPavel Pisa   Other buses have their own specific driver interface to set up the
613c3a0addeSPavel Pisa   device.
614c3a0addeSPavel Pisa
615c3a0addeSPavel Pisa.. [2]
616c3a0addeSPavel Pisa   Not to be mistaken with CAN Error Frame. This is a ``can_frame`` with
617c3a0addeSPavel Pisa   ``CAN_ERR_FLAG`` set and some error info in its ``data`` field.
618c3a0addeSPavel Pisa
619c3a0addeSPavel Pisa.. [3]
620c3a0addeSPavel Pisa   Available in CTU CAN FD repository
621c3a0addeSPavel Pisa   `<https://gitlab.fel.cvut.cz/canbus/ctucanfd_ip_core>`_
622c3a0addeSPavel Pisa
623c3a0addeSPavel Pisa.. [4]
624c3a0addeSPavel Pisa   As is done in the low-level driver functions
625c3a0addeSPavel Pisa   ``ctucan_hw_set_nom_bittiming`` and
626c3a0addeSPavel Pisa   ``ctucan_hw_set_data_bittiming``.
627c3a0addeSPavel Pisa
628c3a0addeSPavel Pisa.. [5]
629c3a0addeSPavel Pisa   At the time of writing this thesis, option 1 is still being used and
630c3a0addeSPavel Pisa   the modification is queued in gitlab issue #222
631c3a0addeSPavel Pisa
632c3a0addeSPavel Pisa.. [6]
633c3a0addeSPavel Pisa   Strictly speaking, multiple CAN TX queues are supported since v4.19
634c3a0addeSPavel Pisa   `can: enable multi-queue for SocketCAN devices <https://lore.kernel.org/patchwork/patch/913526/>`_ but no mainline driver is using
635c3a0addeSPavel Pisa   them yet.
636c3a0addeSPavel Pisa
637c3a0addeSPavel Pisa.. [7]
638c3a0addeSPavel Pisa   Or rather in the next clock cycle
639