xref: /openbmc/linux/Documentation/misc-devices/oxsemi-tornado.rst (revision 7b0364eacb8f5177b6747a1c524b4bfd04011a2a)
1*7b0364eaSMaciej W. Rozycki.. SPDX-License-Identifier: GPL-2.0
2*7b0364eaSMaciej W. Rozycki
3*7b0364eaSMaciej W. Rozycki====================================================================
4*7b0364eaSMaciej W. RozyckiNotes on Oxford Semiconductor PCIe (Tornado) 950 serial port devices
5*7b0364eaSMaciej W. Rozycki====================================================================
6*7b0364eaSMaciej W. Rozycki
7*7b0364eaSMaciej W. RozyckiOxford Semiconductor PCIe (Tornado) 950 serial port devices are driven
8*7b0364eaSMaciej W. Rozyckiby a fixed 62.5MHz clock input derived from the 100MHz PCI Express clock.
9*7b0364eaSMaciej W. Rozycki
10*7b0364eaSMaciej W. RozyckiThe baud rate produced by the baud generator is obtained from this input
11*7b0364eaSMaciej W. Rozyckifrequency by dividing it by the clock prescaler, which can be set to any
12*7b0364eaSMaciej W. Rozyckivalue from 1 to 63.875 in increments of 0.125, and then the usual 16-bit
13*7b0364eaSMaciej W. Rozyckidivisor is used as with the original 8250, to divide the frequency by a
14*7b0364eaSMaciej W. Rozyckivalue from 1 to 65535.  Finally a programmable oversampling rate is used
15*7b0364eaSMaciej W. Rozyckithat can take any value from 4 to 16 to divide the frequency further and
16*7b0364eaSMaciej W. Rozyckidetermine the actual baud rate used.  Baud rates from 15625000bps down
17*7b0364eaSMaciej W. Rozyckito 0.933bps can be obtained this way.
18*7b0364eaSMaciej W. Rozycki
19*7b0364eaSMaciej W. RozyckiBy default the oversampling rate is set to 16 and the clock prescaler is
20*7b0364eaSMaciej W. Rozyckiset to 33.875, meaning that the frequency to be used as the reference
21*7b0364eaSMaciej W. Rozyckifor the usual 16-bit divisor is 115313.653, which is close enough to the
22*7b0364eaSMaciej W. Rozyckifrequency of 115200 used by the original 8250 for the same values to be
23*7b0364eaSMaciej W. Rozyckiused for the divisor to obtain the requested baud rates by software that
24*7b0364eaSMaciej W. Rozyckiis unaware of the extra clock controls available.
25*7b0364eaSMaciej W. Rozycki
26*7b0364eaSMaciej W. RozyckiThe oversampling rate is programmed with the TCR register and the clock
27*7b0364eaSMaciej W. Rozyckiprescaler is programmed with the CPR/CPR2 register pair[1][2][3][4].
28*7b0364eaSMaciej W. RozyckiTo switch away from the default value of 33.875 for the prescaler the
29*7b0364eaSMaciej W. Rozyckithe enhanced mode has to be explicitly enabled though, by setting bit 4
30*7b0364eaSMaciej W. Rozyckiof the EFR.  In that mode setting bit 7 in the MCR enables the prescaler
31*7b0364eaSMaciej W. Rozyckior otherwise it is bypassed as if the value of 1 was used.  Additionally
32*7b0364eaSMaciej W. Rozyckiwriting any value to CPR clears CPR2 for compatibility with old software
33*7b0364eaSMaciej W. Rozyckiwritten for older conventional PCI Oxford Semiconductor devices that do
34*7b0364eaSMaciej W. Rozyckinot have the extra prescaler's 9th bit in CPR2, so the CPR/CPR2 register
35*7b0364eaSMaciej W. Rozyckipair has to be programmed in the right order.
36*7b0364eaSMaciej W. Rozycki
37*7b0364eaSMaciej W. RozyckiBy using these parameters rates from 15625000bps down to 1bps can be
38*7b0364eaSMaciej W. Rozyckiobtained, with either exact or highly-accurate actual bit rates for
39*7b0364eaSMaciej W. Rozyckistandard and many non-standard rates.
40*7b0364eaSMaciej W. Rozycki
41*7b0364eaSMaciej W. RozyckiHere are the figures for the standard and some non-standard baud rates
42*7b0364eaSMaciej W. Rozycki(including those quoted in Oxford Semiconductor documentation), giving
43*7b0364eaSMaciej W. Rozyckithe requested rate (r), the actual rate yielded (a) and its deviation
44*7b0364eaSMaciej W. Rozyckifrom the requested rate (d), and the values of the oversampling rate
45*7b0364eaSMaciej W. Rozycki(tcr), the clock prescaler (cpr) and the divisor (div) produced by the
46*7b0364eaSMaciej W. Rozyckinew `get_divisor' handler:
47*7b0364eaSMaciej W. Rozycki
48*7b0364eaSMaciej W. Rozyckir: 15625000, a: 15625000.00, d:  0.0000%, tcr:  4, cpr:  1.000, div:     1
49*7b0364eaSMaciej W. Rozyckir: 12500000, a: 12500000.00, d:  0.0000%, tcr:  5, cpr:  1.000, div:     1
50*7b0364eaSMaciej W. Rozyckir: 10416666, a: 10416666.67, d:  0.0000%, tcr:  6, cpr:  1.000, div:     1
51*7b0364eaSMaciej W. Rozyckir:  8928571, a:  8928571.43, d:  0.0000%, tcr:  7, cpr:  1.000, div:     1
52*7b0364eaSMaciej W. Rozyckir:  7812500, a:  7812500.00, d:  0.0000%, tcr:  8, cpr:  1.000, div:     1
53*7b0364eaSMaciej W. Rozyckir:  4000000, a:  4000000.00, d:  0.0000%, tcr:  5, cpr:  3.125, div:     1
54*7b0364eaSMaciej W. Rozyckir:  3686400, a:  3676470.59, d: -0.2694%, tcr:  8, cpr:  2.125, div:     1
55*7b0364eaSMaciej W. Rozyckir:  3500000, a:  3496503.50, d: -0.0999%, tcr: 13, cpr:  1.375, div:     1
56*7b0364eaSMaciej W. Rozyckir:  3000000, a:  2976190.48, d: -0.7937%, tcr: 14, cpr:  1.500, div:     1
57*7b0364eaSMaciej W. Rozyckir:  2500000, a:  2500000.00, d:  0.0000%, tcr: 10, cpr:  2.500, div:     1
58*7b0364eaSMaciej W. Rozyckir:  2000000, a:  2000000.00, d:  0.0000%, tcr: 10, cpr:  3.125, div:     1
59*7b0364eaSMaciej W. Rozyckir:  1843200, a:  1838235.29, d: -0.2694%, tcr: 16, cpr:  2.125, div:     1
60*7b0364eaSMaciej W. Rozyckir:  1500000, a:  1492537.31, d: -0.4975%, tcr:  5, cpr:  8.375, div:     1
61*7b0364eaSMaciej W. Rozyckir:  1152000, a:  1152073.73, d:  0.0064%, tcr: 14, cpr:  3.875, div:     1
62*7b0364eaSMaciej W. Rozyckir:   921600, a:   919117.65, d: -0.2694%, tcr: 16, cpr:  2.125, div:     2
63*7b0364eaSMaciej W. Rozyckir:   576000, a:   576036.87, d:  0.0064%, tcr: 14, cpr:  3.875, div:     2
64*7b0364eaSMaciej W. Rozyckir:   460800, a:   460829.49, d:  0.0064%, tcr:  7, cpr:  3.875, div:     5
65*7b0364eaSMaciej W. Rozyckir:   230400, a:   230414.75, d:  0.0064%, tcr: 14, cpr:  3.875, div:     5
66*7b0364eaSMaciej W. Rozyckir:   115200, a:   115207.37, d:  0.0064%, tcr: 14, cpr:  1.250, div:    31
67*7b0364eaSMaciej W. Rozyckir:    57600, a:    57603.69, d:  0.0064%, tcr:  8, cpr:  3.875, div:    35
68*7b0364eaSMaciej W. Rozyckir:    38400, a:    38402.46, d:  0.0064%, tcr: 14, cpr:  3.875, div:    30
69*7b0364eaSMaciej W. Rozyckir:    19200, a:    19201.23, d:  0.0064%, tcr:  8, cpr:  3.875, div:   105
70*7b0364eaSMaciej W. Rozyckir:     9600, a:     9600.06, d:  0.0006%, tcr:  9, cpr:  1.125, div:   643
71*7b0364eaSMaciej W. Rozyckir:     4800, a:     4799.98, d: -0.0004%, tcr:  7, cpr:  2.875, div:   647
72*7b0364eaSMaciej W. Rozyckir:     2400, a:     2400.02, d:  0.0008%, tcr:  9, cpr:  2.250, div:  1286
73*7b0364eaSMaciej W. Rozyckir:     1200, a:     1200.00, d:  0.0000%, tcr: 14, cpr:  2.875, div:  1294
74*7b0364eaSMaciej W. Rozyckir:      300, a:      300.00, d:  0.0000%, tcr: 11, cpr:  2.625, div:  7215
75*7b0364eaSMaciej W. Rozyckir:      200, a:      200.00, d:  0.0000%, tcr: 16, cpr:  1.250, div: 15625
76*7b0364eaSMaciej W. Rozyckir:      150, a:      150.00, d:  0.0000%, tcr: 13, cpr:  2.250, div: 14245
77*7b0364eaSMaciej W. Rozyckir:      134, a:      134.00, d:  0.0000%, tcr: 11, cpr:  2.625, div: 16153
78*7b0364eaSMaciej W. Rozyckir:      110, a:      110.00, d:  0.0000%, tcr: 12, cpr:  1.000, div: 47348
79*7b0364eaSMaciej W. Rozyckir:       75, a:       75.00, d:  0.0000%, tcr:  4, cpr:  5.875, div: 35461
80*7b0364eaSMaciej W. Rozyckir:       50, a:       50.00, d:  0.0000%, tcr: 16, cpr:  1.250, div: 62500
81*7b0364eaSMaciej W. Rozyckir:       25, a:       25.00, d:  0.0000%, tcr: 16, cpr:  2.500, div: 62500
82*7b0364eaSMaciej W. Rozyckir:        4, a:        4.00, d:  0.0000%, tcr: 16, cpr: 20.000, div: 48828
83*7b0364eaSMaciej W. Rozyckir:        2, a:        2.00, d:  0.0000%, tcr: 16, cpr: 40.000, div: 48828
84*7b0364eaSMaciej W. Rozyckir:        1, a:        1.00, d:  0.0000%, tcr: 16, cpr: 63.875, div: 61154
85*7b0364eaSMaciej W. Rozycki
86*7b0364eaSMaciej W. RozyckiWith the baud base set to 15625000 and the unsigned 16-bit UART_DIV_MAX
87*7b0364eaSMaciej W. Rozyckilimitation imposed by `serial8250_get_baud_rate' standard baud rates
88*7b0364eaSMaciej W. Rozyckibelow 300bps become unavailable in the regular way, e.g. the rate of
89*7b0364eaSMaciej W. Rozycki200bps requires the baud base to be divided by 78125 and that is beyond
90*7b0364eaSMaciej W. Rozyckithe unsigned 16-bit range.  The historic spd_cust feature can still be
91*7b0364eaSMaciej W. Rozyckiused by encoding the values for, the prescaler, the oversampling rate
92*7b0364eaSMaciej W. Rozyckiand the clock divisor (DLM/DLL) as follows to obtain such rates if so
93*7b0364eaSMaciej W. Rozyckirequired:
94*7b0364eaSMaciej W. Rozycki
95*7b0364eaSMaciej W. Rozycki 31 29 28             20 19   16 15                            0
96*7b0364eaSMaciej W. Rozycki+-----+-----------------+-------+-------------------------------+
97*7b0364eaSMaciej W. Rozycki|0 0 0|    CPR2:CPR     |  TCR  |            DLM:DLL            |
98*7b0364eaSMaciej W. Rozycki+-----+-----------------+-------+-------------------------------+
99*7b0364eaSMaciej W. Rozycki
100*7b0364eaSMaciej W. RozyckiUse a value such encoded for the `custom_divisor' field along with the
101*7b0364eaSMaciej W. RozyckiASYNC_SPD_CUST flag set in the `flags' field in `struct serial_struct'
102*7b0364eaSMaciej W. Rozyckipassed with the TIOCSSERIAL ioctl(2), such as with the setserial(8)
103*7b0364eaSMaciej W. Rozyckiutility and its `divisor' and `spd_cust' parameters, and the select
104*7b0364eaSMaciej W. Rozyckithe baud rate of 38400bps.  Note that the value of 0 in TCR sets the
105*7b0364eaSMaciej W. Rozyckioversampling rate to 16 and prescaler values below 1 in CPR2/CPR are
106*7b0364eaSMaciej W. Rozyckiclamped by the driver to 1.
107*7b0364eaSMaciej W. Rozycki
108*7b0364eaSMaciej W. RozyckiFor example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL
109*7b0364eaSMaciej W. Rozyckirespectively to 0x1f4, 0x0 and 0x04e2, choosing the prescaler value,
110*7b0364eaSMaciej W. Rozyckithe oversampling rate and the clock divisor of 62.500, 16 and 1250
111*7b0364eaSMaciej W. Rozyckirespectively.  These parameters will set the baud rate for the serial
112*7b0364eaSMaciej W. Rozyckiport to 62500000 / 62.500 / 1250 / 16 = 50bps.
113*7b0364eaSMaciej W. Rozycki
114*7b0364eaSMaciej W. RozyckiReferences:
115*7b0364eaSMaciej W. Rozycki
116*7b0364eaSMaciej W. Rozycki[1] "OXPCIe200 PCI Express Multi-Port Bridge", Oxford Semiconductor,
117*7b0364eaSMaciej W. Rozycki    Inc., DS-0045, 10 Nov 2008, Section "950 Mode", pp. 64-65
118*7b0364eaSMaciej W. Rozycki
119*7b0364eaSMaciej W. Rozycki[2] "OXPCIe952 PCI Express Bridge to Dual Serial & Parallel Port",
120*7b0364eaSMaciej W. Rozycki    Oxford Semiconductor, Inc., DS-0046, Mar 06 08, Section "950 Mode",
121*7b0364eaSMaciej W. Rozycki    p. 20
122*7b0364eaSMaciej W. Rozycki
123*7b0364eaSMaciej W. Rozycki[3] "OXPCIe954 PCI Express Bridge to Quad Serial Port", Oxford
124*7b0364eaSMaciej W. Rozycki    Semiconductor, Inc., DS-0047, Feb 08, Section "950 Mode", p. 20
125*7b0364eaSMaciej W. Rozycki
126*7b0364eaSMaciej W. Rozycki[4] "OXPCIe958 PCI Express Bridge to Octal Serial Port", Oxford
127*7b0364eaSMaciej W. Rozycki    Semiconductor, Inc., DS-0048, Feb 08, Section "950 Mode", p. 20
128*7b0364eaSMaciej W. Rozycki
129*7b0364eaSMaciej W. RozyckiMaciej W. Rozycki  <macro@orcam.me.uk>
130