17b0364eaSMaciej W. Rozycki.. SPDX-License-Identifier: GPL-2.0 27b0364eaSMaciej W. Rozycki 37b0364eaSMaciej W. Rozycki==================================================================== 47b0364eaSMaciej W. RozyckiNotes on Oxford Semiconductor PCIe (Tornado) 950 serial port devices 57b0364eaSMaciej W. Rozycki==================================================================== 67b0364eaSMaciej W. Rozycki 77b0364eaSMaciej W. RozyckiOxford Semiconductor PCIe (Tornado) 950 serial port devices are driven 87b0364eaSMaciej W. Rozyckiby a fixed 62.5MHz clock input derived from the 100MHz PCI Express clock. 97b0364eaSMaciej W. Rozycki 107b0364eaSMaciej W. RozyckiThe baud rate produced by the baud generator is obtained from this input 117b0364eaSMaciej W. Rozyckifrequency by dividing it by the clock prescaler, which can be set to any 127b0364eaSMaciej W. Rozyckivalue from 1 to 63.875 in increments of 0.125, and then the usual 16-bit 137b0364eaSMaciej W. Rozyckidivisor is used as with the original 8250, to divide the frequency by a 147b0364eaSMaciej W. Rozyckivalue from 1 to 65535. Finally a programmable oversampling rate is used 157b0364eaSMaciej W. Rozyckithat can take any value from 4 to 16 to divide the frequency further and 167b0364eaSMaciej W. Rozyckidetermine the actual baud rate used. Baud rates from 15625000bps down 177b0364eaSMaciej W. Rozyckito 0.933bps can be obtained this way. 187b0364eaSMaciej W. Rozycki 197b0364eaSMaciej W. RozyckiBy default the oversampling rate is set to 16 and the clock prescaler is 207b0364eaSMaciej W. Rozyckiset to 33.875, meaning that the frequency to be used as the reference 217b0364eaSMaciej W. Rozyckifor the usual 16-bit divisor is 115313.653, which is close enough to the 227b0364eaSMaciej W. Rozyckifrequency of 115200 used by the original 8250 for the same values to be 237b0364eaSMaciej W. Rozyckiused for the divisor to obtain the requested baud rates by software that 247b0364eaSMaciej W. Rozyckiis unaware of the extra clock controls available. 257b0364eaSMaciej W. Rozycki 267b0364eaSMaciej W. RozyckiThe oversampling rate is programmed with the TCR register and the clock 27*421bdf53SMaciej W. Rozyckiprescaler is programmed with the CPR/CPR2 register pair [OX200]_ [OX952]_ 28*421bdf53SMaciej W. Rozycki[OX954]_ [OX958]_. To switch away from the default value of 33.875 for 29*421bdf53SMaciej W. Rozyckithe prescaler the enhanced mode has to be explicitly enabled though, by 30*421bdf53SMaciej W. Rozyckisetting bit 4 of the EFR. In that mode setting bit 7 in the MCR enables 31*421bdf53SMaciej W. Rozyckithe prescaler or otherwise it is bypassed as if the value of 1 was used. 32*421bdf53SMaciej W. RozyckiAdditionally writing any value to CPR clears CPR2 for compatibility with 33*421bdf53SMaciej W. Rozyckiold software written for older conventional PCI Oxford Semiconductor 34*421bdf53SMaciej W. Rozyckidevices that do not have the extra prescaler's 9th bit in CPR2, so the 35*421bdf53SMaciej W. RozyckiCPR/CPR2 register pair has to be programmed in the right order. 367b0364eaSMaciej W. Rozycki 377b0364eaSMaciej W. RozyckiBy using these parameters rates from 15625000bps down to 1bps can be 387b0364eaSMaciej W. Rozyckiobtained, with either exact or highly-accurate actual bit rates for 397b0364eaSMaciej W. Rozyckistandard and many non-standard rates. 407b0364eaSMaciej W. Rozycki 417b0364eaSMaciej W. RozyckiHere are the figures for the standard and some non-standard baud rates 427b0364eaSMaciej W. Rozycki(including those quoted in Oxford Semiconductor documentation), giving 437b0364eaSMaciej W. Rozyckithe requested rate (r), the actual rate yielded (a) and its deviation 447b0364eaSMaciej W. Rozyckifrom the requested rate (d), and the values of the oversampling rate 457b0364eaSMaciej W. Rozycki(tcr), the clock prescaler (cpr) and the divisor (div) produced by the 46*421bdf53SMaciej W. Rozyckinew ``get_divisor`` handler: 47*421bdf53SMaciej W. Rozycki 48*421bdf53SMaciej W. Rozycki:: 497b0364eaSMaciej W. Rozycki 507b0364eaSMaciej W. Rozycki r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1 517b0364eaSMaciej W. Rozycki r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1 527b0364eaSMaciej W. Rozycki r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1 537b0364eaSMaciej W. Rozycki r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1 547b0364eaSMaciej W. Rozycki r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1 557b0364eaSMaciej W. Rozycki r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1 567b0364eaSMaciej W. Rozycki r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1 577b0364eaSMaciej W. Rozycki r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1 587b0364eaSMaciej W. Rozycki r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1 597b0364eaSMaciej W. Rozycki r: 2500000, a: 2500000.00, d: 0.0000%, tcr: 10, cpr: 2.500, div: 1 607b0364eaSMaciej W. Rozycki r: 2000000, a: 2000000.00, d: 0.0000%, tcr: 10, cpr: 3.125, div: 1 617b0364eaSMaciej W. Rozycki r: 1843200, a: 1838235.29, d: -0.2694%, tcr: 16, cpr: 2.125, div: 1 627b0364eaSMaciej W. Rozycki r: 1500000, a: 1492537.31, d: -0.4975%, tcr: 5, cpr: 8.375, div: 1 637b0364eaSMaciej W. Rozycki r: 1152000, a: 1152073.73, d: 0.0064%, tcr: 14, cpr: 3.875, div: 1 647b0364eaSMaciej W. Rozycki r: 921600, a: 919117.65, d: -0.2694%, tcr: 16, cpr: 2.125, div: 2 657b0364eaSMaciej W. Rozycki r: 576000, a: 576036.87, d: 0.0064%, tcr: 14, cpr: 3.875, div: 2 667b0364eaSMaciej W. Rozycki r: 460800, a: 460829.49, d: 0.0064%, tcr: 7, cpr: 3.875, div: 5 677b0364eaSMaciej W. Rozycki r: 230400, a: 230414.75, d: 0.0064%, tcr: 14, cpr: 3.875, div: 5 687b0364eaSMaciej W. Rozycki r: 115200, a: 115207.37, d: 0.0064%, tcr: 14, cpr: 1.250, div: 31 697b0364eaSMaciej W. Rozycki r: 57600, a: 57603.69, d: 0.0064%, tcr: 8, cpr: 3.875, div: 35 707b0364eaSMaciej W. Rozycki r: 38400, a: 38402.46, d: 0.0064%, tcr: 14, cpr: 3.875, div: 30 717b0364eaSMaciej W. Rozycki r: 19200, a: 19201.23, d: 0.0064%, tcr: 8, cpr: 3.875, div: 105 727b0364eaSMaciej W. Rozycki r: 9600, a: 9600.06, d: 0.0006%, tcr: 9, cpr: 1.125, div: 643 737b0364eaSMaciej W. Rozycki r: 4800, a: 4799.98, d: -0.0004%, tcr: 7, cpr: 2.875, div: 647 747b0364eaSMaciej W. Rozycki r: 2400, a: 2400.02, d: 0.0008%, tcr: 9, cpr: 2.250, div: 1286 757b0364eaSMaciej W. Rozycki r: 1200, a: 1200.00, d: 0.0000%, tcr: 14, cpr: 2.875, div: 1294 767b0364eaSMaciej W. Rozycki r: 300, a: 300.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 7215 777b0364eaSMaciej W. Rozycki r: 200, a: 200.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 15625 787b0364eaSMaciej W. Rozycki r: 150, a: 150.00, d: 0.0000%, tcr: 13, cpr: 2.250, div: 14245 797b0364eaSMaciej W. Rozycki r: 134, a: 134.00, d: 0.0000%, tcr: 11, cpr: 2.625, div: 16153 807b0364eaSMaciej W. Rozycki r: 110, a: 110.00, d: 0.0000%, tcr: 12, cpr: 1.000, div: 47348 817b0364eaSMaciej W. Rozycki r: 75, a: 75.00, d: 0.0000%, tcr: 4, cpr: 5.875, div: 35461 827b0364eaSMaciej W. Rozycki r: 50, a: 50.00, d: 0.0000%, tcr: 16, cpr: 1.250, div: 62500 837b0364eaSMaciej W. Rozycki r: 25, a: 25.00, d: 0.0000%, tcr: 16, cpr: 2.500, div: 62500 847b0364eaSMaciej W. Rozycki r: 4, a: 4.00, d: 0.0000%, tcr: 16, cpr: 20.000, div: 48828 857b0364eaSMaciej W. Rozycki r: 2, a: 2.00, d: 0.0000%, tcr: 16, cpr: 40.000, div: 48828 867b0364eaSMaciej W. Rozycki r: 1, a: 1.00, d: 0.0000%, tcr: 16, cpr: 63.875, div: 61154 877b0364eaSMaciej W. Rozycki 887b0364eaSMaciej W. RozyckiWith the baud base set to 15625000 and the unsigned 16-bit UART_DIV_MAX 89*421bdf53SMaciej W. Rozyckilimitation imposed by ``serial8250_get_baud_rate`` standard baud rates 907b0364eaSMaciej W. Rozyckibelow 300bps become unavailable in the regular way, e.g. the rate of 917b0364eaSMaciej W. Rozycki200bps requires the baud base to be divided by 78125 and that is beyond 927b0364eaSMaciej W. Rozyckithe unsigned 16-bit range. The historic spd_cust feature can still be 937b0364eaSMaciej W. Rozyckiused by encoding the values for, the prescaler, the oversampling rate 947b0364eaSMaciej W. Rozyckiand the clock divisor (DLM/DLL) as follows to obtain such rates if so 957b0364eaSMaciej W. Rozyckirequired: 967b0364eaSMaciej W. Rozycki 97*421bdf53SMaciej W. Rozycki:: 98*421bdf53SMaciej W. Rozycki 997b0364eaSMaciej W. Rozycki 31 29 28 20 19 16 15 0 1007b0364eaSMaciej W. Rozycki +-----+-----------------+-------+-------------------------------+ 1017b0364eaSMaciej W. Rozycki |0 0 0| CPR2:CPR | TCR | DLM:DLL | 1027b0364eaSMaciej W. Rozycki +-----+-----------------+-------+-------------------------------+ 1037b0364eaSMaciej W. Rozycki 104*421bdf53SMaciej W. RozyckiUse a value such encoded for the ``custom_divisor`` field along with the 105*421bdf53SMaciej W. RozyckiASYNC_SPD_CUST flag set in the ``flags`` field in ``struct serial_struct`` 1067b0364eaSMaciej W. Rozyckipassed with the TIOCSSERIAL ioctl(2), such as with the setserial(8) 107*421bdf53SMaciej W. Rozyckiutility and its ``divisor`` and ``spd_cust`` parameters, and then select 1087b0364eaSMaciej W. Rozyckithe baud rate of 38400bps. Note that the value of 0 in TCR sets the 1097b0364eaSMaciej W. Rozyckioversampling rate to 16 and prescaler values below 1 in CPR2/CPR are 1107b0364eaSMaciej W. Rozyckiclamped by the driver to 1. 1117b0364eaSMaciej W. Rozycki 1127b0364eaSMaciej W. RozyckiFor example the value of 0x1f4004e2 will set CPR2/CPR, TCR and DLM/DLL 1137b0364eaSMaciej W. Rozyckirespectively to 0x1f4, 0x0 and 0x04e2, choosing the prescaler value, 1147b0364eaSMaciej W. Rozyckithe oversampling rate and the clock divisor of 62.500, 16 and 1250 1157b0364eaSMaciej W. Rozyckirespectively. These parameters will set the baud rate for the serial 1167b0364eaSMaciej W. Rozyckiport to 62500000 / 62.500 / 1250 / 16 = 50bps. 1177b0364eaSMaciej W. Rozycki 118*421bdf53SMaciej W. RozyckiMaciej W. Rozycki <macro@orcam.me.uk> 1197b0364eaSMaciej W. Rozycki 120*421bdf53SMaciej W. Rozycki.. [OX200] "OXPCIe200 PCI Express Multi-Port Bridge", Oxford Semiconductor, 1217b0364eaSMaciej W. Rozycki Inc., DS-0045, 10 Nov 2008, Section "950 Mode", pp. 64-65 1227b0364eaSMaciej W. Rozycki 123*421bdf53SMaciej W. Rozycki.. [OX952] "OXPCIe952 PCI Express Bridge to Dual Serial & Parallel Port", 1247b0364eaSMaciej W. Rozycki Oxford Semiconductor, Inc., DS-0046, Mar 06 08, Section "950 Mode", 1257b0364eaSMaciej W. Rozycki p. 20 1267b0364eaSMaciej W. Rozycki 127*421bdf53SMaciej W. Rozycki.. [OX954] "OXPCIe954 PCI Express Bridge to Quad Serial Port", Oxford 1287b0364eaSMaciej W. Rozycki Semiconductor, Inc., DS-0047, Feb 08, Section "950 Mode", p. 20 1297b0364eaSMaciej W. Rozycki 130*421bdf53SMaciej W. Rozycki.. [OX958] "OXPCIe958 PCI Express Bridge to Octal Serial Port", Oxford 1317b0364eaSMaciej W. Rozycki Semiconductor, Inc., DS-0048, Feb 08, Section "950 Mode", p. 20 132