1*d2bdd48aSMauro Carvalho Chehab========================================================================= 2*d2bdd48aSMauro Carvalho ChehabRapidIO subsystem mport driver for IDT Tsi721 PCI Express-to-SRIO bridge. 3*d2bdd48aSMauro Carvalho Chehab========================================================================= 4*d2bdd48aSMauro Carvalho Chehab 5*d2bdd48aSMauro Carvalho Chehab1. Overview 6*d2bdd48aSMauro Carvalho Chehab=========== 7*d2bdd48aSMauro Carvalho Chehab 8*d2bdd48aSMauro Carvalho ChehabThis driver implements all currently defined RapidIO mport callback functions. 9*d2bdd48aSMauro Carvalho ChehabIt supports maintenance read and write operations, inbound and outbound RapidIO 10*d2bdd48aSMauro Carvalho Chehabdoorbells, inbound maintenance port-writes and RapidIO messaging. 11*d2bdd48aSMauro Carvalho Chehab 12*d2bdd48aSMauro Carvalho ChehabTo generate SRIO maintenance transactions this driver uses one of Tsi721 DMA 13*d2bdd48aSMauro Carvalho Chehabchannels. This mechanism provides access to larger range of hop counts and 14*d2bdd48aSMauro Carvalho Chehabdestination IDs without need for changes in outbound window translation. 15*d2bdd48aSMauro Carvalho Chehab 16*d2bdd48aSMauro Carvalho ChehabRapidIO messaging support uses dedicated messaging channels for each mailbox. 17*d2bdd48aSMauro Carvalho ChehabFor inbound messages this driver uses destination ID matching to forward messages 18*d2bdd48aSMauro Carvalho Chehabinto the corresponding message queue. Messaging callbacks are implemented to be 19*d2bdd48aSMauro Carvalho Chehabfully compatible with RIONET driver (Ethernet over RapidIO messaging services). 20*d2bdd48aSMauro Carvalho Chehab 21*d2bdd48aSMauro Carvalho Chehab1. Module parameters: 22*d2bdd48aSMauro Carvalho Chehab 23*d2bdd48aSMauro Carvalho Chehab- 'dbg_level' 24*d2bdd48aSMauro Carvalho Chehab - This parameter allows to control amount of debug information 25*d2bdd48aSMauro Carvalho Chehab generated by this device driver. This parameter is formed by set of 26*d2bdd48aSMauro Carvalho Chehab This parameter can be changed bit masks that correspond to the specific 27*d2bdd48aSMauro Carvalho Chehab functional block. 28*d2bdd48aSMauro Carvalho Chehab For mask definitions see 'drivers/rapidio/devices/tsi721.h' 29*d2bdd48aSMauro Carvalho Chehab This parameter can be changed dynamically. 30*d2bdd48aSMauro Carvalho Chehab Use CONFIG_RAPIDIO_DEBUG=y to enable debug output at the top level. 31*d2bdd48aSMauro Carvalho Chehab 32*d2bdd48aSMauro Carvalho Chehab- 'dma_desc_per_channel' 33*d2bdd48aSMauro Carvalho Chehab - This parameter defines number of hardware buffer 34*d2bdd48aSMauro Carvalho Chehab descriptors allocated for each registered Tsi721 DMA channel. 35*d2bdd48aSMauro Carvalho Chehab Its default value is 128. 36*d2bdd48aSMauro Carvalho Chehab 37*d2bdd48aSMauro Carvalho Chehab- 'dma_txqueue_sz' 38*d2bdd48aSMauro Carvalho Chehab - DMA transactions queue size. Defines number of pending 39*d2bdd48aSMauro Carvalho Chehab transaction requests that can be accepted by each DMA channel. 40*d2bdd48aSMauro Carvalho Chehab Default value is 16. 41*d2bdd48aSMauro Carvalho Chehab 42*d2bdd48aSMauro Carvalho Chehab- 'dma_sel' 43*d2bdd48aSMauro Carvalho Chehab - DMA channel selection mask. Bitmask that defines which hardware 44*d2bdd48aSMauro Carvalho Chehab DMA channels (0 ... 6) will be registered with DmaEngine core. 45*d2bdd48aSMauro Carvalho Chehab If bit is set to 1, the corresponding DMA channel will be registered. 46*d2bdd48aSMauro Carvalho Chehab DMA channels not selected by this mask will not be used by this device 47*d2bdd48aSMauro Carvalho Chehab driver. Default value is 0x7f (use all channels). 48*d2bdd48aSMauro Carvalho Chehab 49*d2bdd48aSMauro Carvalho Chehab- 'pcie_mrrs' 50*d2bdd48aSMauro Carvalho Chehab - override value for PCIe Maximum Read Request Size (MRRS). 51*d2bdd48aSMauro Carvalho Chehab This parameter gives an ability to override MRRS value set during PCIe 52*d2bdd48aSMauro Carvalho Chehab configuration process. Tsi721 supports read request sizes up to 4096B. 53*d2bdd48aSMauro Carvalho Chehab Value for this parameter must be set as defined by PCIe specification: 54*d2bdd48aSMauro Carvalho Chehab 0 = 128B, 1 = 256B, 2 = 512B, 3 = 1024B, 4 = 2048B and 5 = 4096B. 55*d2bdd48aSMauro Carvalho Chehab Default value is '-1' (= keep platform setting). 56*d2bdd48aSMauro Carvalho Chehab 57*d2bdd48aSMauro Carvalho Chehab- 'mbox_sel' 58*d2bdd48aSMauro Carvalho Chehab - RIO messaging MBOX selection mask. This is a bitmask that defines 59*d2bdd48aSMauro Carvalho Chehab messaging MBOXes are managed by this device driver. Mask bits 0 - 3 60*d2bdd48aSMauro Carvalho Chehab correspond to MBOX0 - MBOX3. MBOX is under driver's control if the 61*d2bdd48aSMauro Carvalho Chehab corresponding bit is set to '1'. Default value is 0x0f (= all). 62*d2bdd48aSMauro Carvalho Chehab 63*d2bdd48aSMauro Carvalho Chehab2. Known problems 64*d2bdd48aSMauro Carvalho Chehab================= 65*d2bdd48aSMauro Carvalho Chehab 66*d2bdd48aSMauro Carvalho Chehab None. 67*d2bdd48aSMauro Carvalho Chehab 68*d2bdd48aSMauro Carvalho Chehab3. DMA Engine Support 69*d2bdd48aSMauro Carvalho Chehab===================== 70*d2bdd48aSMauro Carvalho Chehab 71*d2bdd48aSMauro Carvalho ChehabTsi721 mport driver supports DMA data transfers between local system memory and 72*d2bdd48aSMauro Carvalho Chehabremote RapidIO devices. This functionality is implemented according to SLAVE 73*d2bdd48aSMauro Carvalho Chehabmode API defined by common Linux kernel DMA Engine framework. 74*d2bdd48aSMauro Carvalho Chehab 75*d2bdd48aSMauro Carvalho ChehabDepending on system requirements RapidIO DMA operations can be included/excluded 76*d2bdd48aSMauro Carvalho Chehabby setting CONFIG_RAPIDIO_DMA_ENGINE option. Tsi721 miniport driver uses seven 77*d2bdd48aSMauro Carvalho Chehabout of eight available BDMA channels to support DMA data transfers. 78*d2bdd48aSMauro Carvalho ChehabOne BDMA channel is reserved for generation of maintenance read/write requests. 79*d2bdd48aSMauro Carvalho Chehab 80*d2bdd48aSMauro Carvalho ChehabIf Tsi721 mport driver have been built with RAPIDIO_DMA_ENGINE support included, 81*d2bdd48aSMauro Carvalho Chehabthis driver will accept DMA-specific module parameter: 82*d2bdd48aSMauro Carvalho Chehab 83*d2bdd48aSMauro Carvalho Chehab "dma_desc_per_channel" 84*d2bdd48aSMauro Carvalho Chehab - defines number of hardware buffer descriptors used by 85*d2bdd48aSMauro Carvalho Chehab each BDMA channel of Tsi721 (by default - 128). 86*d2bdd48aSMauro Carvalho Chehab 87*d2bdd48aSMauro Carvalho Chehab4. Version History 88*d2bdd48aSMauro Carvalho Chehab 89*d2bdd48aSMauro Carvalho Chehab ===== ==================================================================== 90*d2bdd48aSMauro Carvalho Chehab 1.1.0 DMA operations re-worked to support data scatter/gather lists larger 91*d2bdd48aSMauro Carvalho Chehab than hardware buffer descriptors ring. 92*d2bdd48aSMauro Carvalho Chehab 1.0.0 Initial driver release. 93*d2bdd48aSMauro Carvalho Chehab ===== ==================================================================== 94*d2bdd48aSMauro Carvalho Chehab 95*d2bdd48aSMauro Carvalho Chehab5. License 96*d2bdd48aSMauro Carvalho Chehab=========== 97*d2bdd48aSMauro Carvalho Chehab 98*d2bdd48aSMauro Carvalho Chehab Copyright(c) 2011 Integrated Device Technology, Inc. All rights reserved. 99*d2bdd48aSMauro Carvalho Chehab 100*d2bdd48aSMauro Carvalho Chehab This program is free software; you can redistribute it and/or modify it 101*d2bdd48aSMauro Carvalho Chehab under the terms of the GNU General Public License as published by the Free 102*d2bdd48aSMauro Carvalho Chehab Software Foundation; either version 2 of the License, or (at your option) 103*d2bdd48aSMauro Carvalho Chehab any later version. 104*d2bdd48aSMauro Carvalho Chehab 105*d2bdd48aSMauro Carvalho Chehab This program is distributed in the hope that it will be useful, but WITHOUT 106*d2bdd48aSMauro Carvalho Chehab ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 107*d2bdd48aSMauro Carvalho Chehab FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 108*d2bdd48aSMauro Carvalho Chehab more details. 109*d2bdd48aSMauro Carvalho Chehab 110*d2bdd48aSMauro Carvalho Chehab You should have received a copy of the GNU General Public License along with 111*d2bdd48aSMauro Carvalho Chehab this program; if not, write to the Free Software Foundation, Inc., 112*d2bdd48aSMauro Carvalho Chehab 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 113