1547b822cSAlan TullFPGA Manager 2547b822cSAlan Tull============ 3547b822cSAlan Tull 4547b822cSAlan TullOverview 5547b822cSAlan Tull-------- 6547b822cSAlan Tull 7547b822cSAlan TullThe FPGA manager core exports a set of functions for programming an FPGA with 8547b822cSAlan Tullan image. The API is manufacturer agnostic. All manufacturer specifics are 9547b822cSAlan Tullhidden away in a low level driver which registers a set of ops with the core. 10547b822cSAlan TullThe FPGA image data itself is very manufacturer specific, but for our purposes 11547b822cSAlan Tullit's just binary data. The FPGA manager core won't parse it. 12547b822cSAlan Tull 13547b822cSAlan TullThe FPGA image to be programmed can be in a scatter gather list, a single 14547b822cSAlan Tullcontiguous buffer, or a firmware file. Because allocating contiguous kernel 15547b822cSAlan Tullmemory for the buffer should be avoided, users are encouraged to use a scatter 16547b822cSAlan Tullgather list instead if possible. 17547b822cSAlan Tull 18547b822cSAlan TullThe particulars for programming the image are presented in a structure (struct 19547b822cSAlan Tullfpga_image_info). This struct contains parameters such as pointers to the 20547b822cSAlan TullFPGA image as well as image-specific particulars such as whether the image was 21547b822cSAlan Tullbuilt for full or partial reconfiguration. 22547b822cSAlan Tull 23547b822cSAlan TullHow to support a new FPGA device 24547b822cSAlan Tull-------------------------------- 25547b822cSAlan Tull 26547b822cSAlan TullTo add another FPGA manager, write a driver that implements a set of ops. The 27*2da62a13SMarco Paganiprobe function calls ``fpga_mgr_register()`` or ``fpga_mgr_register_full()``, 28*2da62a13SMarco Paganisuch as:: 29547b822cSAlan Tull 30547b822cSAlan Tull static const struct fpga_manager_ops socfpga_fpga_ops = { 31547b822cSAlan Tull .write_init = socfpga_fpga_ops_configure_init, 32547b822cSAlan Tull .write = socfpga_fpga_ops_configure_write, 33547b822cSAlan Tull .write_complete = socfpga_fpga_ops_configure_complete, 34547b822cSAlan Tull .state = socfpga_fpga_ops_state, 35547b822cSAlan Tull }; 36547b822cSAlan Tull 37547b822cSAlan Tull static int socfpga_fpga_probe(struct platform_device *pdev) 38547b822cSAlan Tull { 39547b822cSAlan Tull struct device *dev = &pdev->dev; 40547b822cSAlan Tull struct socfpga_fpga_priv *priv; 41547b822cSAlan Tull struct fpga_manager *mgr; 42547b822cSAlan Tull int ret; 43547b822cSAlan Tull 44547b822cSAlan Tull priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 45547b822cSAlan Tull if (!priv) 46547b822cSAlan Tull return -ENOMEM; 47547b822cSAlan Tull 48547b822cSAlan Tull /* 49547b822cSAlan Tull * do ioremaps, get interrupts, etc. and save 50547b822cSAlan Tull * them in priv 51547b822cSAlan Tull */ 52547b822cSAlan Tull 534ba0b2c2SRuss Weight mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager", 54547b822cSAlan Tull &socfpga_fpga_ops, priv); 554ba0b2c2SRuss Weight if (IS_ERR(mgr)) 564ba0b2c2SRuss Weight return PTR_ERR(mgr); 57547b822cSAlan Tull 58547b822cSAlan Tull platform_set_drvdata(pdev, mgr); 59547b822cSAlan Tull 604ba0b2c2SRuss Weight return 0; 61547b822cSAlan Tull } 62547b822cSAlan Tull 63547b822cSAlan Tull static int socfpga_fpga_remove(struct platform_device *pdev) 64547b822cSAlan Tull { 65547b822cSAlan Tull struct fpga_manager *mgr = platform_get_drvdata(pdev); 66547b822cSAlan Tull 67547b822cSAlan Tull fpga_mgr_unregister(mgr); 68547b822cSAlan Tull 69547b822cSAlan Tull return 0; 70547b822cSAlan Tull } 71547b822cSAlan Tull 724ba0b2c2SRuss WeightAlternatively, the probe function could call one of the resource managed 73*2da62a13SMarco Paganiregister functions, ``devm_fpga_mgr_register()`` or 74*2da62a13SMarco Pagani``devm_fpga_mgr_register_full()``. When these functions are used, the 75*2da62a13SMarco Paganiparameter syntax is the same, but the call to ``fpga_mgr_unregister()`` should be 76*2da62a13SMarco Paganiremoved. In the above example, the ``socfpga_fpga_remove()`` function would not be 77*2da62a13SMarco Paganirequired. 78547b822cSAlan Tull 79547b822cSAlan TullThe ops will implement whatever device specific register writes are needed to 80547b822cSAlan Tulldo the programming sequence for this particular FPGA. These ops return 0 for 81547b822cSAlan Tullsuccess or negative error codes otherwise. 82547b822cSAlan Tull 83547b822cSAlan TullThe programming sequence is:: 84288cc44bSIvan Bornyakov 1. .parse_header (optional, may be called once or multiple times) 85288cc44bSIvan Bornyakov 2. .write_init 86288cc44bSIvan Bornyakov 3. .write or .write_sg (may be called once or multiple times) 87288cc44bSIvan Bornyakov 4. .write_complete 88288cc44bSIvan Bornyakov 89288cc44bSIvan BornyakovThe .parse_header function will set header_size and data_size to 90288cc44bSIvan Bornyakovstruct fpga_image_info. Before parse_header call, header_size is initialized 91288cc44bSIvan Bornyakovwith initial_header_size. If flag skip_header of fpga_manager_ops is true, 92288cc44bSIvan Bornyakov.write function will get image buffer starting at header_size offset from the 93288cc44bSIvan Bornyakovbeginning. If data_size is set, .write function will get data_size bytes of 94288cc44bSIvan Bornyakovthe image buffer, otherwise .write will get data up to the end of image buffer. 95288cc44bSIvan BornyakovThis will not affect .write_sg, .write_sg will still get whole image in 96288cc44bSIvan Bornyakovsg_table form. If FPGA image is already mapped as a single contiguous buffer, 97288cc44bSIvan Bornyakovwhole buffer will be passed into .parse_header. If image is in scatter-gather 98288cc44bSIvan Bornyakovform, core code will buffer up at least .initial_header_size before the first 99288cc44bSIvan Bornyakovcall of .parse_header, if it is not enough, .parse_header should set desired 100288cc44bSIvan Bornyakovsize into info->header_size and return -EAGAIN, then it will be called again 101288cc44bSIvan Bornyakovwith greater part of image buffer on the input. 102547b822cSAlan Tull 103547b822cSAlan TullThe .write_init function will prepare the FPGA to receive the image data. The 104288cc44bSIvan Bornyakovbuffer passed into .write_init will be at least info->header_size bytes long; 105547b822cSAlan Tullif the whole bitstream is not immediately available then the core code will 106547b822cSAlan Tullbuffer up at least this much before starting. 107547b822cSAlan Tull 108547b822cSAlan TullThe .write function writes a buffer to the FPGA. The buffer may be contain the 109547b822cSAlan Tullwhole FPGA image or may be a smaller chunk of an FPGA image. In the latter 110547b822cSAlan Tullcase, this function is called multiple times for successive chunks. This interface 111547b822cSAlan Tullis suitable for drivers which use PIO. 112547b822cSAlan Tull 113547b822cSAlan TullThe .write_sg version behaves the same as .write except the input is a sg_table 114547b822cSAlan Tullscatter list. This interface is suitable for drivers which use DMA. 115547b822cSAlan Tull 116547b822cSAlan TullThe .write_complete function is called after all the image has been written 117547b822cSAlan Tullto put the FPGA into operating mode. 118547b822cSAlan Tull 119a59f95c7SAlan TullThe ops include a .state function which will determine the state the FPGA is in 120a59f95c7SAlan Tulland return a code of type enum fpga_mgr_states. It doesn't result in a change 121a59f95c7SAlan Tullin state. 122547b822cSAlan Tull 123547b822cSAlan TullAPI for implementing a new FPGA Manager driver 124547b822cSAlan Tull---------------------------------------------- 125547b822cSAlan Tull 126758f7467SMauro Carvalho Chehab* ``fpga_mgr_states`` - Values for :c:expr:`fpga_manager->state`. 127758f7467SMauro Carvalho Chehab* struct fpga_manager - the FPGA manager struct 128758f7467SMauro Carvalho Chehab* struct fpga_manager_ops - Low level FPGA manager driver ops 1294ba0b2c2SRuss Weight* struct fpga_manager_info - Parameter structure for fpga_mgr_register_full() 130*2da62a13SMarco Pagani* __fpga_mgr_register_full() - Create and register an FPGA manager using the 1314ba0b2c2SRuss Weight fpga_mgr_info structure to provide the full flexibility of options 132*2da62a13SMarco Pagani* __fpga_mgr_register() - Create and register an FPGA manager using standard 1334ba0b2c2SRuss Weight arguments 134*2da62a13SMarco Pagani* __devm_fpga_mgr_register_full() - Resource managed version of 135*2da62a13SMarco Pagani __fpga_mgr_register_full() 136*2da62a13SMarco Pagani* __devm_fpga_mgr_register() - Resource managed version of __fpga_mgr_register() 137758f7467SMauro Carvalho Chehab* fpga_mgr_unregister() - Unregister an FPGA manager 1384a6ff3c9SAlan Tull 139*2da62a13SMarco PaganiHelper macros ``fpga_mgr_register_full()``, ``fpga_mgr_register()``, 140*2da62a13SMarco Pagani``devm_fpga_mgr_register_full()``, and ``devm_fpga_mgr_register()`` are available 141*2da62a13SMarco Paganito ease the registration. 142*2da62a13SMarco Pagani 1434a6ff3c9SAlan Tull.. kernel-doc:: include/linux/fpga/fpga-mgr.h 1444a6ff3c9SAlan Tull :functions: fpga_mgr_states 1454a6ff3c9SAlan Tull 146547b822cSAlan Tull.. kernel-doc:: include/linux/fpga/fpga-mgr.h 147547b822cSAlan Tull :functions: fpga_manager 148547b822cSAlan Tull 149547b822cSAlan Tull.. kernel-doc:: include/linux/fpga/fpga-mgr.h 150547b822cSAlan Tull :functions: fpga_manager_ops 151547b822cSAlan Tull 1524ba0b2c2SRuss Weight.. kernel-doc:: include/linux/fpga/fpga-mgr.h 1534ba0b2c2SRuss Weight :functions: fpga_manager_info 1544ba0b2c2SRuss Weight 155547b822cSAlan Tull.. kernel-doc:: drivers/fpga/fpga-mgr.c 156*2da62a13SMarco Pagani :functions: __fpga_mgr_register_full 157084181feSAlan Tull 158084181feSAlan Tull.. kernel-doc:: drivers/fpga/fpga-mgr.c 159*2da62a13SMarco Pagani :functions: __fpga_mgr_register 160547b822cSAlan Tull 161547b822cSAlan Tull.. kernel-doc:: drivers/fpga/fpga-mgr.c 162*2da62a13SMarco Pagani :functions: __devm_fpga_mgr_register_full 1634ba0b2c2SRuss Weight 1644ba0b2c2SRuss Weight.. kernel-doc:: drivers/fpga/fpga-mgr.c 165*2da62a13SMarco Pagani :functions: __devm_fpga_mgr_register 1664ba0b2c2SRuss Weight 1674ba0b2c2SRuss Weight.. kernel-doc:: drivers/fpga/fpga-mgr.c 168547b822cSAlan Tull :functions: fpga_mgr_unregister 169