xref: /openbmc/linux/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml (revision 65eba0db22743320376498555d0c47d65b400d53) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung Exynos SoC Multi Core Timer (MCT)
8
9maintainers:
10  - Krzysztof Kozlowski <krzk@kernel.org>
11
12description: |+
13  The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
14  global timer and CPU local timers. The global timer is a 64-bit free running
15  up-counter and can generate 4 interrupts when the counter reaches one of the
16  four preset counter values. The CPU local timers are 32-bit free running
17  down-counters and generate an interrupt when the counter expires. There is
18  one CPU local timer instantiated in MCT for every CPU in the system.
19
20properties:
21  compatible:
22    enum:
23      - samsung,exynos4210-mct
24      - samsung,exynos4412-mct
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    description: |
31      Interrupts should be put in specific order. This is, the local timer
32      interrupts should be specified after the four global timer interrupts
33      have been specified:
34      0: Global Timer Interrupt 0
35      1: Global Timer Interrupt 1
36      2: Global Timer Interrupt 2
37      3: Global Timer Interrupt 3
38      4: Local Timer Interrupt 0
39      5: Local Timer Interrupt 1
40      6: ..
41      7: ..
42      i: Local Timer Interrupt n
43      For MCT block that uses a per-processor interrupt for local timers, such
44      as ones compatible with "samsung,exynos4412-mct", only one local timer
45      interrupt might be specified, meaning that all local timers use the same
46      per processor interrupt.
47    minItems: 5               # 4 Global + 1 local
48    maxItems: 20              # 4 Global + 16 local
49
50required:
51  - compatible
52  - interrupts
53  - reg
54
55examples:
56  - |
57    // In this example, the IP contains two local timers, using separate
58    // interrupts, so two local timer interrupts have been specified,
59    // in addition to four global timer interrupts.
60
61    timer@10050000 {
62        compatible = "samsung,exynos4210-mct";
63        reg = <0x10050000 0x800>;
64        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
65                     <0 42 0>, <0 48 0>;
66    };
67
68  - |
69    // In this example, the timer interrupts are connected to two separate
70    // interrupt controllers. Hence, an interrupts-extended is needed.
71
72    timer@101c0000 {
73        compatible = "samsung,exynos4210-mct";
74        reg = <0x101C0000 0x800>;
75        interrupts-extended = <&gic 0 57 0>,
76                              <&gic 0 69 0>,
77                              <&combiner 12 6>,
78                              <&combiner 12 7>,
79                              <&gic 0 42 0>,
80                              <&gic 0 48 0>;
81    };
82
83  - |
84    // In this example, the IP contains four local timers, but using
85    // a per-processor interrupt to handle them. Only one first local
86    // interrupt is specified.
87
88    timer@10050000 {
89        compatible = "samsung,exynos4412-mct";
90        reg = <0x10050000 0x800>;
91
92        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
93                     <0 42 0>;
94    };
95
96  - |
97    // In this example, the IP contains four local timers, but using
98    // a per-processor interrupt to handle them. All the local timer
99    // interrupts are specified.
100
101    timer@10050000 {
102        compatible = "samsung,exynos4412-mct";
103        reg = <0x10050000 0x800>;
104
105        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
106                     <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;
107    };
108