xref: /openbmc/linux/Documentation/devicetree/bindings/timer/arm,sp804.yaml (revision a85a4aa32ab9568751b7aff8bd33e1b44b1cd3a1) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM sp804 Dual Timers
8
9maintainers:
10  - Haojian Zhuang <haojian.zhuang@linaro.org>
11
12description: |+
13  The Arm SP804 IP implements two independent timers, configurable for
14  16 or 32 bit operation and capable of running in one-shot, periodic, or
15  free-running mode. The input clock is shared, but can be gated and prescaled
16  independently for each timer.
17
18# Need a custom select here or 'arm,primecell' will match on lots of nodes
19select:
20  properties:
21    compatible:
22      contains:
23        const: arm,sp804
24  required:
25    - compatible
26
27properties:
28  compatible:
29    items:
30      - const: arm,sp804
31      - const: arm,primecell
32
33  interrupts:
34    description: |
35      If two interrupts are listed, those are the interrupts for timer
36      1 and 2, respectively. If there is only a single interrupt, it is
37      either a combined interrupt or the sole interrupt of one timer, as
38      specified by the "arm,sp804-has-irq" property.
39    minItems: 1
40    maxItems: 2
41
42  reg:
43    description: The physical base address of the SP804 IP.
44    maxItems: 1
45
46  clocks:
47    description: |
48      Clocks driving the dual timer hardware. This list should
49      be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
50      clock, apb_pclk. A single clock can also be specified if the same
51      clock is used for all clock inputs.
52    oneOf:
53      - items:
54        - description: clock for timer 1
55        - description: clock for timer 2
56        - description: bus clock
57      - items:
58        - description: unified clock for both timers and the bus
59
60  clock-names: true
61    # The original binding did not specify any clock names, and there is no
62    # consistent naming used in the existing DTs. The primecell binding
63    # requires the "apb_pclk" name, so we need this property.
64    # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.
65
66  arm,sp804-has-irq:
67    description: If only one interrupt line is connected to the interrupt
68      controller, this property specifies which timer is connected to this
69      line.
70    $ref: /schemas/types.yaml#/definitions/uint32
71    minimum: 1
72    maximum: 2
73
74required:
75  - compatible
76  - interrupts
77  - reg
78  - clocks
79
80additionalProperties: false
81
82examples:
83  - |
84    timer0: timer@fc800000 {
85        compatible = "arm,sp804", "arm,primecell";
86        reg = <0xfc800000 0x1000>;
87        interrupts = <0 0 4>, <0 1 4>;
88        clocks = <&timclk1>, <&timclk2>, <&pclk>;
89        clock-names = "timer1", "timer2", "apb_pclk";
90    };
91