xref: /openbmc/linux/Documentation/devicetree/bindings/timer/arm,sp804.yaml (revision a85a4aa32ab9568751b7aff8bd33e1b44b1cd3a1)
1*a85a4aa3SAndre Przywara# SPDX-License-Identifier: GPL-2.0
2*a85a4aa3SAndre Przywara%YAML 1.2
3*a85a4aa3SAndre Przywara---
4*a85a4aa3SAndre Przywara$id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
5*a85a4aa3SAndre Przywara$schema: http://devicetree.org/meta-schemas/core.yaml#
6*a85a4aa3SAndre Przywara
7*a85a4aa3SAndre Przywaratitle: ARM sp804 Dual Timers
8*a85a4aa3SAndre Przywara
9*a85a4aa3SAndre Przywaramaintainers:
10*a85a4aa3SAndre Przywara  - Haojian Zhuang <haojian.zhuang@linaro.org>
11*a85a4aa3SAndre Przywara
12*a85a4aa3SAndre Przywaradescription: |+
13*a85a4aa3SAndre Przywara  The Arm SP804 IP implements two independent timers, configurable for
14*a85a4aa3SAndre Przywara  16 or 32 bit operation and capable of running in one-shot, periodic, or
15*a85a4aa3SAndre Przywara  free-running mode. The input clock is shared, but can be gated and prescaled
16*a85a4aa3SAndre Przywara  independently for each timer.
17*a85a4aa3SAndre Przywara
18*a85a4aa3SAndre Przywara# Need a custom select here or 'arm,primecell' will match on lots of nodes
19*a85a4aa3SAndre Przywaraselect:
20*a85a4aa3SAndre Przywara  properties:
21*a85a4aa3SAndre Przywara    compatible:
22*a85a4aa3SAndre Przywara      contains:
23*a85a4aa3SAndre Przywara        const: arm,sp804
24*a85a4aa3SAndre Przywara  required:
25*a85a4aa3SAndre Przywara    - compatible
26*a85a4aa3SAndre Przywara
27*a85a4aa3SAndre Przywaraproperties:
28*a85a4aa3SAndre Przywara  compatible:
29*a85a4aa3SAndre Przywara    items:
30*a85a4aa3SAndre Przywara      - const: arm,sp804
31*a85a4aa3SAndre Przywara      - const: arm,primecell
32*a85a4aa3SAndre Przywara
33*a85a4aa3SAndre Przywara  interrupts:
34*a85a4aa3SAndre Przywara    description: |
35*a85a4aa3SAndre Przywara      If two interrupts are listed, those are the interrupts for timer
36*a85a4aa3SAndre Przywara      1 and 2, respectively. If there is only a single interrupt, it is
37*a85a4aa3SAndre Przywara      either a combined interrupt or the sole interrupt of one timer, as
38*a85a4aa3SAndre Przywara      specified by the "arm,sp804-has-irq" property.
39*a85a4aa3SAndre Przywara    minItems: 1
40*a85a4aa3SAndre Przywara    maxItems: 2
41*a85a4aa3SAndre Przywara
42*a85a4aa3SAndre Przywara  reg:
43*a85a4aa3SAndre Przywara    description: The physical base address of the SP804 IP.
44*a85a4aa3SAndre Przywara    maxItems: 1
45*a85a4aa3SAndre Przywara
46*a85a4aa3SAndre Przywara  clocks:
47*a85a4aa3SAndre Przywara    description: |
48*a85a4aa3SAndre Przywara      Clocks driving the dual timer hardware. This list should
49*a85a4aa3SAndre Przywara      be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
50*a85a4aa3SAndre Przywara      clock, apb_pclk. A single clock can also be specified if the same
51*a85a4aa3SAndre Przywara      clock is used for all clock inputs.
52*a85a4aa3SAndre Przywara    oneOf:
53*a85a4aa3SAndre Przywara      - items:
54*a85a4aa3SAndre Przywara        - description: clock for timer 1
55*a85a4aa3SAndre Przywara        - description: clock for timer 2
56*a85a4aa3SAndre Przywara        - description: bus clock
57*a85a4aa3SAndre Przywara      - items:
58*a85a4aa3SAndre Przywara        - description: unified clock for both timers and the bus
59*a85a4aa3SAndre Przywara
60*a85a4aa3SAndre Przywara  clock-names: true
61*a85a4aa3SAndre Przywara    # The original binding did not specify any clock names, and there is no
62*a85a4aa3SAndre Przywara    # consistent naming used in the existing DTs. The primecell binding
63*a85a4aa3SAndre Przywara    # requires the "apb_pclk" name, so we need this property.
64*a85a4aa3SAndre Przywara    # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.
65*a85a4aa3SAndre Przywara
66*a85a4aa3SAndre Przywara  arm,sp804-has-irq:
67*a85a4aa3SAndre Przywara    description: If only one interrupt line is connected to the interrupt
68*a85a4aa3SAndre Przywara      controller, this property specifies which timer is connected to this
69*a85a4aa3SAndre Przywara      line.
70*a85a4aa3SAndre Przywara    $ref: /schemas/types.yaml#/definitions/uint32
71*a85a4aa3SAndre Przywara    minimum: 1
72*a85a4aa3SAndre Przywara    maximum: 2
73*a85a4aa3SAndre Przywara
74*a85a4aa3SAndre Przywararequired:
75*a85a4aa3SAndre Przywara  - compatible
76*a85a4aa3SAndre Przywara  - interrupts
77*a85a4aa3SAndre Przywara  - reg
78*a85a4aa3SAndre Przywara  - clocks
79*a85a4aa3SAndre Przywara
80*a85a4aa3SAndre PrzywaraadditionalProperties: false
81*a85a4aa3SAndre Przywara
82*a85a4aa3SAndre Przywaraexamples:
83*a85a4aa3SAndre Przywara  - |
84*a85a4aa3SAndre Przywara    timer0: timer@fc800000 {
85*a85a4aa3SAndre Przywara        compatible = "arm,sp804", "arm,primecell";
86*a85a4aa3SAndre Przywara        reg = <0xfc800000 0x1000>;
87*a85a4aa3SAndre Przywara        interrupts = <0 0 4>, <0 1 4>;
88*a85a4aa3SAndre Przywara        clocks = <&timclk1>, <&timclk2>, <&pclk>;
89*a85a4aa3SAndre Przywara        clock-names = "timer1", "timer2", "apb_pclk";
90*a85a4aa3SAndre Przywara    };
91