1f15e60d4SChunyan Zhang# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2f15e60d4SChunyan Zhang%YAML 1.2 3f15e60d4SChunyan Zhang--- 4*99a7fa0eSKrzysztof Kozlowski$id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml# 5*99a7fa0eSKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml# 6f15e60d4SChunyan Zhang 7f15e60d4SChunyan Zhangtitle: Spreadtrum ADI controller 8f15e60d4SChunyan Zhang 9f15e60d4SChunyan Zhangmaintainers: 10f15e60d4SChunyan Zhang - Orson Zhai <orsonzhai@gmail.com> 11f15e60d4SChunyan Zhang - Baolin Wang <baolin.wang7@gmail.com> 12f15e60d4SChunyan Zhang - Chunyan Zhang <zhang.lyra@gmail.com> 13f15e60d4SChunyan Zhang 14f15e60d4SChunyan Zhangdescription: | 15f15e60d4SChunyan Zhang ADI is the abbreviation of Anolog-Digital interface, which is used to access 16f15e60d4SChunyan Zhang analog chip (such as PMIC) from digital chip. ADI controller follows the SPI 17f15e60d4SChunyan Zhang framework for its hardware implementation is alike to SPI bus and its timing 18f15e60d4SChunyan Zhang is compatile to SPI timing. 19f15e60d4SChunyan Zhang 20f15e60d4SChunyan Zhang ADI controller has 50 channels including 2 software read/write channels and 21f15e60d4SChunyan Zhang 48 hardware channels to access analog chip. For 2 software read/write channels, 22f15e60d4SChunyan Zhang users should set ADI registers to access analog chip. For hardware channels, 23f15e60d4SChunyan Zhang we can configure them to allow other hardware components to use it independently, 24f15e60d4SChunyan Zhang which means we can just link one analog chip address to one hardware channel, 25f15e60d4SChunyan Zhang then users can access the mapped analog chip address by this hardware channel 26f15e60d4SChunyan Zhang triggered by hardware components instead of ADI software channels. 27f15e60d4SChunyan Zhang 28f15e60d4SChunyan Zhang Thus we introduce one property named "sprd,hw-channels" to configure hardware 29f15e60d4SChunyan Zhang channels, the first value specifies the hardware channel id which is used to 30f15e60d4SChunyan Zhang transfer data triggered by hardware automatically, and the second value specifies 31f15e60d4SChunyan Zhang the analog chip address where user want to access by hardware components. 32f15e60d4SChunyan Zhang 33f15e60d4SChunyan Zhang Since we have multi-subsystems will use unique ADI to access analog chip, when 34f15e60d4SChunyan Zhang one system is reading/writing data by ADI software channels, that should be under 35f15e60d4SChunyan Zhang one hardware spinlock protection to prevent other systems from reading/writing 36f15e60d4SChunyan Zhang data by ADI software channels at the same time, or two parallel routine of setting 37f15e60d4SChunyan Zhang ADI registers will make ADI controller registers chaos to lead incorrect results. 38f15e60d4SChunyan Zhang Then we need one hardware spinlock to synchronize between the multiple subsystems. 39f15e60d4SChunyan Zhang 40f15e60d4SChunyan Zhang The new version ADI controller supplies multiple master channels for different 41f15e60d4SChunyan Zhang subsystem accessing, that means no need to add hardware spinlock to synchronize, 42f15e60d4SChunyan Zhang thus change the hardware spinlock support to be optional to keep backward 43f15e60d4SChunyan Zhang compatibility. 44f15e60d4SChunyan Zhang 45f15e60d4SChunyan ZhangallOf: 4622a41e9aSRob Herring - $ref: /schemas/spi/spi-controller.yaml# 47f15e60d4SChunyan Zhang 48f15e60d4SChunyan Zhangproperties: 49f15e60d4SChunyan Zhang compatible: 50f15e60d4SChunyan Zhang enum: 51f15e60d4SChunyan Zhang - sprd,sc9860-adi 520f887ac8SChunyan Zhang - sprd,sc9863-adi 530f887ac8SChunyan Zhang - sprd,ums512-adi 54f15e60d4SChunyan Zhang 55f15e60d4SChunyan Zhang reg: 56f15e60d4SChunyan Zhang maxItems: 1 57f15e60d4SChunyan Zhang 58f15e60d4SChunyan Zhang hwlocks: 59f15e60d4SChunyan Zhang maxItems: 1 60f15e60d4SChunyan Zhang 61f15e60d4SChunyan Zhang hwlock-names: 62f15e60d4SChunyan Zhang const: adi 63f15e60d4SChunyan Zhang 64f15e60d4SChunyan Zhang sprd,hw-channels: 65f15e60d4SChunyan Zhang $ref: /schemas/types.yaml#/definitions/uint32-matrix 66f15e60d4SChunyan Zhang description: A list of hardware channels 67f15e60d4SChunyan Zhang minItems: 1 68f15e60d4SChunyan Zhang maxItems: 48 69f15e60d4SChunyan Zhang items: 70f15e60d4SChunyan Zhang items: 71f15e60d4SChunyan Zhang - description: The hardware channel id which is used to transfer data 72f15e60d4SChunyan Zhang triggered by hardware automatically, channel id 0-1 are for software 73f15e60d4SChunyan Zhang use, 2-49 are hardware channels. 74f15e60d4SChunyan Zhang minimum: 2 75f15e60d4SChunyan Zhang maximum: 49 76f15e60d4SChunyan Zhang - description: The analog chip address where user want to access by 77f15e60d4SChunyan Zhang hardware components. 78f15e60d4SChunyan Zhang 79f15e60d4SChunyan Zhangrequired: 80f15e60d4SChunyan Zhang - compatible 81f15e60d4SChunyan Zhang - reg 82f15e60d4SChunyan Zhang - '#address-cells' 83f15e60d4SChunyan Zhang - '#size-cells' 84f15e60d4SChunyan Zhang 85f15e60d4SChunyan ZhangunevaluatedProperties: false 86f15e60d4SChunyan Zhang 87f15e60d4SChunyan Zhangexamples: 88f15e60d4SChunyan Zhang - | 89f15e60d4SChunyan Zhang aon { 90f15e60d4SChunyan Zhang #address-cells = <2>; 91f15e60d4SChunyan Zhang #size-cells = <2>; 92f15e60d4SChunyan Zhang 93f15e60d4SChunyan Zhang adi_bus: spi@40030000 { 94f15e60d4SChunyan Zhang compatible = "sprd,sc9860-adi"; 95f15e60d4SChunyan Zhang reg = <0 0x40030000 0 0x10000>; 96f15e60d4SChunyan Zhang hwlocks = <&hwlock1 0>; 97f15e60d4SChunyan Zhang hwlock-names = "adi"; 98f15e60d4SChunyan Zhang #address-cells = <1>; 99f15e60d4SChunyan Zhang #size-cells = <0>; 100f15e60d4SChunyan Zhang sprd,hw-channels = <30 0x8c20>; 101f15e60d4SChunyan Zhang }; 102f15e60d4SChunyan Zhang }; 103f15e60d4SChunyan Zhang... 104