1cc0f6e96SRob Herring# SPDX-License-Identifier: GPL-2.0 2cc0f6e96SRob Herring%YAML 1.2 3cc0f6e96SRob Herring--- 4cc0f6e96SRob Herring$id: http://devicetree.org/schemas/spi/spi-pl022.yaml# 5cc0f6e96SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6cc0f6e96SRob Herring 7cc0f6e96SRob Herringtitle: ARM PL022 SPI controller 8cc0f6e96SRob Herring 9cc0f6e96SRob Herringmaintainers: 10cc0f6e96SRob Herring - Linus Walleij <linus.walleij@linaro.org> 11cc0f6e96SRob Herring 12cc0f6e96SRob HerringallOf: 13cc0f6e96SRob Herring - $ref: "spi-controller.yaml#" 14cc0f6e96SRob Herring 15cc0f6e96SRob Herring# We need a select here so we don't match all nodes with 'arm,primecell' 16cc0f6e96SRob Herringselect: 17cc0f6e96SRob Herring properties: 18cc0f6e96SRob Herring compatible: 19cc0f6e96SRob Herring contains: 20cc0f6e96SRob Herring const: arm,pl022 21cc0f6e96SRob Herring required: 22cc0f6e96SRob Herring - compatible 23cc0f6e96SRob Herring 24cc0f6e96SRob Herringproperties: 25cc0f6e96SRob Herring compatible: 26cc0f6e96SRob Herring items: 27cc0f6e96SRob Herring - const: arm,pl022 28cc0f6e96SRob Herring - const: arm,primecell 29cc0f6e96SRob Herring 30cc0f6e96SRob Herring reg: 31cc0f6e96SRob Herring maxItems: 1 32cc0f6e96SRob Herring 33cc0f6e96SRob Herring interrupts: 34cc0f6e96SRob Herring maxItems: 1 35cc0f6e96SRob Herring 36cc0f6e96SRob Herring clocks: 37cc0f6e96SRob Herring maxItems: 2 38cc0f6e96SRob Herring 39cc0f6e96SRob Herring clock-names: 40cc0f6e96SRob Herring items: 41cc0f6e96SRob Herring - enum: 42cc0f6e96SRob Herring - SSPCLK 43cc0f6e96SRob Herring - sspclk 44cc0f6e96SRob Herring - const: apb_pclk 45cc0f6e96SRob Herring 46cc0f6e96SRob Herring pl022,autosuspend-delay: 47cc0f6e96SRob Herring description: delay in ms following transfer completion before the 48cc0f6e96SRob Herring runtime power management system suspends the device. A setting of 0 49cc0f6e96SRob Herring indicates no delay and the device will be suspended immediately. 50cc0f6e96SRob Herring $ref: "/schemas/types.yaml#/definitions/uint32" 51cc0f6e96SRob Herring 52cc0f6e96SRob Herring pl022,rt: 53cc0f6e96SRob Herring description: indicates the controller should run the message pump with realtime 54cc0f6e96SRob Herring priority to minimise the transfer latency on the bus (boolean) 55cc0f6e96SRob Herring type: boolean 56cc0f6e96SRob Herring 57cc0f6e96SRob Herring dmas: 58cc0f6e96SRob Herring description: 59cc0f6e96SRob Herring Two or more DMA channel specifiers following the convention outlined 60cc0f6e96SRob Herring in bindings/dma/dma.txt 61cc0f6e96SRob Herring minItems: 2 62cc0f6e96SRob Herring maxItems: 32 63cc0f6e96SRob Herring 64cc0f6e96SRob Herring dma-names: 65cc0f6e96SRob Herring description: 66cc0f6e96SRob Herring There must be at least one channel named "tx" for transmit and named "rx" 67cc0f6e96SRob Herring for receive. 68cc0f6e96SRob Herring minItems: 2 69cc0f6e96SRob Herring maxItems: 32 70cc0f6e96SRob Herring additionalItems: true 71cc0f6e96SRob Herring items: 72cc0f6e96SRob Herring - const: rx 73cc0f6e96SRob Herring - const: tx 74cc0f6e96SRob Herring 75*d94758b3SLinus Walleij resets: 76*d94758b3SLinus Walleij maxItems: 1 77*d94758b3SLinus Walleij 78cc0f6e96SRob HerringpatternProperties: 79cc0f6e96SRob Herring "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$": 80cc0f6e96SRob Herring type: object 81cc0f6e96SRob Herring # SPI slave nodes must be children of the SPI master node and can 82cc0f6e96SRob Herring # contain the following properties. 83cc0f6e96SRob Herring properties: 84cc0f6e96SRob Herring pl022,interface: 85cc0f6e96SRob Herring description: SPI interface type 863d21a460SRob Herring $ref: "/schemas/types.yaml#/definitions/uint32" 873d21a460SRob Herring enum: 88cc0f6e96SRob Herring - 0 # SPI 89cc0f6e96SRob Herring - 1 # Texas Instruments Synchronous Serial Frame Format 90cc0f6e96SRob Herring - 2 # Microwire (Half Duplex) 91cc0f6e96SRob Herring 92cc0f6e96SRob Herring pl022,com-mode: 93cc0f6e96SRob Herring description: Specifies the transfer mode 943d21a460SRob Herring $ref: "/schemas/types.yaml#/definitions/uint32" 953d21a460SRob Herring enum: 96cc0f6e96SRob Herring - 0 # interrupt mode 97cc0f6e96SRob Herring - 1 # polling mode 98cc0f6e96SRob Herring - 2 # DMA mode 99cc0f6e96SRob Herring default: 1 100cc0f6e96SRob Herring 101cc0f6e96SRob Herring pl022,rx-level-trig: 102cc0f6e96SRob Herring description: Rx FIFO watermark level 1033d21a460SRob Herring $ref: "/schemas/types.yaml#/definitions/uint32" 1043d21a460SRob Herring minimum: 0 105cc0f6e96SRob Herring maximum: 4 106cc0f6e96SRob Herring 107cc0f6e96SRob Herring pl022,tx-level-trig: 108cc0f6e96SRob Herring description: Tx FIFO watermark level 1093d21a460SRob Herring $ref: "/schemas/types.yaml#/definitions/uint32" 1103d21a460SRob Herring minimum: 0 111cc0f6e96SRob Herring maximum: 4 112cc0f6e96SRob Herring 113cc0f6e96SRob Herring pl022,ctrl-len: 114cc0f6e96SRob Herring description: Microwire interface - Control length 1153d21a460SRob Herring $ref: "/schemas/types.yaml#/definitions/uint32" 1163d21a460SRob Herring minimum: 0x03 117cc0f6e96SRob Herring maximum: 0x1f 118cc0f6e96SRob Herring 119cc0f6e96SRob Herring pl022,wait-state: 120cc0f6e96SRob Herring description: Microwire interface - Wait state 1213d21a460SRob Herring $ref: "/schemas/types.yaml#/definitions/uint32" 1223d21a460SRob Herring enum: [0, 1] 123cc0f6e96SRob Herring 124cc0f6e96SRob Herring pl022,duplex: 125cc0f6e96SRob Herring description: Microwire interface - Full/Half duplex 1263d21a460SRob Herring $ref: "/schemas/types.yaml#/definitions/uint32" 1273d21a460SRob Herring enum: [0, 1] 128cc0f6e96SRob Herring 129cc0f6e96SRob Herringrequired: 130cc0f6e96SRob Herring - compatible 131cc0f6e96SRob Herring - reg 132cc0f6e96SRob Herring - interrupts 133cc0f6e96SRob Herring 1346fdc6e23SRob HerringunevaluatedProperties: false 1356fdc6e23SRob Herring 136cc0f6e96SRob Herringexamples: 137cc0f6e96SRob Herring - | 138cc0f6e96SRob Herring spi@e0100000 { 139cc0f6e96SRob Herring compatible = "arm,pl022", "arm,primecell"; 140cc0f6e96SRob Herring reg = <0xe0100000 0x1000>; 141cc0f6e96SRob Herring #address-cells = <1>; 142cc0f6e96SRob Herring #size-cells = <0>; 143cc0f6e96SRob Herring interrupts = <0 31 0x4>; 144cc0f6e96SRob Herring dmas = <&dma_controller 23 1>, 145cc0f6e96SRob Herring <&dma_controller 24 0>; 146cc0f6e96SRob Herring dma-names = "rx", "tx"; 147cc0f6e96SRob Herring 148cc0f6e96SRob Herring m25p80@1 { 149cc0f6e96SRob Herring compatible = "st,m25p80"; 150cc0f6e96SRob Herring reg = <1>; 151cc0f6e96SRob Herring spi-max-frequency = <12000000>; 152cc0f6e96SRob Herring spi-cpol; 153cc0f6e96SRob Herring spi-cpha; 154cc0f6e96SRob Herring pl022,interface = <0>; 155cc0f6e96SRob Herring pl022,com-mode = <0x2>; 156cc0f6e96SRob Herring pl022,rx-level-trig = <0>; 157cc0f6e96SRob Herring pl022,tx-level-trig = <0>; 158cc0f6e96SRob Herring pl022,ctrl-len = <0x11>; 159cc0f6e96SRob Herring pl022,wait-state = <0>; 160cc0f6e96SRob Herring pl022,duplex = <0>; 161cc0f6e96SRob Herring }; 162cc0f6e96SRob Herring }; 163cc0f6e96SRob Herring... 164