1164c05f0SSerge Semin# SPDX-License-Identifier: GPL-2.0-only 2164c05f0SSerge Semin%YAML 1.2 3164c05f0SSerge Semin--- 4164c05f0SSerge Semin$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml# 5164c05f0SSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 6164c05f0SSerge Semin 7164c05f0SSerge Semintitle: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface 8164c05f0SSerge Semin 9164c05f0SSerge Seminmaintainers: 10164c05f0SSerge Semin - Mark Brown <broonie@kernel.org> 11164c05f0SSerge Semin 12164c05f0SSerge SeminallOf: 13164c05f0SSerge Semin - $ref: "spi-controller.yaml#" 14164c05f0SSerge Semin - if: 15164c05f0SSerge Semin properties: 16164c05f0SSerge Semin compatible: 17164c05f0SSerge Semin contains: 18164c05f0SSerge Semin enum: 19164c05f0SSerge Semin - mscc,ocelot-spi 20164c05f0SSerge Semin - mscc,jaguar2-spi 21164c05f0SSerge Semin then: 22164c05f0SSerge Semin properties: 23164c05f0SSerge Semin reg: 24164c05f0SSerge Semin minItems: 2 25164c05f0SSerge Semin 26164c05f0SSerge Seminproperties: 27164c05f0SSerge Semin compatible: 28164c05f0SSerge Semin oneOf: 29164c05f0SSerge Semin - description: Generic DW SPI Controller 30164c05f0SSerge Semin enum: 31164c05f0SSerge Semin - snps,dw-apb-ssi 32164c05f0SSerge Semin - snps,dwc-ssi-1.01a 33164c05f0SSerge Semin - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller 34164c05f0SSerge Semin items: 35164c05f0SSerge Semin - enum: 36164c05f0SSerge Semin - mscc,ocelot-spi 37164c05f0SSerge Semin - mscc,jaguar2-spi 38164c05f0SSerge Semin - const: snps,dw-apb-ssi 39*5ce78f44SLars Povlsen - description: Microchip Sparx5 SoC SPI Controller 40*5ce78f44SLars Povlsen const: microchip,sparx5-spi 41164c05f0SSerge Semin - description: Amazon Alpine SPI Controller 42164c05f0SSerge Semin const: amazon,alpine-dw-apb-ssi 43164c05f0SSerge Semin - description: Renesas RZ/N1 SPI Controller 44164c05f0SSerge Semin items: 45164c05f0SSerge Semin - const: renesas,rzn1-spi 46164c05f0SSerge Semin - const: snps,dw-apb-ssi 47164c05f0SSerge Semin - description: Intel Keem Bay SPI Controller 48164c05f0SSerge Semin const: intel,keembay-ssi 49164c05f0SSerge Semin 50164c05f0SSerge Semin reg: 51164c05f0SSerge Semin minItems: 1 52164c05f0SSerge Semin items: 53164c05f0SSerge Semin - description: DW APB SSI controller memory mapped registers 54164c05f0SSerge Semin - description: SPI MST region map 55164c05f0SSerge Semin 56164c05f0SSerge Semin interrupts: 57164c05f0SSerge Semin maxItems: 1 58164c05f0SSerge Semin 59164c05f0SSerge Semin clocks: 60164c05f0SSerge Semin minItems: 1 61164c05f0SSerge Semin items: 62164c05f0SSerge Semin - description: SPI Controller reference clock source 63164c05f0SSerge Semin - description: APB interface clock source 64164c05f0SSerge Semin 65164c05f0SSerge Semin clock-names: 66164c05f0SSerge Semin minItems: 1 67164c05f0SSerge Semin items: 68164c05f0SSerge Semin - const: ssi_clk 69164c05f0SSerge Semin - const: pclk 70164c05f0SSerge Semin 71164c05f0SSerge Semin resets: 72164c05f0SSerge Semin maxItems: 1 73164c05f0SSerge Semin 74164c05f0SSerge Semin reset-names: 75164c05f0SSerge Semin const: spi 76164c05f0SSerge Semin 77164c05f0SSerge Semin reg-io-width: 78164c05f0SSerge Semin $ref: /schemas/types.yaml#/definitions/uint32 79164c05f0SSerge Semin description: I/O register width (in bytes) implemented by this device 80164c05f0SSerge Semin default: 4 81164c05f0SSerge Semin enum: [ 2, 4 ] 82164c05f0SSerge Semin 83164c05f0SSerge Semin num-cs: 84164c05f0SSerge Semin default: 4 85164c05f0SSerge Semin minimum: 1 86164c05f0SSerge Semin maximum: 4 87164c05f0SSerge Semin 88164c05f0SSerge Semin dmas: 89164c05f0SSerge Semin items: 90164c05f0SSerge Semin - description: TX DMA Channel 91164c05f0SSerge Semin - description: RX DMA Channel 92164c05f0SSerge Semin 93164c05f0SSerge Semin dma-names: 94164c05f0SSerge Semin items: 95164c05f0SSerge Semin - const: tx 96164c05f0SSerge Semin - const: rx 97164c05f0SSerge Semin 98*5ce78f44SLars Povlsen rx-sample-delay-ns: 99*5ce78f44SLars Povlsen default: 0 100*5ce78f44SLars Povlsen description: Default value of the rx-sample-delay-ns property. 101*5ce78f44SLars Povlsen This value will be used if the property is not explicitly defined 102*5ce78f44SLars Povlsen for a SPI slave device. See below. 103*5ce78f44SLars Povlsen 104164c05f0SSerge SeminpatternProperties: 105164c05f0SSerge Semin "^.*@[0-9a-f]+$": 106164c05f0SSerge Semin type: object 107164c05f0SSerge Semin properties: 108164c05f0SSerge Semin reg: 109164c05f0SSerge Semin minimum: 0 110164c05f0SSerge Semin maximum: 3 111164c05f0SSerge Semin 112164c05f0SSerge Semin spi-rx-bus-width: 113164c05f0SSerge Semin const: 1 114164c05f0SSerge Semin 115164c05f0SSerge Semin spi-tx-bus-width: 116164c05f0SSerge Semin const: 1 117164c05f0SSerge Semin 118*5ce78f44SLars Povlsen rx-sample-delay-ns: 119*5ce78f44SLars Povlsen description: SPI Rx sample delay offset, unit is nanoseconds. 120*5ce78f44SLars Povlsen The delay from the default sample time before the actual 121*5ce78f44SLars Povlsen sample of the rxd input signal occurs. The "rx_sample_delay" 122*5ce78f44SLars Povlsen is an optional feature of the designware controller, and the 123*5ce78f44SLars Povlsen upper limit is also subject to controller configuration. 124*5ce78f44SLars Povlsen 125164c05f0SSerge SeminunevaluatedProperties: false 126164c05f0SSerge Semin 127164c05f0SSerge Seminrequired: 128164c05f0SSerge Semin - compatible 129164c05f0SSerge Semin - reg 130164c05f0SSerge Semin - "#address-cells" 131164c05f0SSerge Semin - "#size-cells" 132164c05f0SSerge Semin - interrupts 133164c05f0SSerge Semin - clocks 134164c05f0SSerge Semin 135164c05f0SSerge Seminexamples: 136164c05f0SSerge Semin - | 137164c05f0SSerge Semin spi@fff00000 { 138164c05f0SSerge Semin compatible = "snps,dw-apb-ssi"; 139164c05f0SSerge Semin reg = <0xfff00000 0x1000>; 140164c05f0SSerge Semin #address-cells = <1>; 141164c05f0SSerge Semin #size-cells = <0>; 142164c05f0SSerge Semin interrupts = <0 154 4>; 143164c05f0SSerge Semin clocks = <&spi_m_clk>; 144164c05f0SSerge Semin num-cs = <2>; 145164c05f0SSerge Semin cs-gpios = <&gpio0 13 0>, 146164c05f0SSerge Semin <&gpio0 14 0>; 147*5ce78f44SLars Povlsen rx-sample-delay-ns = <3>; 148*5ce78f44SLars Povlsen spi-flash@1 { 149*5ce78f44SLars Povlsen compatible = "spi-nand"; 150*5ce78f44SLars Povlsen reg = <1>; 151*5ce78f44SLars Povlsen rx-sample-delay-ns = <7>; 152*5ce78f44SLars Povlsen }; 153164c05f0SSerge Semin }; 154164c05f0SSerge Semin... 155