1*164c05f0SSerge Semin# SPDX-License-Identifier: GPL-2.0-only 2*164c05f0SSerge Semin%YAML 1.2 3*164c05f0SSerge Semin--- 4*164c05f0SSerge Semin$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml# 5*164c05f0SSerge Semin$schema: http://devicetree.org/meta-schemas/core.yaml# 6*164c05f0SSerge Semin 7*164c05f0SSerge Semintitle: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface 8*164c05f0SSerge Semin 9*164c05f0SSerge Seminmaintainers: 10*164c05f0SSerge Semin - Mark Brown <broonie@kernel.org> 11*164c05f0SSerge Semin 12*164c05f0SSerge SeminallOf: 13*164c05f0SSerge Semin - $ref: "spi-controller.yaml#" 14*164c05f0SSerge Semin - if: 15*164c05f0SSerge Semin properties: 16*164c05f0SSerge Semin compatible: 17*164c05f0SSerge Semin contains: 18*164c05f0SSerge Semin enum: 19*164c05f0SSerge Semin - mscc,ocelot-spi 20*164c05f0SSerge Semin - mscc,jaguar2-spi 21*164c05f0SSerge Semin then: 22*164c05f0SSerge Semin properties: 23*164c05f0SSerge Semin reg: 24*164c05f0SSerge Semin minItems: 2 25*164c05f0SSerge Semin 26*164c05f0SSerge Seminproperties: 27*164c05f0SSerge Semin compatible: 28*164c05f0SSerge Semin oneOf: 29*164c05f0SSerge Semin - description: Generic DW SPI Controller 30*164c05f0SSerge Semin enum: 31*164c05f0SSerge Semin - snps,dw-apb-ssi 32*164c05f0SSerge Semin - snps,dwc-ssi-1.01a 33*164c05f0SSerge Semin - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller 34*164c05f0SSerge Semin items: 35*164c05f0SSerge Semin - enum: 36*164c05f0SSerge Semin - mscc,ocelot-spi 37*164c05f0SSerge Semin - mscc,jaguar2-spi 38*164c05f0SSerge Semin - const: snps,dw-apb-ssi 39*164c05f0SSerge Semin - description: Amazon Alpine SPI Controller 40*164c05f0SSerge Semin const: amazon,alpine-dw-apb-ssi 41*164c05f0SSerge Semin - description: Renesas RZ/N1 SPI Controller 42*164c05f0SSerge Semin items: 43*164c05f0SSerge Semin - const: renesas,rzn1-spi 44*164c05f0SSerge Semin - const: snps,dw-apb-ssi 45*164c05f0SSerge Semin - description: Intel Keem Bay SPI Controller 46*164c05f0SSerge Semin const: intel,keembay-ssi 47*164c05f0SSerge Semin 48*164c05f0SSerge Semin reg: 49*164c05f0SSerge Semin minItems: 1 50*164c05f0SSerge Semin items: 51*164c05f0SSerge Semin - description: DW APB SSI controller memory mapped registers 52*164c05f0SSerge Semin - description: SPI MST region map 53*164c05f0SSerge Semin 54*164c05f0SSerge Semin interrupts: 55*164c05f0SSerge Semin maxItems: 1 56*164c05f0SSerge Semin 57*164c05f0SSerge Semin clocks: 58*164c05f0SSerge Semin minItems: 1 59*164c05f0SSerge Semin items: 60*164c05f0SSerge Semin - description: SPI Controller reference clock source 61*164c05f0SSerge Semin - description: APB interface clock source 62*164c05f0SSerge Semin 63*164c05f0SSerge Semin clock-names: 64*164c05f0SSerge Semin minItems: 1 65*164c05f0SSerge Semin items: 66*164c05f0SSerge Semin - const: ssi_clk 67*164c05f0SSerge Semin - const: pclk 68*164c05f0SSerge Semin 69*164c05f0SSerge Semin resets: 70*164c05f0SSerge Semin maxItems: 1 71*164c05f0SSerge Semin 72*164c05f0SSerge Semin reset-names: 73*164c05f0SSerge Semin const: spi 74*164c05f0SSerge Semin 75*164c05f0SSerge Semin reg-io-width: 76*164c05f0SSerge Semin $ref: /schemas/types.yaml#/definitions/uint32 77*164c05f0SSerge Semin description: I/O register width (in bytes) implemented by this device 78*164c05f0SSerge Semin default: 4 79*164c05f0SSerge Semin enum: [ 2, 4 ] 80*164c05f0SSerge Semin 81*164c05f0SSerge Semin num-cs: 82*164c05f0SSerge Semin default: 4 83*164c05f0SSerge Semin minimum: 1 84*164c05f0SSerge Semin maximum: 4 85*164c05f0SSerge Semin 86*164c05f0SSerge Semin dmas: 87*164c05f0SSerge Semin items: 88*164c05f0SSerge Semin - description: TX DMA Channel 89*164c05f0SSerge Semin - description: RX DMA Channel 90*164c05f0SSerge Semin 91*164c05f0SSerge Semin dma-names: 92*164c05f0SSerge Semin items: 93*164c05f0SSerge Semin - const: tx 94*164c05f0SSerge Semin - const: rx 95*164c05f0SSerge Semin 96*164c05f0SSerge SeminpatternProperties: 97*164c05f0SSerge Semin "^.*@[0-9a-f]+$": 98*164c05f0SSerge Semin type: object 99*164c05f0SSerge Semin properties: 100*164c05f0SSerge Semin reg: 101*164c05f0SSerge Semin minimum: 0 102*164c05f0SSerge Semin maximum: 3 103*164c05f0SSerge Semin 104*164c05f0SSerge Semin spi-rx-bus-width: 105*164c05f0SSerge Semin const: 1 106*164c05f0SSerge Semin 107*164c05f0SSerge Semin spi-tx-bus-width: 108*164c05f0SSerge Semin const: 1 109*164c05f0SSerge Semin 110*164c05f0SSerge SeminunevaluatedProperties: false 111*164c05f0SSerge Semin 112*164c05f0SSerge Seminrequired: 113*164c05f0SSerge Semin - compatible 114*164c05f0SSerge Semin - reg 115*164c05f0SSerge Semin - "#address-cells" 116*164c05f0SSerge Semin - "#size-cells" 117*164c05f0SSerge Semin - interrupts 118*164c05f0SSerge Semin - clocks 119*164c05f0SSerge Semin 120*164c05f0SSerge Seminexamples: 121*164c05f0SSerge Semin - | 122*164c05f0SSerge Semin spi@fff00000 { 123*164c05f0SSerge Semin compatible = "snps,dw-apb-ssi"; 124*164c05f0SSerge Semin reg = <0xfff00000 0x1000>; 125*164c05f0SSerge Semin #address-cells = <1>; 126*164c05f0SSerge Semin #size-cells = <0>; 127*164c05f0SSerge Semin interrupts = <0 154 4>; 128*164c05f0SSerge Semin clocks = <&spi_m_clk>; 129*164c05f0SSerge Semin num-cs = <2>; 130*164c05f0SSerge Semin cs-gpios = <&gpio0 13 0>, 131*164c05f0SSerge Semin <&gpio0 14 0>; 132*164c05f0SSerge Semin }; 133*164c05f0SSerge Semin... 134