1*644c2dcfSMaruthi Srinivas BayyavarapuDevice-Tree bindings for Xilinx I2S PL block 2*644c2dcfSMaruthi Srinivas Bayyavarapu 3*644c2dcfSMaruthi Srinivas BayyavarapuThe IP supports I2S based playback/capture audio 4*644c2dcfSMaruthi Srinivas Bayyavarapu 5*644c2dcfSMaruthi Srinivas BayyavarapuRequired property: 6*644c2dcfSMaruthi Srinivas Bayyavarapu - compatible: "xlnx,i2s-transmitter-1.0" for playback and 7*644c2dcfSMaruthi Srinivas Bayyavarapu "xlnx,i2s-receiver-1.0" for capture 8*644c2dcfSMaruthi Srinivas Bayyavarapu 9*644c2dcfSMaruthi Srinivas BayyavarapuRequired property common to both I2S playback and capture: 10*644c2dcfSMaruthi Srinivas Bayyavarapu - reg: Base address and size of the IP core instance. 11*644c2dcfSMaruthi Srinivas Bayyavarapu - xlnx,dwidth: sample data width. Can be any of 16, 24. 12*644c2dcfSMaruthi Srinivas Bayyavarapu - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4. 13*644c2dcfSMaruthi Srinivas Bayyavarapu supported channels = 2 * xlnx,num-channels 14*644c2dcfSMaruthi Srinivas Bayyavarapu 15*644c2dcfSMaruthi Srinivas BayyavarapuExample: 16*644c2dcfSMaruthi Srinivas Bayyavarapu 17*644c2dcfSMaruthi Srinivas Bayyavarapu i2s_receiver@a0080000 { 18*644c2dcfSMaruthi Srinivas Bayyavarapu compatible = "xlnx,i2s-receiver-1.0"; 19*644c2dcfSMaruthi Srinivas Bayyavarapu reg = <0x0 0xa0080000 0x0 0x10000>; 20*644c2dcfSMaruthi Srinivas Bayyavarapu xlnx,dwidth = <0x18>; 21*644c2dcfSMaruthi Srinivas Bayyavarapu xlnx,num-channels = <1>; 22*644c2dcfSMaruthi Srinivas Bayyavarapu }; 23*644c2dcfSMaruthi Srinivas Bayyavarapu i2s_transmitter@a0090000 { 24*644c2dcfSMaruthi Srinivas Bayyavarapu compatible = "xlnx,i2s-transmitter-1.0"; 25*644c2dcfSMaruthi Srinivas Bayyavarapu reg = <0x0 0xa0090000 0x0 0x10000>; 26*644c2dcfSMaruthi Srinivas Bayyavarapu xlnx,dwidth = <0x18>; 27*644c2dcfSMaruthi Srinivas Bayyavarapu xlnx,num-channels = <1>; 28*644c2dcfSMaruthi Srinivas Bayyavarapu }; 29