1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Audio Graph based Tegra sound card driver 8 9description: | 10 This is based on generic audio graph card driver along with additional 11 customizations for Tegra platforms. It uses the same bindings with 12 additional standard clock DT bindings required for Tegra. 13 14maintainers: 15 - Jon Hunter <jonathanh@nvidia.com> 16 - Sameer Pujar <spujar@nvidia.com> 17 18allOf: 19 - $ref: audio-graph.yaml# 20 21properties: 22 compatible: 23 enum: 24 - nvidia,tegra210-audio-graph-card 25 - nvidia,tegra186-audio-graph-card 26 27 clocks: 28 minItems: 2 29 30 clock-names: 31 minItems: 2 32 items: 33 - const: pll_a 34 - const: plla_out0 35 36 assigned-clocks: 37 minItems: 1 38 maxItems: 3 39 40 assigned-clock-parents: 41 minItems: 1 42 maxItems: 3 43 44 assigned-clock-rates: 45 minItems: 1 46 maxItems: 3 47 48required: 49 - clocks 50 - clock-names 51 - assigned-clocks 52 - assigned-clock-parents 53 54unevaluatedProperties: false 55 56examples: 57 - | 58 #include<dt-bindings/clock/tegra210-car.h> 59 60 tegra_sound { 61 compatible = "nvidia,tegra210-audio-graph-card"; 62 63 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 64 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 65 clock-names = "pll_a", "plla_out0"; 66 67 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 68 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 69 <&tegra_car TEGRA210_CLK_EXTERN1>; 70 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 71 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 72 73 dais = /* FE */ 74 <&admaif1_port>, 75 /* Router */ 76 <&xbar_i2s1_port>, 77 /* I/O DAP Ports */ 78 <&i2s1_port>; 79 80 label = "jetson-tx1-ape"; 81 }; 82 83 // The ports are defined for AHUB and its child devices. 84 ahub@702d0800 { 85 compatible = "nvidia,tegra210-ahub"; 86 reg = <0x702d0800 0x800>; 87 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 88 clock-names = "ahub"; 89 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 90 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges = <0x702d0000 0x702d0000 0x0000e400>; 94 95 ports { 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 port@0 { 100 reg = <0x0>; 101 xbar_admaif1_ep: endpoint { 102 remote-endpoint = <&admaif1_ep>; 103 }; 104 }; 105 106 // ... 107 108 xbar_i2s1_port: port@a { 109 reg = <0xa>; 110 xbar_i2s1_ep: endpoint { 111 remote-endpoint = <&i2s1_cif_ep>; 112 }; 113 }; 114 }; 115 116 admaif@702d0000 { 117 compatible = "nvidia,tegra210-admaif"; 118 reg = <0x702d0000 0x800>; 119 dmas = <&adma 1>, <&adma 1>, 120 <&adma 2>, <&adma 2>, 121 <&adma 3>, <&adma 3>, 122 <&adma 4>, <&adma 4>, 123 <&adma 5>, <&adma 5>, 124 <&adma 6>, <&adma 6>, 125 <&adma 7>, <&adma 7>, 126 <&adma 8>, <&adma 8>, 127 <&adma 9>, <&adma 9>, 128 <&adma 10>, <&adma 10>; 129 dma-names = "rx1", "tx1", 130 "rx2", "tx2", 131 "rx3", "tx3", 132 "rx4", "tx4", 133 "rx5", "tx5", 134 "rx6", "tx6", 135 "rx7", "tx7", 136 "rx8", "tx8", 137 "rx9", "tx9", 138 "rx10", "tx10"; 139 140 ports { 141 #address-cells = <1>; 142 #size-cells = <0>; 143 144 admaif1_port: port@0 { 145 reg = <0x0>; 146 admaif1_ep: endpoint { 147 remote-endpoint = <&xbar_admaif1_ep>; 148 }; 149 }; 150 151 // More ADMAIF ports to follow 152 }; 153 }; 154 155 i2s@702d1000 { 156 compatible = "nvidia,tegra210-i2s"; 157 clocks = <&tegra_car TEGRA210_CLK_I2S0>; 158 clock-names = "i2s"; 159 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 160 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 161 assigned-clock-rates = <1536000>; 162 reg = <0x702d1000 0x100>; 163 164 ports { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 port@0 { 169 reg = <0x0>; 170 171 i2s1_cif_ep: endpoint { 172 remote-endpoint = <&xbar_i2s1_ep>; 173 }; 174 }; 175 176 i2s1_port: port@1 { 177 reg = <0x1>; 178 179 i2s1_dap: endpoint { 180 dai-format = "i2s"; 181 }; 182 }; 183 }; 184 }; 185 }; 186 187... 188