143d24e76SNicolin ChenFreescale Enhanced Serial Audio Interface (ESAI) Controller 243d24e76SNicolin Chen 343d24e76SNicolin ChenThe Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port 443d24e76SNicolin Chenfor serial communication with a variety of serial devices, including industry 543d24e76SNicolin Chenstandard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and 643d24e76SNicolin Chenother DSPs. It has up to six transmitters and four receivers. 743d24e76SNicolin Chen 843d24e76SNicolin ChenRequired properties: 943d24e76SNicolin Chen 109ea08f2aSShengjiu Wang - compatible : Compatible list, should contain one of the following 119ea08f2aSShengjiu Wang compatibles: 129ea08f2aSShengjiu Wang "fsl,imx35-esai", 139ea08f2aSShengjiu Wang "fsl,vf610-esai", 149ea08f2aSShengjiu Wang "fsl,imx6ull-esai", 15d59628b3SShengjiu Wang "fsl,imx8qm-esai", 1643d24e76SNicolin Chen 1743d24e76SNicolin Chen - reg : Offset and length of the register set for the device. 1843d24e76SNicolin Chen 1943d24e76SNicolin Chen - interrupts : Contains the spdif interrupt. 2043d24e76SNicolin Chen 2143d24e76SNicolin Chen - dmas : Generic dma devicetree binding as described in 2243d24e76SNicolin Chen Documentation/devicetree/bindings/dma/dma.txt. 2343d24e76SNicolin Chen 2443d24e76SNicolin Chen - dma-names : Two dmas have to be defined, "tx" and "rx". 2543d24e76SNicolin Chen 2643d24e76SNicolin Chen - clocks : Contains an entry for each entry in clock-names. 2743d24e76SNicolin Chen 2843d24e76SNicolin Chen - clock-names : Includes the following entries: 2943d24e76SNicolin Chen "core" The core clock used to access registers 3073a2cd91SNicolin Chen "extal" The esai baud clock for esai controller used to 3173a2cd91SNicolin Chen derive HCK, SCK and FS. 3273a2cd91SNicolin Chen "fsys" The system clock derived from ahb clock used to 3373a2cd91SNicolin Chen derive HCK, SCK and FS. 34a2a4d604SShengjiu Wang "spba" The spba clock is required when ESAI is placed as a 35a2a4d604SShengjiu Wang bus slave of the Shared Peripheral Bus and when two 36a2a4d604SShengjiu Wang or more bus masters (CPU, DMA or DSP) try to access 37a2a4d604SShengjiu Wang it. This property is optional depending on the SoC 38a2a4d604SShengjiu Wang design. 3943d24e76SNicolin Chen 4073a2cd91SNicolin Chen - fsl,fifo-depth : The number of elements in the transmit and receive 4173a2cd91SNicolin Chen FIFOs. This number is the maximum allowed value for 4273a2cd91SNicolin Chen TFCR[TFWM] or RFCR[RFWM]. 4343d24e76SNicolin Chen 4443d24e76SNicolin Chen - fsl,esai-synchronous: This is a boolean property. If present, indicating 4573a2cd91SNicolin Chen that ESAI would work in the synchronous mode, which 4673a2cd91SNicolin Chen means all the settings for Receiving would be 47*47aab533SBjorn Helgaas duplicated from Transmission related registers. 4843d24e76SNicolin Chen 499ff3036aSFabio EstevamOptional properties: 509ff3036aSFabio Estevam 5173a2cd91SNicolin Chen - big-endian : If this property is absent, the native endian mode 5273a2cd91SNicolin Chen will be in use as default, or the big endian mode 5373a2cd91SNicolin Chen will be in use for all the device registers. 54eaba603fSXiubo Li 5543d24e76SNicolin ChenExample: 5643d24e76SNicolin Chen 5748c926cdSMarco Franchiesai: esai@2024000 { 5843d24e76SNicolin Chen compatible = "fsl,imx35-esai"; 5943d24e76SNicolin Chen reg = <0x02024000 0x4000>; 6043d24e76SNicolin Chen interrupts = <0 51 0x04>; 6143d24e76SNicolin Chen clocks = <&clks 208>, <&clks 118>, <&clks 208>; 6243d24e76SNicolin Chen clock-names = "core", "extal", "fsys"; 6343d24e76SNicolin Chen dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; 6443d24e76SNicolin Chen dma-names = "rx", "tx"; 6543d24e76SNicolin Chen fsl,fifo-depth = <128>; 6643d24e76SNicolin Chen fsl,esai-synchronous; 67eaba603fSXiubo Li big-endian; 6843d24e76SNicolin Chen}; 69